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# CUDA Driver API functions supported by HIP
## **1. Data types used by CUDA driver**
| **type** | **CUDA** | **HIP** | **CUDA description** |
|-------------:|---------------------------------------------------------------|------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| struct | `CUDA_ARRAY3D_DESCRIPTOR` | | |
| struct | `CUDA_ARRAY_DESCRIPTOR` | | |
| struct | `CUDA_MEMCPY2D` | | |
| struct | `CUDA_MEMCPY3D` | | |
| struct | `CUDA_MEMCPY3D_PEER` | | |
| struct | `CUDA_POINTER_ATTRIBUTE_P2P_TOKENS` | | |
| struct | `CUDA_RESOURCE_DESC` | | |
| struct | `CUDA_RESOURCE_VIEW_DESC` | | |
| struct | `CUdevprop` | `hipDeviceProp_t` | |
| struct | `CUipcEventHandle` | | |
| struct | `CUipcMemHandle` | | |
| enum |***`CUaddress_mode`*** | | Texture reference addressing modes |
| 0 |*`CU_TR_ADDRESS_MODE_WRAP`* | | Wrapping address mode |
| 1 |*`CU_TR_ADDRESS_MODE_CLAMP`* | | Clamp to edge address mode |
| 2 |*`CU_TR_ADDRESS_MODE_MIRROR`* | | Mirror address mode |
| 3 |*`CU_TR_ADDRESS_MODE_BORDER`* | | Border address mode |
| enum |***`CUarray_cubemap_face`*** | | Array indices for cube faces |
| 0x00 |*`CU_CUBEMAP_FACE_POSITIVE_X`* | | Positive X face of cubemap |
| 0x01 |*`CU_CUBEMAP_FACE_NEGATIVE_X`* | | Negative X face of cubemap |
| 0x02 |*`CU_CUBEMAP_FACE_POSITIVE_Y`* | | Positive Y face of cubemap |
| 0x03 |*`CU_CUBEMAP_FACE_NEGATIVE_Y`* | | Negative Y face of cubemap |
| 0x04 |*`CU_CUBEMAP_FACE_POSITIVE_Z`* | | Positive Z face of cubemap |
| 0x05 |*`CU_CUBEMAP_FACE_NEGATIVE_Z`* | | Negative Z face of cubemap |
| enum |***`CUarray_format`*** | | Array formats |
| 0x01 |*`CU_AD_FORMAT_UNSIGNED_INT8`* | | Unsigned 8-bit integers |
| 0x02 |*`CU_AD_FORMAT_UNSIGNED_INT16`* | | Unsigned 16-bit integers |
| 0x03 |*`CU_AD_FORMAT_UNSIGNED_INT32`* | | Unsigned 32-bit integers |
| 0x08 |*`CU_AD_FORMAT_SIGNED_INT8`* | | Signed 8-bit integers |
| 0x09 |*`CU_AD_FORMAT_SIGNED_INT16`* | | Signed 16-bit integers |
| 0x0a |*`CU_AD_FORMAT_SIGNED_INT32`* | | Signed 32-bit integers |
| 0x10 |*`CU_AD_FORMAT_HALF`* | | 16-bit floating point |
| 0x20 |*`CU_AD_FORMAT_FLOAT`* | | 32-bit floating point |
| enum |***`CUctx_flags`*** | | Context creation flags |
| 0x00 |*`CU_CTX_SCHED_AUTO`* | | Automatic scheduling |
| 0x01 |*`CU_CTX_SCHED_SPIN`* | | Set spin as default scheduling |
| 0x02 |*`CU_CTX_SCHED_YIELD`* | | Set yield as default scheduling |
| 0x04 |*`CU_CTX_SCHED_BLOCKING_SYNC`* | | Set blocking synchronization as default scheduling |
| 0x04 |*`CU_CTX_BLOCKING_SYNC`* | | Set blocking synchronization as default scheduling Deprecated. This flag was deprecated as of CUDA 4.0 and was replaced with CU_CTX_SCHED_BLOCKING_SYNC.|
| 0x07 |*`CU_CTX_SCHED_MASK`* | | |
| 0x08 |*`CU_CTX_MAP_HOST`* | | Support mapped pinned allocations |
| 0x10 |*`CU_CTX_LMEM_RESIZE_TO_MAX`* | | Keep local memory allocation after launch |
| 0x1f |*`CU_CTX_FLAGS_MASK`* | | |
| enum |***`CUdevice_attribute`*** | | Device properties |
| 1 |*`CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK`* |*`hipDeviceAttributeMaxThreadsPerBlock`* | Maximum number of threads per block |
| 2 |*`CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_X`* |*`hipDeviceAttributeMaxBlockDimX`* | Maximum block dimension X |
| 3 |*`CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Y`* |*`hipDeviceAttributeMaxBlockDimY`* | Maximum block dimension Y |
| 4 |*`CU_DEVICE_ATTRIBUTE_MAX_BLOCK_DIM_Z`* |*`hipDeviceAttributeMaxBlockDimZ`* | Maximum block dimension Z |
| 5 |*`CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X`* |*`hipDeviceAttributeMaxGridDimX`* | Maximum grid dimension X |
| 6 |*`CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Y`* |*`hipDeviceAttributeMaxGridDimY`* | Maximum grid dimension Y |
| 7 |*`CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_Z`* |*`hipDeviceAttributeMaxGridDimZ`* | Maximum grid dimension Y |
| 8 |*`CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK`* |*`hipDeviceAttributeMaxSharedMemoryPerBlock`* | Maximum shared memory available per block in bytes |
| 8 |*`CU_DEVICE_ATTRIBUTE_SHARED_MEMORY_PER_BLOCK`* |*`hipDeviceAttributeMaxSharedMemoryPerBlock`* | Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK |
| 9 |*`CU_DEVICE_ATTRIBUTE_TOTAL_CONSTANT_MEMORY`* |*`hipDeviceAttributeTotalConstantMemory`* | Memory available on device for __constant__ variables in a CUDA C kernel in bytes |
| 10 |*`CU_DEVICE_ATTRIBUTE_WARP_SIZE`* |*`hipDeviceAttributeWarpSize`* | Warp size in threads |
| 11 |*`CU_DEVICE_ATTRIBUTE_MAX_PITCH`* | | Maximum pitch in bytes allowed by memory copies |
| 12 |*`CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK`* |*`hipDeviceAttributeMaxRegistersPerBlock`* | Maximum number of 32-bit registers available per block |
| 12 |*`CU_DEVICE_ATTRIBUTE_REGISTERS_PER_BLOCK`* |*`hipDeviceAttributeMaxRegistersPerBlock`* | Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK |
| 13 |*`CU_DEVICE_ATTRIBUTE_CLOCK_RATE`* |*`hipDeviceAttributeClockRate`* | Typical clock frequency in kilohertz |
| 14 |*`CU_DEVICE_ATTRIBUTE_TEXTURE_ALIGNMENT`* | | Alignment requirement for textures |
| 15 |*`CU_DEVICE_ATTRIBUTE_GPU_OVERLAP`* | | Device can possibly copy memory and execute a kernel concurrently. Deprecated. Use instead CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT|
| 16 |*`CU_DEVICE_ATTRIBUTE_MULTIPROCESSOR_COUNT`* |*`hipDeviceAttributeMultiprocessorCount`* | Number of multiprocessors on device |
| 17 |*`CU_DEVICE_ATTRIBUTE_KERNEL_EXEC_TIMEOUT`* | | Specifies whether there is a run time limit on kernels |
| 18 |*`CU_DEVICE_ATTRIBUTE_INTEGRATED`* | | Device is integrated with host memory |
| 19 |*`CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY`* | | Device can map host memory into CUDA address space |
| 20 |*`CU_DEVICE_ATTRIBUTE_COMPUTE_MODE`* |*`hipDeviceAttributeComputeMode`* | Compute mode (See CUcomputemode for details) |
| 21 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_WIDTH`* | | Maximum 1D texture width |
| 22 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_WIDTH`* | | Maximum 2D texture width |
| 23 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_HEIGHT`* | | Maximum 2D texture height |
| 24 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH`* | | Maximum 3D texture width |
| 25 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT`* | | Maximum 3D texture height |
| 26 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH`* | | Maximum 3D texture depth |
| 27 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH`* | | Maximum 2D layered texture width |
| 28 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT`* | | Maximum 2D layered texture height |
| 29 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS`* | | Maximum layers in a 2D layered texture |
| 27 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH`* | | Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH |
| 28 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT`* | | Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT |
| 29 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES`* | | Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS |
| 30 |*`CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT`* | | Alignment requirement for surfaces |
| 31 |*`CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS`* |*`hipDeviceAttributeConcurrentKernels`* | Device can possibly execute multiple kernels concurrently |
| 32 |*`CU_DEVICE_ATTRIBUTE_ECC_ENABLED`* | | Device has ECC support enabled |
| 33 |*`CU_DEVICE_ATTRIBUTE_PCI_BUS_ID`* |*`hipDeviceAttributePciBusId`* | PCI bus ID of the device |
| 34 |*`CU_DEVICE_ATTRIBUTE_PCI_DEVICE_ID`* |*`hipDeviceAttributePciDeviceId`* | PCI device ID of the device |
| 35 |*`CU_DEVICE_ATTRIBUTE_TCC_DRIVER`* | | Device is using TCC driver model |
| 36 |*`CU_DEVICE_ATTRIBUTE_MEMORY_CLOCK_RATE`* |*`hipDeviceAttributeMemoryClockRate`* | Peak memory clock frequency in kilohertz |
| 37 |*`CU_DEVICE_ATTRIBUTE_GLOBAL_MEMORY_BUS_WIDTH`* |*`hipDeviceAttributeMemoryBusWidth`* | Global memory bus width in bits |
| 38 |*`CU_DEVICE_ATTRIBUTE_L2_CACHE_SIZE`* |*`hipDeviceAttributeL2CacheSize`* | Size of L2 cache in bytes |
| 39 |*`CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_MULTIPROCESSOR`* |*`hipDeviceAttributeMaxThreadsPerMultiProcessor`* | Maximum resident threads per multiprocessor |
| 40 |*`CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT`* | | Number of asynchronous engines |
| 41 |*`CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING`* | | Device shares a unified address space with the host |
| 42 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH`* | | Maximum 1D layered texture width |
| 43 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS`* | | Maximum layers in a 1D layered texture |
| 44 |*`CU_DEVICE_ATTRIBUTE_CAN_TEX2D_GATHER`* | | Deprecated, do not use |
| 45 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH`* | | Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set |
| 46 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT`* | | Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set |
| 47 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE`* | | Alternate maximum 3D texture width |
| 48 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE`* | | Alternate maximum 3D texture height |
| 49 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE`* | | Alternate maximum 3D texture depth |
| 50 |*`CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID`* | | PCI domain ID of the device |
| 51 |*`CU_DEVICE_ATTRIBUTE_TEXTURE_PITCH_ALIGNMENT`* | | Pitch alignment requirement for textures |
| 52 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH`* | | Maximum cubemap texture width/height |
| 53 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH`* | | Maximum cubemap layered texture width/height |
| 54 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS`* | | Maximum layers in a cubemap layered texture |
| 55 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH`* | | Maximum 1D surface width |
| 56 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH`* | | Maximum 2D surface width |
| 57 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT`* | | Maximum 2D surface height |
| 58 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH`* | | Maximum 3D surface width |
| 59 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT`* | | Maximum 3D surface height |
| 60 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH`* | | Maximum 3D surface depth |
| 61 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH`* | | Maximum 1D layered surface width |
| 62 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS`* | | Maximum layers in a 1D layered surface |
| 63 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH`* | | Maximum 2D layered surface width |
| 64 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT`* | | Maximum 2D layered surface height |
| 65 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS`* | | Maximum layers in a 2D layered surface |
| 66 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH`* | | Maximum cubemap surface width |
| 67 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH`* | | Maximum cubemap layered surface width |
| 68 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS`* | | Maximum layers in a cubemap layered surface |
| 69 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH`* | | Maximum 1D linear texture width |
| 70 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH`* | | Maximum 2D linear texture width |
| 71 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT`* | | Maximum 2D linear texture height |
| 72 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH`* | | Maximum 2D linear texture pitch in bytes |
| 73 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH`* | | Maximum mipmapped 2D texture width |
| 74 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT`* | | Maximum mipmapped 2D texture height |
| 75 |*`CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR`* |*`hipDeviceAttributeComputeCapabilityMajor`* | Major compute capability version number |
| 76 |*`CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR`* |*`hipDeviceAttributeComputeCapabilityMinor`* | Minor compute capability version number |
| 77 |*`CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH`* | | Maximum mipmapped 1D texture width |
| 78 |*`CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED`* | | Device supports stream priorities |
| 79 |*`CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED`* | | Device supports caching globals in L1 |
| 80 |*`CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED`* | | Device supports caching locals in L1 |
| 81 |*`CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_MULTIPROCESSOR`* |*`hipDeviceAttributeMaxSharedMemoryPerMultiprocessor`* | Maximum shared memory available per multiprocessor in bytes |
| 82 |*`CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR`* | | Maximum number of 32-bit registers available per multiprocessor |
| 83 |*`CU_DEVICE_ATTRIBUTE_MANAGED_MEMORY`* |*`hipDeviceAttributeManagedMemory`* | Device can allocate managed memory on this system |
| 84 |*`CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD`* | | Device is on a multi-GPU board |
| 85 |*`CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID`* | | Unique id for a group of devices on the same multi-GPU board |
| 86 |*`CU_DEVICE_ATTRIBUTE_MAX`* | | |
| enum |***`CUevent_flags`*** | | Event creation flags |
| 0x00 |*`CU_EVENT_DEFAULT`* |*`hipEventDefault`* | Default event flag |
| 0x01 |*`CU_EVENT_BLOCKING_SYNC`* |*`hipEventBlockingSync`* | Event uses blocking synchronization |
| 0x02 |*`CU_EVENT_DISABLE_TIMING`* |*`hipEventDisableTiming`* | Event will not record timing data |
| 0x04 |*`CU_EVENT_INTERPROCESS`* |*`hipEventInterprocess`* | Event is suitable for interprocess use. CU_EVENT_DISABLE_TIMING must be set |
| enum |***`CUfilter_mode`*** |***`hipTextureFilterMode`*** | Texture reference filtering modes |
| 0 |*`CU_TR_FILTER_MODE_POINT`* |*`hipFilterModePoint`* | Point filter mode |
| 1 |*`CU_TR_FILTER_MODE_LINEAR`* |*`hipFilterModeLinear`* | Linear filter mode |
| enum |***`CUfunc_cache`*** |***`hipFuncCache`*** | Function cache configurations |
| 0x00 |*`CU_FUNC_CACHE_PREFER_NONE`* |*`hipFuncCachePreferNone`* | no preference for shared memory or L1 (default) |
| 0x01 |*`CU_FUNC_CACHE_PREFER_SHARED`* |*`hipFuncCachePreferShared`* | prefer larger shared memory and smaller L1 cache |
| 0x02 |*`CU_FUNC_CACHE_PREFER_L1`* |*`hipFuncCachePreferL1`* | prefer larger L1 cache and smaller shared memory |
| 0x03 |*`CU_FUNC_CACHE_PREFER_EQUAL`* |*`hipFuncCachePreferEqual`* | prefer equal sized L1 cache and shared memory |
| enum |***`CUfunction_attribute`*** | | Function properties |
| 0 |*`CU_FUNC_ATTRIBUTE_MAX_THREADS_PER_BLOCK`* | | The maximum number of threads per block, beyond which a launch of the function would fail. This number depends on both the function and the device on which the function is currently loaded. |
| 1 |*`CU_FUNC_ATTRIBUTE_SHARED_SIZE_BYTES`* | | The size in bytes of statically-allocated shared memory required by this function. This does not include dynamically-allocated shared memory requested by the user at runtime. |
| 2 |*`CU_FUNC_ATTRIBUTE_CONST_SIZE_BYTES`* | | The size in bytes of user-allocated constant memory required by this function. |
| 3 |*`CU_FUNC_ATTRIBUTE_LOCAL_SIZE_BYTES`* | | The size in bytes of local memory used by each thread of this function. |
| 4 |*`CU_FUNC_ATTRIBUTE_NUM_REGS`* | | The number of registers used by each thread of this function. |
| 5 |*`CU_FUNC_ATTRIBUTE_PTX_VERSION`* | | The PTX virtual architecture version for which the function was compiled. This value is the major PTX version * 10 + the minor PTX version, so a PTX version 1.3 function would return the value 13. Note that this may return the undefined value of 0 for cubins compiled prior to CUDA 3.0. |
| 6 |*`CU_FUNC_ATTRIBUTE_BINARY_VERSION`* | | The binary architecture version for which the function was compiled. This value is the major binary version * 10 + the minor binary version, so a binary version 1.3 function would return the value 13. Note that this will return a value of 10 for legacy cubins that do not have a properly-encoded binary architecture version. |
| 7 |*`CU_FUNC_ATTRIBUTE_CACHE_MODE_CA`* | | The attribute to indicate whether the function has been compiled with user specified option "-Xptxas --dlcm=ca" set. |
| 8 |*`CU_FUNC_ATTRIBUTE_MAX`* | | |
| enum |***`CUgraphicsMapResourceFlags`*** | | Flags for mapping and unmapping interop resources |
| 0x00 |*`CU_GRAPHICS_MAP_RESOURCE_FLAGS_NONE`* | | |
| 0x01 |*`CU_GRAPHICS_MAP_RESOURCE_FLAGS_READ_ONLY`* | | |
| 0x02 |*`CU_GRAPHICS_MAP_RESOURCE_FLAGS_WRITE_DISCARD`* | | |
| enum |***`CUgraphicsRegisterFlags`*** | | Flags to register a graphics resource |
| 0x00 |*`CU_GRAPHICS_REGISTER_FLAGS_NONE`* | | |
| 0x01 |*`CU_GRAPHICS_REGISTER_FLAGS_READ_ONLY`* | | |
| 0x02 |*`CU_GRAPHICS_REGISTER_FLAGS_WRITE_DISCARD`* | | |
| 0x04 |*`CU_GRAPHICS_REGISTER_FLAGS_SURFACE_LDST`* | | |
| 0x08 |*`CU_GRAPHICS_REGISTER_FLAGS_TEXTURE_GATHER`* | | |
| enum |***`CUipcMem_flags`*** | | CUDA Ipc Mem Flags |
| 0x1 |*`CU_IPC_MEM_LAZY_ENABLE_PEER_ACCESS`* |*`hipIpcMemLazyEnablePeerAccess`* | Automatically enable peer access between remote devices as needed |
| enum |***`CUjit_cacheMode`*** | | Caching modes for dlcm |
| 0 |*`CU_JIT_CACHE_OPTION_NONE`* | | Compile with no -dlcm flag specified |
| |*`CU_JIT_CACHE_OPTION_CG`* | | Compile with L1 cache disabled |
| |*`CU_JIT_CACHE_OPTION_CA`* | | Compile with L1 cache enabled |
| enum |***`CUjit_fallback`*** | | Cubin matching fallback strategies |
| 0 |*`CU_PREFER_PTX`* | | Prefer to compile ptx if exact binary match not found |
| |*`CU_PREFER_BINARY`* | | Prefer to fall back to compatible binary code if exact match not found |
| enum |***`CUjit_option`*** | | Online compiler and linker options |
| 0 |*`CU_JIT_MAX_REGISTERS`* | | Max number of registers that a thread may use. Option type: unsigned int Applies to: compiler only. |
| |*`CU_JIT_THREADS_PER_BLOCK`* | | IN: Specifies minimum number of threads per block to target compilation for OUT: Returns the number of threads the compiler actually targeted. This restricts the resource utilization fo the compiler (e.g. max registers) such that a block with the given number of threads should be able to launch based on register limitations. Note, this option does not currently take into account any other resource limitations, such as shared memory utilization. Cannot be combined with CU_JIT_TARGET. Option type: unsigned int Applies to: compiler only. |
| |*`CU_JIT_WALL_TIME`* | | Overwrites the option value with the total wall clock time, in milliseconds, spent in the compiler and linker Option type: float Applies to: compiler and linker. |
| |*`CU_JIT_INFO_LOG_BUFFER`* | | Pointer to a buffer in which to print any log messages that are informational in nature (the buffer size is specified via option CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES) Option type: char * Applies to: compiler and linker. |
| |*`CU_JIT_INFO_LOG_BUFFER_SIZE_BYTES`* | | IN: Log buffer size in bytes. Log messages will be capped at this size (including null terminator) OUT: Amount of log buffer filled with messages Option type: unsigned int Applies to: compiler and linker. |
| |*`CU_JIT_OPTIMIZATION_LEVEL`* | | Level of optimizations to apply to generated code (0 - 4), with 4 being the default and highest level of optimizations. Option type: unsigned int Applies to: compiler only. |
| |*`CU_JIT_TARGET_FROM_CUCONTEXT`* | | No option value required. Determines the target based on the current attached context (default) Option type: No option value needed Applies to: compiler and linker. |
| |*`CU_JIT_TARGET`* | | Target is chosen based on supplied CUjit_target. Cannot be combined with CU_JIT_THREADS_PER_BLOCK. Option type: unsigned int for enumerated type CUjit_target Applies to: compiler and linker. |
| |*`CU_JIT_FALLBACK_STRATEGY`* | | Specifies choice of fallback strategy if matching cubin is not found. Choice is based on supplied CUjit_fallback. This option cannot be used with cuLink* APIs as the linker requires exact matches. Option type: unsigned int for enumerated type CUjit_fallback Applies to: compiler only. |
| |*`CU_JIT_GENERATE_DEBUG_INFO`* | | Specifies whether to create debug information in output (-g) (0: false, default) Option type: int Applies to: compiler and linker. |
| |*`CU_JIT_LOG_VERBOSE`* | | Generate verbose log messages (0: false, default) Option type: int Applies to: compiler and linker. |
| |*`CU_JIT_GENERATE_LINE_INFO`* | | Generate line number information (-lineinfo) (0: false, default) Option type: int Applies to: compiler only. |
| |*`CU_JIT_CACHE_MODE`* | | Specifies whether to enable caching explicitly (-dlcm) Choice is based on supplied CUjit_cacheMode_enum. Option type: unsigned int for enumerated type CUjit_cacheMode_enum Applies to: compiler only. |
| |*`CU_JIT_NUM_OPTIONS`* | | |
| enum |***`CUjit_target`*** | | Online compilation targets |
| 10 |*`CU_TARGET_COMPUTE_10`* | | Compute device class 1.0. |
| 11 |*`CU_TARGET_COMPUTE_11`* | | Compute device class 1.1. |
| 12 |*`CU_TARGET_COMPUTE_12`* | | Compute device class 1.2. |
| 13 |*`CU_TARGET_COMPUTE_13`* | | Compute device class 1.3. |
| 20 |*`CU_TARGET_COMPUTE_20`* | | Compute device class 2.0. |
| 21 |*`CU_TARGET_COMPUTE_21`* | | Compute device class 2.1. |
| 30 |*`CU_TARGET_COMPUTE_30`* | | Compute device class 3.0. |
| 32 |*`CU_TARGET_COMPUTE_32`* | | Compute device class 3.2. |
| 35 |*`CU_TARGET_COMPUTE_35`* | | Compute device class 3.5. |
| 37 |*`CU_TARGET_COMPUTE_37`* | | Compute device class 3.7. |
| 50 |*`CU_TARGET_COMPUTE_50`* | | Compute device class 5.0. |
| 52 |*`CU_TARGET_COMPUTE_52`* | | Compute device class 5.2. |
| enum |***`CUjitInputType`*** | | Device code formats |
| 0 |*`CU_JIT_INPUT_CUBIN`* | | Compiled device-class-specific device code Applicable options: none. |
| |*`CU_JIT_INPUT_PTX`* | | PTX source code Applicable options: PTX compiler options. |
| |*`CU_JIT_INPUT_FATBINARY`* | | Bundle of multiple cubins and/or PTX of some device code Applicable options: PTX compiler options, CU_JIT_FALLBACK_STRATEGY. |
| |*`CU_JIT_INPUT_OBJECT`* | | Host object with embedded device code Applicable options: PTX compiler options, CU_JIT_FALLBACK_STRATEGY. |
| |*`CU_JIT_INPUT_LIBRARY`* | | Archive of host objects with embedded device code Applicable options: PTX compiler options, CU_JIT_FALLBACK_STRATEGY. |
| |*`CU_JIT_NUM_INPUT_TYPES`* | | |
| enum |***`CUlimit`*** |***`hipLimit_t`*** | Limits |
| 0x00 |*`CU_LIMIT_STACK_SIZE`* | | GPU thread stack size. |
| 0x01 |*`CU_LIMIT_PRINTF_FIFO_SIZE`* | | GPU printf FIFO size. |
| 0x02 |*`CU_LIMIT_MALLOC_HEAP_SIZE`* |*`hipLimitMallocHeapSize`* | GPU malloc heap size. |
| 0x03 |*`CU_LIMIT_DEV_RUNTIME_SYNC_DEPTH`* | | GPU device runtime launch synchronize depth. |
| 0x04 |*`CU_LIMIT_DEV_RUNTIME_PENDING_LAUNCH_COUNT`* | | GPU device runtime pending launch count. |
| |*`CU_LIMIT_MAX`* | | |
| enum |***`CUmemAttach_flags`*** | | CUDA Mem Attach Flags |
| 0x1 |*`CU_MEM_ATTACH_GLOBAL`* | | Memory can be accessed by any stream on any device. |
| 0x2 |*`CU_MEM_ATTACH_HOST`* | | Memory cannot be accessed by any stream on any device. |
| 0x4 |*`CU_MEM_ATTACH_SINGLE`* | | Memory can only be accessed by a single stream on the associated device. |
| enum |***`CUmemorytype`*** | | Memory types |
| 0x01 |*`CU_MEMORYTYPE_HOST`* | | Host memory |
| 0x02 |*`CU_MEMORYTYPE_DEVICE`* | | Device memory |
| 0x03 |*`CU_MEMORYTYPE_ARRAY`* | | Array memory |
| 0x04 |*`CU_MEMORYTYPE_UNIFIED`* | | Unified device or host memory |
| enum |***`CUoccupancy_flags`*** | | Occupancy calculator flag |
| 0x00 |*`CU_OCCUPANCY_DEFAULT`* | | Default behavior |
| 0x01 |*`CU_OCCUPANCY_DISABLE_CACHING_OVERRIDE`* | | Assume global caching is enabled and cannot be automatically turned off |
| enum |***`CUpointer_attribute`*** | | Pointer information |
| 1 |*`CU_POINTER_ATTRIBUTE_CONTEXT`* | | The CUcontext on which a pointer was allocated or registered |
| 2 |*`CU_POINTER_ATTRIBUTE_MEMORY_TYPE`* | | The CUmemorytype describing the physical location of a pointer |
| 3 |*`CU_POINTER_ATTRIBUTE_DEVICE_POINTER`* | | The address at which a pointer's memory may be accessed on the device |
| 4 |*`CU_POINTER_ATTRIBUTE_HOST_POINTER`* | | The address at which a pointer's memory may be accessed on the host |
| 5 |*`CU_POINTER_ATTRIBUTE_P2P_TOKENS`* | | A pair of tokens for use with the nv-p2p.h Linux kernel interface |
| 6 |*`CU_POINTER_ATTRIBUTE_SYNC_MEMOPS`* | | Synchronize every synchronous memory operation initiated on this region |
| 7 |*`CU_POINTER_ATTRIBUTE_BUFFER_ID`* | | A process-wide unique ID for an allocated memory region |
| 8 |*`CU_POINTER_ATTRIBUTE_IS_MANAGED`* | | Indicates if the pointer points to managed memory |
| enum |***`CUmemorytype`*** | | Resource types |
| 0x00 |*`CU_RESOURCE_TYPE_ARRAY`* | | Array resoure |
| 0x01 |*`CU_RESOURCE_TYPE_MIPMAPPED_ARRAY`* | | Mipmapped array resource |
| 0x02 |*`CU_RESOURCE_TYPE_LINEAR`* | | Linear resource |
| 0x03 |*`CU_RESOURCE_TYPE_PITCH2D`* | | Pitch 2D resource |
| enum |***`CUresourceViewFormat`*** | | Resource view format |
| 0x00 |*`CU_RES_VIEW_FORMAT_NONE`* | | No resource view format (use underlying resource format) |
| 0x01 |*`CU_RES_VIEW_FORMAT_UINT_1X8`* | | 1 channel unsigned 8-bit integers |
| 0x02 |*`CU_RES_VIEW_FORMAT_UINT_2X8`* | | 2 channel unsigned 8-bit integers |
| 0x03 |*`CU_RES_VIEW_FORMAT_UINT_4X8`* | | 4 channel unsigned 8-bit integers |
| 0x04 |*`CU_RES_VIEW_FORMAT_SINT_1X8`* | | 1 channel signed 8-bit integers |
| 0x05 |*`CU_RES_VIEW_FORMAT_SINT_2X8`* | | 2 channel signed 8-bit integers |
| 0x06 |*`CU_RES_VIEW_FORMAT_SINT_4X8`* | | 4 channel signed 8-bit integers |
| 0x07 |*`CU_RES_VIEW_FORMAT_UINT_1X16`* | | 1 channel unsigned 16-bit integers |
| 0x08 |*`CU_RES_VIEW_FORMAT_UINT_2X16`* | | 2 channel unsigned 16-bit integers |
| 0x09 |*`CU_RES_VIEW_FORMAT_UINT_4X16`* | | 4 channel unsigned 16-bit integers |
| 0x0a |*`CU_RES_VIEW_FORMAT_SINT_1X16`* | | 1 channel signed 16-bit integers |
| 0x0b |*`CU_RES_VIEW_FORMAT_SINT_2X16`* | | 2 channel signed 16-bit integers |
| 0x0c |*`CU_RES_VIEW_FORMAT_SINT_4X16`* | | 4 channel signed 16-bit integers |
| 0x0d |*`CU_RES_VIEW_FORMAT_UINT_1X32`* | | 1 channel unsigned 32-bit integers |
| 0x0e |*`CU_RES_VIEW_FORMAT_UINT_2X32`* | | 2 channel unsigned 32-bit integers |
| 0x0f |*`CU_RES_VIEW_FORMAT_UINT_4X32`* | | 4 channel unsigned 32-bit integers |
| 0x10 |*`CU_RES_VIEW_FORMAT_SINT_1X32`* | | 1 channel signed 32-bit integers |
| 0x11 |*`CU_RES_VIEW_FORMAT_SINT_2X32`* | | 2 channel signed 32-bit integers |
| 0x12 |*`CU_RES_VIEW_FORMAT_SINT_4X32`* | | 4 channel signed 32-bit integers |
| 0x13 |*`CU_RES_VIEW_FORMAT_FLOAT_1X16`* | | 1 channel 16-bit floating point |
| 0x14 |*`CU_RES_VIEW_FORMAT_FLOAT_2X16`* | | 2 channel 16-bit floating point |
| 0x15 |*`CU_RES_VIEW_FORMAT_FLOAT_4X16`* | | 4 channel 16-bit floating point |
| 0x16 |*`CU_RES_VIEW_FORMAT_FLOAT_1X32`* | | 1 channel 32-bit floating point |
| 0x17 |*`CU_RES_VIEW_FORMAT_FLOAT_2X32`* | | 2 channel 32-bit floating point |
| 0x18 |*`CU_RES_VIEW_FORMAT_FLOAT_4X32`* | | 4 channel 32-bit floating point |
| 0x19 |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC1`* | | Block compressed 1 |
| 0x1a |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC3`* | | Block compressed 2 |
| 0x1b |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC3`* | | Block compressed 3 |
| 0x1c |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC4`* | | Block compressed 4 unsigned |
| 0x1d |*`CU_RES_VIEW_FORMAT_SIGNED_BC4`* | | Block compressed 4 signed |
| 0x1e |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC5`* | | Block compressed 5 unsigned |
| 0x1f |*`CU_RES_VIEW_FORMAT_SIGNED_BC5`* | | Block compressed 5 signed |
| 0x20 |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC6H`* | | Block compressed 6 unsigned half-float |
| 0x21 |*`CU_RES_VIEW_FORMAT_SIGNED_BC6H`* | | Block compressed 6 signed half-float |
| 0x22 |*`CU_RES_VIEW_FORMAT_UNSIGNED_BC7`* | | Block compressed 7 |
| enum |***`CUresult`*** |***`hipError_t`*** | Error codes |
| 0 |*`CUDA_SUCCESS`* |*`hipSuccess`* | The API call returned with no errors. In the case of query calls, this can also mean that the operation being queried is complete (see cuEventQuery() and cuStreamQuery()). |
| 1 |*`CUDA_ERROR_INVALID_VALUE`* |*`hipErrorInvalidValue`* | This indicates that one or more of the parameters passed to the API call is not within an acceptable range of values. |
| 2 |*`CUDA_ERROR_OUT_OF_MEMORY`* |*`hipErrorMemoryAllocation`* | The API call failed because it was unable to allocate enough memory to perform the requested operation. |
| 3 |*`CUDA_ERROR_NOT_INITIALIZED`* |*`hipErrorNotInitialized`* | This indicates that the CUDA driver has not been initialized with cuInit() or that initialization has failed. |
| 4 |*`CUDA_ERROR_DEINITIALIZED`* |*`hipErrorDeinitialized`* | This indicates that the CUDA driver is in the process of shutting down. |
| 5 |*`CUDA_ERROR_PROFILER_DISABLED`* |*`hipErrorProfilerDisabled`* | This indicates profiler is not initialized for this run. This can happen when the application is running with external profiling tools like visual profiler. |
| 6 |*`CUDA_ERROR_PROFILER_NOT_INITIALIZED`* |*`hipErrorProfilerNotInitialized`* | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to attempt to enable/disable the profiling via cuProfilerStart or cuProfilerStop without initialization. |
| 7 |*`CUDA_ERROR_PROFILER_ALREADY_STARTED`* |*`hipErrorProfilerAlreadyStarted`* | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to call cuProfilerStart() when profiling is already enabled. |
| 8 |*`CUDA_ERROR_PROFILER_ALREADY_STOPPED`* |*`hipErrorProfilerAlreadyStopped`* | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to call cuProfilerStop() when profiling is already disabled. |
| 100 |*`CUDA_ERROR_NO_DEVICE`* |*`hipErrorNoDevice`* | This indicates that no CUDA-capable devices were detected by the installed CUDA driver. |
| 101 |*`CUDA_ERROR_INVALID_DEVICE`* |*`hipErrorInvalidDevice`* | This indicates that the device ordinal supplied by the user does not correspond to a valid CUDA device. |
| 200 |*`CUDA_ERROR_INVALID_IMAGE`* |*`hipErrorInvalidImage`* | This indicates that the device kernel image is invalid. This can also indicate an invalid CUDA module. |
| 201 |*`CUDA_ERROR_INVALID_CONTEXT`* |*`hipErrorInvalidContext`* | This most frequently indicates that there is no context bound to the current thread. This can also be returned if the context passed to an API call is not a valid handle (such as a context that has had cuCtxDestroy() invoked on it). This can also be returned if a user mixes different API versions (i.e. 3010 context with 3020 API calls). See cuCtxGetApiVersion() for more details. |
| 202 |*`CUDA_ERROR_CONTEXT_ALREADY_CURRENT`* |*`hipErrorContextAlreadyCurrent`* | This indicated that the context being supplied as a parameter to the API call was already the active context. Deprecated This error return is deprecated as of CUDA 3.2. It is no longer an error to attempt to push the active context via cuCtxPushCurrent(). |
| 205 |*`CUDA_ERROR_MAP_FAILED`* |*`hipErrorMapFailed`* | This indicates that a map or register operation has failed. |
| 206 |*`CUDA_ERROR_UNMAP_FAILED`* |*`hipErrorUnmapFailed`* | This indicates that an unmap or unregister operation has failed. |
| 207 |*`CUDA_ERROR_ARRAY_IS_MAPPED`* |*`hipErrorArrayIsMapped`* | This indicates that the specified array is currently mapped and thus cannot be destroyed. |
| 208 |*`CUDA_ERROR_ALREADY_MAPPED`* |*`hipErrorAlreadyMapped`* | This indicates that the resource is already mapped. |
| 209 |*`CUDA_ERROR_NO_BINARY_FOR_GPU`* |*`hipErrorNoBinaryForGpu* | This indicates that there is no kernel image available that is suitable for the device. This can occur when a user specifies code generation options for a particular CUDA source file that do not include the corresponding device configuration. |
| 210 |*`CUDA_ERROR_ALREADY_ACQUIRED`* |*`hipErrorAlreadyAcquired* | This indicates that a resource has already been acquired. |
| 211 |*`CUDA_ERROR_NOT_MAPPED`* |*`hipErrorNotMapped`* | This indicates that a resource is not mapped. |
| 212 |*`CUDA_ERROR_NOT_MAPPED_AS_ARRAY`* |*`hipErrorNotMappedAsArray`* | This indicates that a mapped resource is not available for access as an array. |
| 213 |*`CUDA_ERROR_NOT_MAPPED_AS_POINTER`* |*`hipErrorNotMappedAsPointer`* | This indicates that a mapped resource is not available for access as a pointer. |
| 214 |*`CUDA_ERROR_ECC_UNCORRECTABLE`* |*`hipErrorECCNotCorrectable`* | This indicates that an uncorrectable ECC error was detected during execution. |
| 215 |*`CUDA_ERROR_UNSUPPORTED_LIMIT`* |*`hipErrorUnsupportedLimit`* | This indicates that the CUlimit passed to the API call is not supported by the active device. |
| 216 |*`CUDA_ERROR_CONTEXT_ALREADY_IN_USE`* |*`hipErrorContextAlreadyInUse`* | This indicates that the CUcontext passed to the API call can only be bound to a single CPU thread at a time but is already bound to a CPU thread. |
| 217 |*`CUDA_ERROR_PEER_ACCESS_UNSUPPORTED`* |*`hipErrorPeerAccessUnsupported`* | This indicates that peer access is not supported across the given devices. |
| 218 |*`CUDA_ERROR_INVALID_PTX`* |*`hipErrorInvalidKernelFile`* | This indicates that a PTX JIT compilation failed. |
| 219 |*`CUDA_ERROR_INVALID_GRAPHICS_CONTEXT`* |*`hipErrorInvalidGraphicsContext`* | This indicates an error with OpenGL or DirectX context. |
| 300 |*`CUDA_ERROR_INVALID_SOURCE`* |*`hipErrorInvalidSource`* | This indicates that the device kernel source is invalid. |
| 301 |*`CUDA_ERROR_FILE_NOT_FOUND`* |*`hipErrorFileNotFound`* | This indicates that the file specified was not found. |
| 302 |*`CUDA_ERROR_SHARED_OBJECT_SYMBOL_NOT_FOUND`* |*`hipErrorSharedObjectSymbolNotFound`* | This indicates that a link to a shared object failed to resolve. |
| 303 |*`CUDA_ERROR_SHARED_OBJECT_INIT_FAILED`* |*`hipErrorSharedObjectInitFailed`* | This indicates that initialization of a shared object failed. |
| 304 |*`CUDA_ERROR_OPERATING_SYSTEM`* |*`hipErrorOperatingSystem`* | This indicates that an OS call failed. |
| 400 |*`CUDA_ERROR_INVALID_HANDLE`* |*`hipErrorInvalidResourceHandle`* | This indicates that a resource handle passed to the API call was not valid. Resource handles are opaque types like CUstream and CUevent. |
| 500 |*`CUDA_ERROR_NOT_FOUND`* |*`hipErrorNotFound`* | This indicates that a named symbol was not found. Examples of symbols are global/constant variable names, texture names, and surface names. |
| 600 |*`CUDA_ERROR_NOT_READY`* |*`hipErrorNotReady`* | This indicates that asynchronous operations issued previously have not completed yet. This result is not actually an error, but must be indicated differently than CUDA_SUCCESS (which indicates completion). Calls that may return this value include cuEventQuery() and cuStreamQuery(). |
| 700 |*`CUDA_ERROR_ILLEGAL_ADDRESS`* |*`hipErrorIllegalAddress`* | While executing a kernel, the device encountered a load or store instruction on an invalid memory address. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA. |
## **2. Error Handling**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **3. Initialization**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **4. Version Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **5. Device Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **6. Device Management [DEPRECATED]**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **7. Primary Context Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **8. Context Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **9. Context Management [DEPRECATED]**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **10. Module Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **11. Memory Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **12. Unified Addressing**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **13. Stream Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **14. Event Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **15. Execution Control**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **16. Execution Control [DEPRECATED]**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **17. Occupancy**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **18. Texture Reference Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **19. Texture Reference Management [DEPRECATED]**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **20. Surface Reference Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **21. Texture Object Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **22. Surface Object Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **23. Peer Context Memory Access**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **24. Graphics Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **25. Profiler Control**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **26. OpenGL Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **27. Direct3D 9 Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **28. Direct3D 10 Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **29. Direct3D 11 Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
## **30. VDPAU Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
docs/markdown/CUDA_Runtime_API_functions_supported_by_HIP.md
+421 -54
Voir le fichier
@@ -1,34 +1,36 @@
**1. Device Management**
# CUDA Runtime API functions supported by HIP
## **1. Device Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaChooseDevice` | `hipChooseDevice` | Select compute-device which best matches criteria. |
| `cudaChooseDevice` | `hipChooseDevice` | Select compute-device which best matches criteria. |
| `cudaDeviceGetAttribute` | `hipDeviceGetAttribute` | Returns information about the device. |
| `cudaDeviceGetByPCIBusId` | | Returns a handle to a compute device. |
| `cudaDeviceGetByPCIBusId` | `hipDeviceGetByPCIBusId` | Returns a handle to a compute device. |
| `cudaDeviceGetCacheConfig` | `hipDeviceGetCacheConfig` | Returns the preferred cache configuration for the current device. |
| `cudaDeviceGetLimit` | `hipDeviceGetLimit` | Returns resource limits. |
| `cudaDeviceGetPCIBusId` | | Returns a PCI Bus Id string for the device. |
| `cudaDeviceGetLimit` | `hipDeviceGetLimit` | Returns resource limits. |
| `cudaDeviceGetPCIBusId` | `hipDeviceGetPCIBusId` | Returns a PCI Bus Id string for the device. |
| `cudaDeviceGetSharedMemConfig` | `hipDeviceGetSharedMemConfig` | Returns the shared memory configuration for the current device. |
| `cudaDeviceGetStreamPriorityRange` | | Returns numerical values that correspond to the least and greatest stream priorities. |
| `cudaDeviceReset` | `hipDeviceReset` | Destroy all allocations and reset all state on the current device in the current process. |
| `cudaDeviceSetCacheConfig` | `hipDeviceSetCacheConfig` | Sets the preferred cache configuration for the current device. |
| `cudaDeviceSetLimit` | `hipDeviceSetLimit` | Set resource limits. |
| `cudaDeviceSetLimit` | `hipDeviceSetLimit` | Set resource limits. |
| `cudaDeviceSetSharedMemConfig` | `hipDeviceSetSharedMemConfig` | Sets the shared memory configuration for the current device. |
| `cudaDeviceSynchronize` | `hipDeviceSynchronize` | Wait for compute device to finish. |
| `cudaGetDevice` | `hipGetDevice` | Returns which device is currently being used. |
| `cudaGetDeviceCount` | `hipGetDeviceCount` | Returns the number of compute-capable devices. |
| `cudaGetDeviceFlags` | | Gets the flags for the current device. |
| `cudaGetDeviceProperties` | `hipGetDeviceProperties` | Returns information about the compute-device. |
| `cudaIpcCloseMemHandle` | | Close memory mapped with cudaIpcOpenMemHandle. |
| `cudaIpcGetEventHandle` | | Gets an interprocess handle for a previously allocated event. |
| `cudaIpcGetMemHandle` | | Gets an interprocess memory handle for an existing device memory allocation. |
| `cudaIpcOpenEventHandle` | | Opens an interprocess event handle for use in the current process. |
| `cudaIpcOpenMemHandle` | | Opens an interprocess memory handle exported from another process and returns a device pointer usable in the local process. |
| `cudaIpcCloseMemHandle` | `hipIpcCloseMemHandle` | Close memory mapped with cudaIpcOpenMemHandle. |
| `cudaIpcGetEventHandle` | `hipIpcGetEventHandle` | Gets an interprocess handle for a previously allocated event. |
| `cudaIpcGetMemHandle` | `hipIpcGetMemHandle` | Gets an interprocess memory handle for an existing device memory allocation. |
| `cudaIpcOpenEventHandle` | `hipIpcOpenEventHandle` | Opens an interprocess event handle for use in the current process. |
| `cudaIpcOpenMemHandle` | `hipIpcOpenMemHandle` | Opens an interprocess memory handle exported from another process and returns a device pointer usable in the local process. |
| `cudaSetDevice` | `hipSetDevice` | Set device to be used for GPU executions. |
| `cudaSetDeviceFlags` | `hipSetDeviceFlags` | Sets flags to be used for device executions. |
| `cudaSetValidDevices` | | Set a list of devices that can be used for CUDA. |`
| `cudaSetValidDevices` | | Set a list of devices that can be used for CUDA. |
**2. Error Handling**
## **2. Error Handling**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -37,12 +39,12 @@
| `cudaGetLastError` | `hipGetLastError` | Returns the last error from a runtime call. |
| `cudaPeekAtLastError` | `hipPeekAtLastError` | Returns the last error from a runtime call. |
**3. Stream Management**
## **3. Stream Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaStreamAddCallback` | | Add a callback to a compute stream. |
| `cudaStreamAttachMemAsync` | | Attach managed memory to a stream asynchronously. |
| `cudaStreamAddCallback` | `hipStreamAddCallback` | Add a callback to a compute stream. |
| `cudaStreamAttachMemAsync` | | Attach managed memory to a stream asynchronously. |
| `cudaStreamCreate` | `hipStreamCreate` | Create an asynchronous stream. |
| `cudaStreamCreateWithFlags` | `hipStreamCreateWithFlags` | Create an asynchronous stream. |
| `cudaStreamCreateWithPriority` | | Create an asynchronous stream with the specified priority. |
@@ -53,7 +55,7 @@
| `cudaStreamSynchronize` | `hipStreamSynchronize` | Waits for stream tasks to complete. |
| `cudaStreamWaitEvent` | `hipStreamWaitEvent` | Make a compute stream wait on an event. |
**4. Event Management**
## **4. Event Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -65,7 +67,7 @@
| `cudaEventRecord` | `hipEventRecord` | Records an event. |
| `cudaEventSynchronize` | `hipEventSynchronize` | Waits for an event to complete. |
**5. Execution Control**
## **5. Execution Control**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -78,46 +80,54 @@
| `cudaSetDoubleForDevice` | | Converts a double argument to be executed on a device. |
| `cudaSetDoubleForHost` | | Converts a double argument after execution on a device. |
**6. Occupancy**
## **6. Occupancy**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaOccupancyMaxActiveBlocksPerMultiprocessor` | | Returns occupancy for a device function. |
| `cudaOccupancyMaxActiveBlocksPerMultiprocessor` | `hipOccupancyMaxActiveBlocksPerMultiprocessor`| Returns occupancy for a device function. |
| `cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags` | | Returns occupancy for a device function with the specified flags. |
**7. Memory Management**
## **7. Execution Control [deprecated since 7.0]**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaConfigureCall` | | Configure a device-launch. |
| `cudaLaunch` | | Launches a device function. |
| `cudaSetupArgument` | | Configure a device launch. |
## **8. Memory Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaArrayGetInfo` | | Gets info about the specified cudaArray. |
| `cudaFree` | `hipFree` | Frees memory on the device. |
| `cudaFreeArray` | | Frees an array on the device. |
| `cudaFreeArray` | `hipFreeArray` | Frees an array on the device. |
| `cudaFreeHost` | `hipHostFree` | Frees page-locked memory. |
| `cudaFreeMipmappedArray` | | Frees a mipmapped array on the device. |
| `cudaGetMipmappedArrayLevel` | | Gets a mipmap level of a CUDA mipmapped array. |
| `cudaGetSymbolAddress` | | Finds the address associated with a CUDA symbol. |
| `cudaGetSymbolSize` | | Finds the size of the object associated with a CUDA symbol. |
| `cudaHostAlloc` | `hipHostMalloc` | Allocates page-locked memory on the host. |
| `cudaHostGetDevicePointer` | `hipHostGetDevicePointer` | Passes back device pointer of mapped host memory allocated by cudaHostAlloc or registered by cudaHostRegister. |
| `cudaHostGetFlags` | `hipHostGetFlags` | Passes back flags used to allocate pinned host memory allocated by cudaHostAlloc. |
| `cudaHostAlloc` | `hipHostMalloc` | Allocates page-locked memory on the host. |
| `cudaHostGetDevicePointer` | `hipHostGetDevicePointer` | Passes back device pointer of mapped host memory allocated by cudaHostAlloc or registered by cudaHostRegister. |
| `cudaHostGetFlags` | `hipHostGetFlags` | Passes back flags used to allocate pinned host memory allocated by cudaHostAlloc. |
| `cudaHostRegister` | `hipHostRegister` | Registers an existing host memory range for use by CUDA. |
| `cudaHostUnregister` | `hipHostUnregister` | Unregisters a memory range that was registered with cudaHostRegister. |
| `cudaMalloc` | `hipMalloc` | Allocate memory on the device. |
| `cudaMalloc3D` | | Allocates logical 1D, 2D, or 3D memory objects on the device. |
| `cudaMalloc3DArray` | | Allocate an array on the device. |
| `cudaMallocArray` | | Allocate an array on the device. |
| `cudaMallocHost` | `hipHostMalloc` | Allocates page-locked memory on the host. |
| `cudaMallocArray` | `hipMallocArray` | Allocate an array on the device. |
| `cudaMallocHost` | `hipHostMalloc` | Allocates page-locked memory on the host. |
| `cudaMallocManaged` | | Allocates memory that will be automatically managed by the Unified Memory system. |
| `cudaMallocMipmappedArray` | | Allocate a mipmapped array on the device. |
| `cudaMallocPitch` | | Allocates pitched memory on the device. |
| `cudaMemGetInfo` | | Gets free and total device memory. |
| `cudaMemGetInfo` | `hipMemGetInfo` | Gets free and total device memory. |
| `cudaMemcpy` | `hipMemcpy` | Copies data between host and device. |
| `cudaMemcpy2D` | | Copies data between host and device. |
| `cudaMemcpy2D` | `hipMemcpy2D` | Copies data between host and device. |
| `cudaMemcpy2DArrayToArray` | | Copies data between host and device. |
| `cudaMemcpy2DAsync` | | Copies data between host and device. |
| `cudaMemcpy2DFromArray` | | Copies data between host and device. |
| `cudaMemcpy2DFromArrayAsync` | | Copies data between host and device. |
| `cudaMemcpy2DToArray` | | Copies data between host and device. |
| `cudaMemcpy2DToArray` | `hipMemcpy2DToArray` | Copies data between host and device. |
| `cudaMemcpy2DToArrayAsync` | | Copies data between host and device. |
| `cudaMemcpy3D` | | Copies data between 3D objects. |
| `cudaMemcpy3DAsync` | | Copies data between 3D objects. |
@@ -131,27 +141,27 @@
| `cudaMemcpyFromSymbolAsync` | | Copies data from the given symbol on the device. |
| `cudaMemcpyPeer` | `hipMemcpyPeer` | Copies memory between two devices. |
| `cudaMemcpyPeerAsync` | `hipMemcpyPeerAsync` | Copies memory between two devices asynchronously. |
| `cudaMemcpyToArray` | | Copies data between host and device. |
| `cudaMemcpyToArray` | `hipMemcpyToArray` | Copies data between host and device. |
| `cudaMemcpyToArrayAsync` | | Copies data between host and device. |
| `cudaMemcpyToSymbol` | `hipMemcpyToSymbol` | Copies data to the given symbol on the device. |
| `cudaMemcpyToSymbolAsync` | | Copies data to the given symbol on the device. |
| `cudaMemcpyToSymbolAsync` | `hipMemcpyToSymbolAsync` | Copies data to the given symbol on the device. |
| `cudaMemset` | `hipMemset` | Initializes or sets device memory to a value. |
| `cudaMemset2D` | | Initializes or sets device memory to a value. |
| `cudaMemset2DAsync` | | Initializes or sets device memory to a value. |
| `cudaMemset3D` | | Initializes or sets device memory to a value. |
| `cudaMemset3DAsync` | | Initializes or sets device memory to a value. |
| `cudaMemsetAsync` | `hipMemsetAsync` | Initializes or sets device memory to a value. |
| `make\_cudaExtent` | | Returns a cudaExtent based on input parameters. |
| `make\_cudaPitchedPtr` | | Returns a cudaPitchedPtr based on input parameters. |
| `make\_cudaPos` | | Returns a cudaPos based on input parameters. |
| `make_cudaExtent` | | Returns a cudaExtent based on input parameters. |
| `make_cudaPitchedPtr` | | Returns a cudaPitchedPtr based on input parameters. |
| `make_cudaPos` | | Returns a cudaPos based on input parameters. |
**8. Unified Addressing**
## **9. Unified Addressing**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaPointerGetAttributes` | `hipPointerGetAttributes` | Returns attributes about a specified pointer. |
**9. Peer Device Memory Access**
## **10. Peer Device Memory Access**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -159,7 +169,7 @@
| `cudaDeviceDisablePeerAccess` | `hipDeviceDisablePeerAccess` | Disables direct access to memory allocations on a peer device. |
| `cudaDeviceEnablePeerAccess` | `hipDeviceEnablePeerAccess` | Enables direct access to memory allocations on a peer device. |
**10. OpenGL Interoperability**
## **11. OpenGL Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -168,7 +178,7 @@
| `cudaGraphicsGLRegisterImage` | | Register an OpenGL texture or renderbuffer object. |
| `cudaWGLGetDevice` | | Gets the CUDA device associated with hGpu. |
**11. Graphics Interoperability**
## **12. Graphics Interoperability**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -180,7 +190,7 @@
| `cudaGraphicsUnmapResources` | | Unmap graphics resources. |
| `cudaGraphicsUnregisterResource` | | Unregisters a graphics resource for access by CUDA. |
**12. Texture Reference Management**
## **13. Texture Reference Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -194,14 +204,14 @@
| `cudaGetTextureReference` | | Get the texture reference associated with a symbol. |
| `cudaUnbindTexture` | | Unbinds a texture. |
**13. Surface Reference Management**
## **14. Surface Reference Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaBindSurfaceToArray` | | Binds an array to a surface. |
| `cudaGetSurfaceReference` | | Get the surface reference associated with a symbol. |
**14. Texture Object Management**
## **15. Texture Object Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -211,7 +221,7 @@
| `cudaGetTextureObjectResourceViewDesc` | | Returns a texture object's resource view descriptor. |
| `cudaGetTextureObjectTextureDesc` | | Returns a texture object's texture descriptor. |
**15. Surface Object Management**
## **16. Surface Object Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
@@ -219,25 +229,24 @@
| `cudaDestroySurfaceObject` | | Destroys a surface object. |
| `cudaGetSurfaceObjectResourceDesc` | | Returns a surface object's resource descriptor Returns the resource descriptor for the surface object specified by surfObject. |
**16. Version Management**
## **17. Version Management**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaDriverGetVersion` | `hipDriverGetVersion` | Returns the CUDA driver version. |
| `cudaRuntimeGetVersion` | | Returns the CUDA Runtime version. |
| `cudaRuntimeGetVersion` | `hipRuntimeGetVersion` | Returns the CUDA Runtime version. |
**17. C++ API Routines (7.0 contains, 7.5 doesn’t)**
> Will not support for HIP (probably)
## **18. C++ API Routines**
*(7.0 contains, 7.5 doesn’t)*
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaBindSurfaceToArray` | | Binds an array to a surface. |
| `cudaBindTexture` | | Binds a memory area to a texture. |
| `cudaBindTexture` | `hipBindTexture` | Binds a memory area to a texture. |
| `cudaBindTexture2D` | | Binds a 2D memory area to a texture. |
| `cudaBindTextureToArray` | | Binds an array to a texture. |
| `cudaBindTextureToMipmappedArray` | | Binds a mipmapped array to a texture. |
| `cudaCreateChannelDesc` | | Returns a channel descriptor using the specified format. |
| `cudaEventCreate` | | Creates an event object with the specified flags. |
| `cudaCreateChannelDesc` | `hipCreateChannelDesc` | Returns a channel descriptor using the specified format. |
| `cudaFuncGetAttributes` | | Find out attributes for a given function. |
| `cudaFuncSetCacheConfig` | | Sets the preferred cache configuration for a device function. |
| `cudaGetSymbolAddress` | | Finds the address associated with a CUDA symbol |
@@ -251,20 +260,378 @@
| `cudaMemcpyFromSymbolAsync` | | Copies data from the given symbol on the device. |
| `cudaMemcpyToSymbol` | | Copies data to the given symbol on the device. |
| `cudaMemcpyToSymbolAsync` | | Async copies data to the given symbol on the device. |
| `cudaOccupancyMaxActiveBlocksPerMultiprocessor` | | Returns occupancy for a device function. |
| `cudaOccupancyMaxActiveBlocksPerMultiprocessor` | `hipOccupancyMaxActiveBlocksPerMultiprocessor` | Returns occupancy for a device function. |
| `cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags` | | Returns occupancy for a device function with the specified flags. |
| `cudaOccupancyMaxPotentialBlockSize` | | Returns grid and block size that achieves maximum potential occupancy for a device function. |
| `cudaOccupancyMaxPotentialBlockSize` | `hipOccupancyMaxPotentialBlockSize` | Returns grid and block size that achieves maximum potential occupancy for a device function. |
| `cudaOccupancyMaxPotentialBlockSizeVariableSMem` | | Returns grid and block size that achieves maximum potential occupancy for a device function. |
| `cudaOccupancyMaxPotentialBlockSizeVariableSMemWithFlags` | | Returns grid and block size that achieves maximum potential occupancy for a device function. |
| `cudaOccupancyMaxPotentialBlockSizeWithFlags` | | Returns grid and block size that achived maximum potential occupancy for a device function with the specified flags. |
| `cudaSetupArgument` | | Configure a device launch. |
| `cudaStreamAttachMemAsync` | | Attach memory to a stream asynchronously. |
| `cudaUnbindTexture` | | Unbinds a texture. |
| `cudaUnbindTexture` | `hipUnbindTexture` | Unbinds a texture. |
**18. Profiler Control**
## **19. Profiler Control**
| **CUDA** | **HIP** | **CUDA description** |
|-----------------------------------------------------------|-------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| `cudaProfilerInitialize` | | Initialize the CUDA profiler. |
| `cudaProfilerStart` | `hipProfilerStart` | Enable profiling. |
| `cudaProfilerStop` | `hipProfilerStop` | Disable profiling. |
# Data types used by CUDA Runtime API and supported by HIP
## **20. Data types**
| **type** | **CUDA** | **HIP** | **CUDA description** |
|-------------:|-----------------------------------------------|------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------|
| struct | `cudaChannelFormatDesc` | `hipChannelFormatDesc` | CUDA Channel format descriptor. |
| struct | `cudaDeviceProp` | `hipDeviceProp_t` | CUDA device properties. |
| struct | `cudaExtent` | | CUDA extent (width, height, depth). |
| struct | `cudaFuncAttributes` | | CUDA function attributes. |
| struct | `cudaIpcEventHandle_t` | `hipIpcEventHandle_t` | CUDA IPC event handle. |
| struct | `cudaIpcMemHandle_t` | `hipIpcMemHandle_t` | CUDA IPC memory handle. |
| struct | `cudaMemcpy3DParms` | | CUDA 3D memory copying parameters. |
| struct | `cudaMemcpy3DPeerParms` | | CUDA 3D cross-device memory copying parameters. |
| struct | `cudaPitchedPtr` | | CUDA Pitched memory pointer. |
| struct | `cudaPointerAttributes` | `hipPointerAttribute_t` | CUDA pointer attributes. |
| struct | `cudaPos` | | CUDA 3D position. |
| struct | `cudaResourceDesc` | | CUDA resource descriptor. |
| struct | `cudaResourceViewDesc` | | CUDA resource view descriptor. |
| struct | `cudaTextureDesc` | | CUDA texture descriptor. |
| struct | `surfaceReference` | | CUDA Surface reference. |
| struct | `textureReference` | `textureReference` | CUDA texture reference. |
| enum |***`cudaChannelFormatKind`*** |***`hipChannelFormatKind`*** | Channel format kind. |
| 0 |*`cudaChannelFormatKindSigned`* |*`hipChannelFormatKindSigned`* | Signed channel format. |
| 1 |*`cudaChannelFormatKindUnsigned`* |*`hipChannelFormatKindUnsigned`* | Unsigned channel format. |
| 2 |*`cudaChannelFormatKindFloat`* |*`hipChannelFormatKindFloat`* | Float channel format. |
| 3 |*`cudaChannelFormatKindNone`* |*`hipChannelFormatKindNone`* | No channel format. |
| enum |***`cudaComputeMode`*** | | CUDA device compute modes. |
| 0 |*`cudaComputeModeDefault`* | | Default compute mode (Multiple threads can use ::cudaSetDevice() with this device). |
| 1 |*`cudaComputeModeExclusive`* | | Compute-exclusive-thread mode (Only one thread in one process will be able to use ::cudaSetDevice() with this device). |
| 2 |*`cudaComputeModeProhibited`* | | Compute-prohibited mode (No threads can use ::cudaSetDevice() with this device). |
| 3 |*`cudaComputeModeExclusiveProcess`* | | Compute-exclusive-process mode (Many threads in one process will be able to use ::cudaSetDevice() with this device). |
| enum |***`cudaDeviceAttr`*** |***`hipDeviceAttribute_t`*** | CUDA device attributes. |
| 1 |*`cudaDevAttrMaxThreadsPerBlock`* |*`hipDeviceAttributeMaxThreadsPerBlock`* | Maximum number of threads per block. |
| 2 |*`cudaDevAttrMaxBlockDimX`* |*`hipDeviceAttributeMaxBlockDimX`* | Maximum block dimension X. |
| 3 |*`cudaDevAttrMaxBlockDimY`* |*`hipDeviceAttributeMaxBlockDimY`* | Maximum block dimension Y. |
| 4 |*`cudaDevAttrMaxBlockDimZ`* |*`hipDeviceAttributeMaxBlockDimZ`* | Maximum block dimension Y. |
| 5 |*`cudaDevAttrMaxGridDimX`* |*`hipDeviceAttributeMaxGridDimX`* | Maximum grid dimension X. |
| 6 |*`cudaDevAttrMaxGridDimY`* |*`hipDeviceAttributeMaxGridDimY`* | Maximum grid dimension Y. |
| 7 |*`cudaDevAttrMaxGridDimZ`* |*`hipDeviceAttributeMaxGridDimZ`* | Maximum grid dimension Y. |
| 8 |*`cudaDevAttrMaxSharedMemoryPerBlock`* |*`hipDeviceAttributeMaxSharedMemoryPerBlock`* | Maximum shared memory available per block in bytes. |
| 9 |*`cudaDevAttrTotalConstantMemory`* |*`hipDeviceAttributeTotalConstantMemory`* | Memory available on device for \__constant__ variables in a CUDA C kernel in bytes. |
| 10 |*`cudaDevAttrWarpSize`* |*`hipDeviceAttributeWarpSize`* | Warp size in threads. |
| 11 |*`cudaDevAttrMaxPitch`* | | Maximum pitch in bytes allowed by memory copies. |
| 12 |*`cudaDevAttrMaxRegistersPerBlock`* |*`hipDeviceAttributeMaxRegistersPerBlock`* | Maximum number of 32-bit registers available per block. |
| 13 |*`cudaDevAttrClockRate`* |*`hipDeviceAttributeClockRate`* | Peak clock frequency in kilohertz. |
| 14 |*`cudaDevAttrTextureAlignment`* | | Alignment requirement for textures. |
| 15 |*`cudaDevAttrGpuOverlap`* | | Device can possibly copy memory and execute a kernel concurrently. |
| 16 |*`cudaDevAttrMultiProcessorCount`* |*`hipDeviceAttributeMultiprocessorCount`* | Number of multiprocessors on device. |
| 17 |*`cudaDevAttrKernelExecTimeout`* | | Specifies whether there is a run time limit on kernels. |
| 18 |*`cudaDevAttrIntegrated`* | | Device is integrated with host memory. |
| 19 |*`cudaDevAttrCanMapHostMemory`* | | Device can map host memory into CUDA address space. |
| 20 |*`cudaDevAttrComputeMode`* |*`hipDeviceAttributeComputeMode`* | Compute mode (See cudaComputeMode for details). |
| 21 |*`cudaDevAttrMaxTexture1DWidth`* | | Maximum 1D texture width. |
| 22 |*`cudaDevAttrMaxTexture2DWidth`* | | Maximum 2D texture width. |
| 23 |*`cudaDevAttrMaxTexture2DHeight`* | | Maximum 2D texture height. |
| 24 |*`cudaDevAttrMaxTexture3DWidth`* | | Maximum 3D texture width. |
| 25 |*`cudaDevAttrMaxTexture3DHeight`* | | Maximum 3D texture height. |
| 26 |*`cudaDevAttrMaxTexture3DDepth`* | | Maximum 3D texture depth. |
| 27 |*`cudaDevAttrMaxTexture2DLayeredWidth`* | | Maximum 2D layered texture width. |
| 28 |*`cudaDevAttrMaxTexture2DLayeredHeight`* | | Maximum 2D layered texture height. |
| 29 |*`cudaDevAttrMaxTexture2DLayeredLayers`* | | Maximum layers in a 2D layered texture. |
| 30 |*`cudaDevAttrSurfaceAlignment`* | | Alignment requirement for surfaces. |
| 31 |*`cudaDevAttrConcurrentKernels`* |*`hipDeviceAttributeConcurrentKernels`* | Device can possibly execute multiple kernels concurrently. |
| 32 |*`cudaDevAttrEccEnabled`* | | Device has ECC support enabled. |
| 33 |*`cudaDevAttrPciBusId`* |*`hipDeviceAttributePciBusId`* | PCI bus ID of the device. |
| 34 |*`cudaDevAttrPciDeviceId`* |*`hipDeviceAttributePciDeviceId`* | PCI device ID of the device. |
| 35 |*`cudaDevAttrTccDriver`* | | Device is using TCC driver model. |
| 36 |*`cudaDevAttrMemoryClockRate`* |*`hipDeviceAttributeMemoryClockRate`* | Peak memory clock frequency in kilohertz. |
| 37 |*`cudaDevAttrGlobalMemoryBusWidth`* |*`hipDeviceAttributeMemoryBusWidth`* | Global memory bus width in bits. |
| 38 |*`cudaDevAttrL2CacheSize`* |*`hipDeviceAttributeL2CacheSize`* | Size of L2 cache in bytes. |
| 39 |*`cudaDevAttrMaxThreadsPerMultiProcessor`* |*`hipDeviceAttributeMaxThreadsPerMultiProcessor`* | Maximum resident threads per multiprocessor. |
| 40 |*`cudaDevAttrAsyncEngineCount`* | | Number of asynchronous engines. |
| 41 |*`cudaDevAttrUnifiedAddressing`* | | Device shares a unified address space with the host. |
| 42 |*`cudaDevAttrMaxTexture1DLayeredWidth`* | | Maximum 1D layered texture width. |
| 43 |*`cudaDevAttrMaxTexture1DLayeredLayers`* | | Maximum layers in a 1D layered texture. |
| 44 | | | *reserved* |
| 45 |*`cudaDevAttrMaxTexture2DGatherWidth`* | | Maximum 2D texture width if cudaArrayTextureGather is set. |
| 46 |*`cudaDevAttrMaxTexture2DGatherHeight`* | | Maximum 2D texture height if cudaArrayTextureGather is set. |
| 47 |*`cudaDevAttrMaxTexture3DWidthAlt`* | | Alternate maximum 3D texture width. |
| 48 |*`cudaDevAttrMaxTexture3DHeightAlt`* | | Alternate maximum 3D texture height. |
| 49 |*`cudaDevAttrMaxTexture3DDepthAlt`* | | Alternate maximum 3D texture depth. |
| 50 |*`cudaDevAttrPciDomainId`* | | PCI domain ID of the device. |
| 51 |*`cudaDevAttrTexturePitchAlignment`* | | Pitch alignment requirement for textures. |
| 52 |*`cudaDevAttrMaxTextureCubemapWidth`* | | Maximum cubemap texture width/height. |
| 53 |*`cudaDevAttrMaxTextureCubemapLayeredWidth`* | | Maximum cubemap layered texture width/height. |
| 54 |*`cudaDevAttrMaxTextureCubemapLayeredLayers`* | | Maximum layers in a cubemap layered texture. |
| 55 |*`cudaDevAttrMaxSurface1DWidth`* | | Maximum 1D surface width. |
| 56 |*`cudaDevAttrMaxSurface2DWidth`* | | Maximum 2D surface width. |
| 57 |*`cudaDevAttrMaxSurface2DHeight`* | | Maximum 2D surface height. |
| 58 |*`cudaDevAttrMaxSurface3DWidth`* | | Maximum 3D surface width. |
| 59 |*`cudaDevAttrMaxSurface3DHeight`* | | Maximum 3D surface height. |
| 60 |*`cudaDevAttrMaxSurface3DDepth`* | | Maximum 3D surface depth. |
| 61 |*`cudaDevAttrMaxSurface1DLayeredWidth`* | | Maximum 1D layered surface width. |
| 62 |*`cudaDevAttrMaxSurface1DLayeredLayers`* | | Maximum layers in a 1D layered surface. |
| 63 |*`cudaDevAttrMaxSurface2DLayeredWidth`* | | Maximum 2D layered surface width. |
| 64 |*`cudaDevAttrMaxSurface2DLayeredHeight`* | | Maximum 2D layered surface height. |
| 65 |*`cudaDevAttrMaxSurface2DLayeredLayers`* | | Maximum layers in a 2D layered surface. |
| 66 |*`cudaDevAttrMaxSurfaceCubemapWidth`* | | Maximum cubemap surface width. |
| 67 |*`cudaDevAttrMaxSurfaceCubemapLayeredWidth`* | | Maximum cubemap layered surface width. |
| 68 |*`cudaDevAttrMaxSurfaceCubemapLayeredLayers`* | | Maximum layers in a cubemap layered surface. |
| 69 |*`cudaDevAttrMaxTexture1DLinearWidth`* | | Maximum 1D linear texture width. |
| 70 |*`cudaDevAttrMaxTexture2DLinearWidth`* | | Maximum 2D linear texture width. |
| 71 |*`cudaDevAttrMaxTexture2DLinearHeight`* | | Maximum 2D linear texture height. |
| 72 |*`cudaDevAttrMaxTexture2DLinearPitch`* | | Maximum 2D linear texture pitch in bytes. |
| 73 |*`cudaDevAttrMaxTexture2DMipmappedWidth`* | | Maximum mipmapped 2D texture width. |
| 74 |*`cudaDevAttrMaxTexture2DMipmappedHeight`* | | Maximum mipmapped 2D texture height. |
| 75 |*`cudaDevAttrComputeCapabilityMajor`* |*`hipDeviceAttributeComputeCapabilityMajor`* | Major compute capability version number. |
| 76 |*`cudaDevAttrComputeCapabilityMinor`* |*`hipDeviceAttributeComputeCapabilityMinor`* | Minor compute capability version number. |
| 77 |*`cudaDevAttrMaxTexture1DMipmappedWidth`* | | Maximum mipmapped 1D texture width. |
| 78 |*`cudaDevAttrStreamPrioritiesSupported`* | | Device supports stream priorities. |
| 79 |*`cudaDevAttrGlobalL1CacheSupported`* | | Device supports caching globals in L1. |
| 80 |*`cudaDevAttrLocalL1CacheSupported`* | | Device supports caching locals in L1. |
| 81 |*`cudaDevAttrMaxSharedMemoryPerMultiprocessor`*|*`hipDeviceAttributeMaxSharedMemoryPerMultiprocessor`*| Maximum shared memory available per multiprocessor in bytes. |
| 82 |*`cudaDevAttrMaxRegistersPerMultiprocessor`* | | Maximum number of 32-bit registers available per multiprocessor. |
| 83 |*`cudaDevAttrManagedMemory`* | | Device can allocate managed memory on this system. |
| 84 |*`cudaDevAttrIsMultiGpuBoard`* |*`hipDeviceAttributeIsMultiGpuBoard`* | Device is on a multi-GPU board. |
| 85 |*`cudaDevAttrMultiGpuBoardGroupID`* | | Unique identifier for a group of devices on the same multi-GPU board. |
| enum |***`cudaError`*** |***`hipError_t`*** | CUDA Error types. |
| enum |***`cudaError_t`*** |***`hipError_t`*** | CUDA Error types. |
| 0 |*`cudaSuccess`* |*`hipSuccess`* | The API call returned with no errors. In the case of query calls, this can also mean that the operation being queried is complete.|
| 1 |*`cudaErrorMissingConfiguration`* | | The device function being invoked (usually via cudaLaunchKernel()) was not previously configured via the cudaConfigureCall() function.|
| 2 |*`cudaErrorMemoryAllocation`* |*`hipErrorMemoryAllocation`* | The API call failed because it was unable to allocate enough memory to perform the requested operation. |
| 3 |*`cudaErrorInitializationError`* |*`hipErrorInitializationError`* | The API call failed because the CUDA driver and runtime could not be initialized. |
| 4 |*`cudaErrorLaunchFailure`* | | An exception occurred on the device while executing a kernel. Common causes include dereferencing an invalid device pointer and accessing out of bounds shared memory. The device cannot be used until cudaThreadExit() is called. All existing device memory allocations are invalid and must be reconstructed if the program is to continue using CUDA. |
| 5 |*`cudaErrorPriorLaunchFailure`* | | This indicated that a previous kernel launch failed. This was previously used for device emulation of kernel launches. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 6 |*`cudaErrorLaunchTimeout`* | | This indicates that the device kernel took too long to execute. This can only occur if timeouts are enabled - see the device property kernelExecTimeoutEnabled for more information. The device cannot be used until cudaThreadExit() is called. All existing device memory allocations are invalid and must be reconstructed if the program is to continue using CUDA.|
| 7 |*`cudaErrorLaunchOutOfResources`* |*`hipErrorLaunchOutOfResources`* | This indicates that a launch did not occur because it did not have appropriate resources. Although this error is similar to cudaErrorInvalidConfiguration, this error usually indicates that the user has attempted to pass too many arguments to the device kernel, or the kernel launch specifies too many threads for the kernel's register count.|
| 8 |*`cudaErrorInvalidDeviceFunction`* | | The requested device function does not exist or is not compiled for the proper device architecture. |
| 9 |*`cudaErrorInvalidConfiguration`* | | This indicates that a kernel launch is requesting resources that can never be satisfied by the current device. Requesting more shared memory per block than the device supports will trigger this error, as will requesting too many threads or blocks. See cudaDeviceProp for more device limitations.|
| 10 |*`cudaErrorInvalidDevice`* |*`hipErrorInvalidDevice`* | This indicates that the device ordinal supplied by the user does not correspond to a valid CUDA device. |
| 11 |*`cudaErrorInvalidValue`* |*`hipErrorInvalidValue`* | This indicates that one or more of the parameters passed to the API call is not within an acceptable range of values. |
| 12 |*`cudaErrorInvalidPitchValue`* | | This indicates that one or more of the pitch-related parameters passed to the API call is not within the acceptable range for pitch.|
| 13 |*`cudaErrorInvalidSymbol`* | | This indicates that the symbol name/identifier passed to the API call is not a valid name or identifier. |
| 14 |*`cudaErrorMapBufferObjectFailed`* | | This indicates that the buffer object could not be mapped. |
| 15 |*`cudaErrorUnmapBufferObjectFailed`* | | This indicates that the buffer object could not be unmapped. |
| 16 |*`cudaErrorInvalidHostPointer`* | | This indicates that at least one host pointer passed to the API call is not a valid host pointer. |
| 17 |*`cudaErrorInvalidDevicePointer`* |*`hipErrorInvalidDevicePointer`* | This indicates that at least one host pointer passed to the API call is not a valid host pointer. |
| 18 |*`cudaErrorInvalidTexture`* | | This indicates that the texture passed to the API call is not a valid texture. |
| 19 |*`cudaErrorInvalidTextureBinding`* | | This indicates that the texture binding is not valid. This occurs if you call cudaGetTextureAlignmentOffset() with an unbound texture.|
| 20 |*`cudaErrorInvalidChannelDescriptor`* | | This indicates that the channel descriptor passed to the API call is not valid. This occurs if the format is not one of the formats specified by cudaChannelFormatKind, or if one of the dimensions is invalid.|
| 21 |*`cudaErrorInvalidMemcpyDirection`* | | This indicates that the direction of the memcpy passed to the API call is not one of the types specified by cudaMemcpyKind. |
| 22 |*`cudaErrorAddressOfConstant`* | | This indicated that the user has taken the address of a constant variable, which was forbidden up until the CUDA 3.1 release. Deprecated This error return is deprecated as of CUDA 3.1. Variables in constant memory may now have their address taken by the runtime via cudaGetSymbolAddress().|
| 23 |*`cudaErrorTextureFetchFailed`* | | This indicated that a texture fetch was not able to be performed. This was previously used for device emulation of texture operations. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 24 |*`cudaErrorTextureNotBound`* | | This indicated that a texture was not bound for access. This was previously used for device emulation of texture operations. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 25 |*`cudaErrorSynchronizationError`* | | This indicated that a synchronization operation had failed. This was previously used for some device emulation functions. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 26 |*`cudaErrorInvalidFilterSetting`* | | This indicates that a non-float texture was being accessed with linear filtering. This is not supported by CUDA. |
| 27 |*`cudaErrorInvalidNormSetting`* | | This indicates that an attempt was made to read a non-float texture as a normalized float. This is not supported by CUDA. |
| 28 |*`cudaErrorMixedDeviceExecution`* | | Mixing of device and device emulation code was not allowed. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 29 |*`cudaErrorCudartUnloading`* | | This indicates that a CUDA Runtime API call cannot be executed because it is being called during process shut down, at a point in time after CUDA driver has been unloaded.|
| 30 |*`cudaErrorUnknown`* |*`hipErrorUnknown`* | This indicates that an unknown internal error has occurred. |
| 31 |*`cudaErrorNotYetImplemented`* | | This indicates that the API call is not yet implemented. Production releases of CUDA will never return this error. Deprecated This error return is deprecated as of CUDA 4.1.|
| 32 |*`cudaErrorMemoryValueTooLarge`* | | This indicated that an emulated device pointer exceeded the 32-bit address range. Deprecated This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.|
| 33 |*`cudaErrorInvalidResourceHandle`* |*`hipErrorInvalidResourceHandle`* | This indicates that a resource handle passed to the API call was not valid. Resource handles are opaque types like cudaStream_t and cudaEvent_t.|
| 34 |*`cudaErrorNotReady`* |*`hipErrorNotReady`* | This indicates that asynchronous operations issued previously have not completed yet. This result is not actually an error, but must be indicated differently than cudaSuccess (which indicates completion). Calls that may return this value include cudaEventQuery() and cudaStreamQuery().|
| 35 |*`cudaErrorInsufficientDriver`* | | This indicates that the installed NVIDIA CUDA driver is older than the CUDA runtime library. This is not a supported configuration. Users should install an updated NVIDIA display driver to allow the application to run.|
| 36 |*`cudaErrorSetOnActiveProcess`* | | This indicates that the user has called cudaSetValidDevices(), cudaSetDeviceFlags(), cudaD3D9SetDirect3DDevice(), cudaD3D10SetDirect3DDevice, cudaD3D11SetDirect3DDevice(), or cudaVDPAUSetVDPAUDevice() after initializing the CUDA runtime by calling non-device management operations (allocating memory and launching kernels are examples of non-device management operations). This error can also be returned if using runtime/driver interoperability and there is an existing CUcontext active on the host thread.|
| 37 |*`cudaErrorInvalidSurface`* | | This indicates that the surface passed to the API call is not a valid surface. |
| 38 |*`cudaErrorNoDevice`* |*`hipErrorNoDevice`* | This indicates that no CUDA-capable devices were detected by the installed CUDA driver. |
| 39 |*`cudaErrorECCUncorrectable`* | | This indicates that an uncorrectable ECC error was detected during execution. |
| 40 |*`cudaErrorSharedObjectSymbolNotFound`* | | This indicates that a link to a shared object failed to resolve. |
| 41 |*`cudaErrorSharedObjectInitFailed`* | | This indicates that initialization of a shared object failed. |
| 42 |*`cudaErrorUnsupportedLimit`* |*`hipErrorUnsupportedLimit`* | This indicates that the cudaLimit passed to the API call is not supported by the active device. |
| 43 |*`cudaErrorDuplicateVariableName`* | | This indicates that multiple global or constant variables (across separate CUDA source files in the application) share the same string name.|
| 44 |*`cudaErrorDuplicateTextureName`* | | This indicates that multiple textures (across separate CUDA source files in the application) share the same string name. |
| 45 |*`cudaErrorDuplicateSurfaceName`* | | This indicates that multiple surfaces (across separate CUDA source files in the application) share the same string name. |
| 46 |*`cudaErrorDevicesUnavailable`* | | This indicates that all CUDA devices are busy or unavailable at the current time. Devices are often busy/unavailable due to use of cudaComputeModeExclusive, cudaComputeModeProhibited or when long running CUDA kernels have filled up the GPU and are blocking new work from starting. They can also be unavailable due to memory constraints on a device that already has active CUDA work being performed.|
| 47 |*`cudaErrorInvalidKernelImage`* | | This indicates that the device kernel image is invalid. |
| 48 |*`cudaErrorNoKernelImageForDevice`* | | This indicates that there is no kernel image available that is suitable for the device. This can occur when a user specifies code generation options for a particular CUDA source file that do not include the corresponding device configuration.|
| 49 |*`cudaErrorIncompatibleDriverContext`* | | This indicates that the current context is not compatible with this the CUDA Runtime. This can only occur if you are using CUDA Runtime/Driver interoperability and have created an existing Driver context using the driver API. The Driver context may be incompatible either because the Driver context was created using an older version of the API, because the Runtime API call expects a primary driver context and the Driver context is not primary, or because the Driver context has been destroyed. Please see Interactions with the CUDA Driver API" for more information.|
| 50 |*`cudaErrorPeerAccessAlreadyEnabled`* |*`hipErrorPeerAccessAlreadyEnabled`* | This error indicates that a call to cudaDeviceEnablePeerAccess() is trying to re-enable peer addressing on from a context which has already had peer addressing enabled.|
| 51 |*`cudaErrorPeerAccessNotEnabled`* |*`hipErrorPeerAccessNotEnabled`* | This error indicates that a call to cudaDeviceEnablePeerAccess() is trying to re-enable peer addressing on from a context which has already had peer addressing enabled.|
| 52 | | | *reserved* |
| 53 | | | *reserved* |
| 54 |*`cudaErrorDeviceAlreadyInUse`* | | This indicates that a call tried to access an exclusive-thread device that is already in use by a different thread. |
| 55 |*`cudaErrorProfilerDisabled`* | | This indicates profiler is not initialized for this run. This can happen when the application is running with external profiling tools like visual profiler.|
| 56 |*`cudaErrorProfilerNotInitialized`* | | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to attempt to enable/disable the profiling via cudaProfilerStart or cudaProfilerStop without initialization.|
| 57 |*`cudaErrorProfilerAlreadyStarted`* | | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to call cudaProfilerStart() when profiling is already enabled.|
| 58 |*`cudaErrorProfilerAlreadyStopped`* | | Deprecated This error return is deprecated as of CUDA 5.0. It is no longer an error to call cudaProfilerStop() when profiling is already disabled.|
| 59 |*`cudaErrorAssert`* | | An assert triggered in device code during kernel execution. The device cannot be used again until cudaThreadExit() is called. All existing allocations are invalid and must be reconstructed if the program is to continue using CUDA.|
| 60 |*`cudaErrorTooManyPeers`* | | This error indicates that the hardware resources required to enable peer access have been exhausted for one or more of the devices passed to cudaEnablePeerAccess().|
| 61 |*`cudaErrorHostMemoryAlreadyRegistered`* | *`hipErrorHostMemoryAlreadyRegistered`* | This error indicates that the memory range passed to cudaHostRegister() has already been registered. |
| 62 |*`cudaErrorHostMemoryNotRegistered`* | *`hipErrorHostMemoryNotRegistered`* | This error indicates that the pointer passed to cudaHostUnregister() does not correspond to any currently registered memory region.|
| 63 |*`cudaErrorOperatingSystem`* | | This error indicates that an OS call failed. |
| 64 |*`cudaErrorPeerAccessUnsupported`* | | This error indicates that P2P access is not supported across the given devices. |
| 65 |*`cudaErrorLaunchMaxDepthExceeded`* | | This error indicates that a device runtime grid launch did not occur because the depth of the child grid would exceed the maximum supported number of nested grid launches.|
| 66 |*`cudaErrorLaunchFileScopedTex`* | | This error indicates that a grid launch did not occur because the kernel uses filescoped textures which are unsupported by the device runtime. Kernels launched via the device runtime only support textures created with the Texture Object API's.|
| 67 |*`cudaErrorLaunchFileScopedSurf`* | | This error indicates that a grid launch did not occur because the kernel uses filescoped surfaces which are unsupported by the device runtime. Kernels launched via the device runtime only support surfaces created with the Surface Object API's.|
| 68 |*`cudaErrorSyncDepthExceeded`* | | This error indicates that a call to cudaDeviceSynchronize made from the device runtime failed because the call was made at grid depth greater than than either the default (2 levels of grids) or user specified device limit cudaLimitDevRuntimeSyncDepth. To be able to synchronize on launched grids at a greater depth successfully, the maximum nested depth at which cudaDeviceSynchronize will be called must be specified with the cudaLimitDevRuntimeSyncDepth limit to the cudaDeviceSetLimit api before the host-side launch of a kernel using the device runtime. Keep in mind that additional levels of sync depth require the runtime to reserve large amounts of device memory that cannot be used for user allocations.|
| 69 |*`cudaErrorLaunchPendingCountExceeded`* | | This error indicates that a device runtime grid launch failed because the launch would exceed the limit cudaLimitDevRuntimePendingLaunchCount. For this launch to proceed successfully, cudaDeviceSetLimit must be called to set the cudaLimitDevRuntimePendingLaunchCount to be higher than the upper bound of outstanding launches that can be issued to the device runtime. Keep in mind that raising the limit of pending device runtime launches will require the runtime to reserve device memory that cannot be used for user allocations.|
| 70 |*`cudaErrorNotPermitted`* | | This error indicates the attempted operation is not permitted. |
| 71 |*`cudaErrorNotSupported`* | | This error indicates the attempted operation is not supported on the current system or device. |
| 72 |*`cudaErrorHardwareStackError`* | | Device encountered an error in the call stack during kernel execution, possibly due to stack corruption or exceeding the stack size limit. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 73 |*`cudaErrorIllegalInstruction`* | | The device encountered an illegal instruction during kernel execution The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 74 |*`cudaErrorMisalignedAddress`* | | The device encountered a load or store instruction on a memory address which is not aligned. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 75 |*`cudaErrorInvalidAddressSpace`* | | While executing a kernel, the device encountered an instruction which can only operate on memory locations in certain address spaces (global, shared, or local), but was supplied a memory address not belonging to an allowed address space. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 76 |*`cudaErrorInvalidPc`* | | The device encountered an invalid program counter. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 77 |*`cudaErrorIllegalAddress`* | | The device encountered a load or store instruction on an invalid memory address. The context cannot be used, so it must be destroyed (and a new one should be created). All existing device memory allocations from this context are invalid and must be reconstructed if the program is to continue using CUDA.|
| 78 |*`cudaErrorInvalidPtx`* | | A PTX compilation failed. The runtime may fall back to compiling PTX if an application does not contain a suitable binary for the current device.|
| 79 |*`cudaErrorInvalidGraphicsContext`* | | This indicates an error with the OpenGL or DirectX context. |
| 0x7f |*`cudaErrorStartupFailure`* | | This indicates an internal startup failure in the CUDA runtime. |
| 1000 |*`cudaErrorApiFailureBase`* | | Any unhandled CUDA driver error is added to this value and returned via the runtime. Production releases of CUDA should not return such errors. Deprecated This error return is deprecated as of CUDA 4.1.|
| enum |***`cudaFuncCache`*** |***`hipFuncCache_t`*** | CUDA function cache configurations. |
| 0 |*`cudaFuncCachePreferNone`* |*`hipFuncCachePreferNone`* | Default function cache configuration, no preference. |
| 1 |*`cudaFuncCachePreferShared`* |*`hipFuncCachePreferShared`* | Prefer larger shared memory and smaller L1 cache. |
| 2 |*`cudaFuncCachePreferL1`* |*`hipFuncCachePreferL1`* | Prefer larger L1 cache and smaller shared memory. |
| 3 |*`cudaFuncCachePreferEqual`* |*`hipFuncCachePreferEqual`* | Prefer equal size L1 cache and shared memory. |
| enum |***`cudaGraphicsCubeFace`*** | | CUDA graphics interop array indices for cube maps. |
| 0x00 |*`cudaGraphicsCubeFacePositiveX`* | | Positive X face of cubemap. |
| 0x01 |*`cudaGraphicsCubeFaceNegativeX`* | | Negative X face of cubemap. |
| 0x02 |*`cudaGraphicsCubeFacePositiveY`* | | Positive Y face of cubemap. |
| 0x03 |*`cudaGraphicsCubeFaceNegativeY`* | | Negative Y face of cubemap. |
| 0x04 |*`cudaGraphicsCubeFacePositiveZ`* | | Positive Z face of cubemap. |
| 0x05 |*`cudaGraphicsCubeFaceNegativeZ`* | | Negative Z face of cubemap. |
| enum |***`cudaGraphicsMapFlags`*** | | CUDA graphics interop map flags. |
| 0 |*`cudaGraphicsMapFlagsNone`* | | Default; Assume resource can be read/written. |
| 1 |*`cudaGraphicsMapFlagsReadOnly`* | | CUDA will not write to this resource. |
| 2 |*`cudaGraphicsMapFlagsWriteDiscard`* | | CUDA will only write to and will not read from this resource. |
| enum |***`cudaGraphicsRegisterFlags`*** | | CUDA graphics interop register flags. |
| 0 |*`cudaGraphicsRegisterFlagsNone`* | | Default. |
| 1 |*`cudaGraphicsRegisterFlagsReadOnly`* | | CUDA will not write to this resource. |
| 2 |*`cudaGraphicsRegisterFlagsWriteDiscard`* | | CUDA will only write to and will not read from this resource. |
| 4 |*`cudaGraphicsRegisterFlagsSurfaceLoadStore`* | | CUDA will bind this resource to a surface reference. |
| 8 |*`cudaGraphicsRegisterFlagsTextureGather`* | | CUDA will perform texture gather operations on this resource. |
| enum |***`cudaLimit`*** |***`hipLimit_t`*** | CUDA Limits. |
| 0x00 |*`cudaLimitStackSize`* | | GPU thread stack size. |
| 0x01 |*`cudaLimitPrintfFifoSize`* | | GPU printf/fprintf FIFO size. |
| 0x02 |*`cudaLimitMallocHeapSize`* |*`hipLimitMallocHeapSize`* | GPU malloc heap size. |
| 0x03 |*`cudaLimitDevRuntimeSyncDepth`* | | GPU device runtime synchronize depth. |
| 0x04 |*`cudaLimitDevRuntimePendingLaunchCount`* | | GPU device runtime pending launch count. |
| enum |***`cudaMemcpyKind`*** |***`hipMemcpyKind`*** | CUDA memory copy types. |
| 0 |*`cudaMemcpyHostToHost`* |*`hipMemcpyHostToHost`* | Host -> Host. |
| 1 |*`cudaMemcpyHostToDevice`* |*`hipMemcpyHostToDevice`* | Host -> Device. |
| 2 |*`cudaMemcpyDeviceToHost`* |*`hipMemcpyDeviceToHost`* | Device -> Host. |
| 3 |*`cudaMemcpyDeviceToDevice`* |*`hipMemcpyDeviceToDevice`* | Device -> Device. |
| 4 |*`cudaMemcpyDefault`* |*`hipMemcpyDefault`* | Default based unified virtual address space. |
| enum |***`cudaMemoryType`*** |***`hipMemoryType`*** | CUDA memory types. |
| 1 |*`cudaMemoryTypeHost`* |*`hipMemoryTypeHost`* | Host memory. |
| 2 |*`cudaMemoryTypeDevice`* |*`hipMemoryTypeDevice`* | Device memory. |
| enum |***`cudaResourceType`*** | | CUDA resource types. |
| 0 |*`cudaResourceTypeArray`* | | Array resource. |
| 1 |*`cudaResourceTypeMipmappedArray`* | | Mipmapped array resource. |
| 2 |*`cudaResourceTypeLinear`* | | Linear resource. |
| 3 |*`cudaResourceTypePitch2D`* | | Pitch 2D resource. |
| enum |***`cudaResourceViewFormat`*** | | CUDA texture resource view formats. |
| 0x00 |*`cudaResViewFormatNone`* | | No resource view format (use underlying resource format). |
| 0x01 |*`cudaResViewFormatUnsignedChar1`* | | 1 channel unsigned 8-bit integers. |
| 0x02 |*`cudaResViewFormatUnsignedChar2`* | | 2 channel unsigned 8-bit integers. |
| 0x03 |*`cudaResViewFormatUnsignedChar4`* | | 4 channel unsigned 8-bit integers. |
| 0x04 |*`cudaResViewFormatSignedChar1`* | | 1 channel signed 8-bit integers. |
| 0x05 |*`cudaResViewFormatSignedChar2`* | | 2 channel signed 8-bit integers. |
| 0x06 |*`cudaResViewFormatSignedChar4`* | | 4 channel signed 8-bit integers. |
| 0x07 |*`cudaResViewFormatUnsignedShort1`* | | 1 channel unsigned 16-bit integers. |
| 0x08 |*`cudaResViewFormatUnsignedShort2`* | | 2 channel unsigned 16-bit integers. |
| 0x09 |*`cudaResViewFormatUnsignedShort4`* | | 4 channel unsigned 16-bit integers. |
| 0x0a |*`cudaResViewFormatSignedShort1`* | | 1 channel signed 16-bit integers. |
| 0x0b |*`cudaResViewFormatSignedShort2`* | | 2 channel signed 16-bit integers. |
| 0x0c |*`cudaResViewFormatSignedShort4`* | | 4 channel signed 16-bit integers. |
| 0x0d |*`cudaResViewFormatUnsignedInt1`* | | 1 channel unsigned 32-bit integers. |
| 0x0e |*`cudaResViewFormatUnsignedInt2`* | | 2 channel unsigned 32-bit integers. |
| 0x0f |*`cudaResViewFormatUnsignedInt4`* | | 4 channel unsigned 32-bit integers. |
| 0x10 |*`cudaResViewFormatSignedInt1`* | | 1 channel signed 32-bit integers. |
| 0x11 |*`cudaResViewFormatSignedInt2`* | | 2 channel signed 32-bit integers. |
| 0x12 |*`cudaResViewFormatSignedInt4`* | | 4 channel signed 32-bit integers. |
| 0x13 |*`cudaResViewFormatHalf1`* | | 1 channel 16-bit floating point. |
| 0x14 |*`cudaResViewFormatHalf2`* | | 2 channel 16-bit floating point. |
| 0x15 |*`cudaResViewFormatHalf4`* | | 4 channel 16-bit floating point. |
| 0x16 |*`cudaResViewFormatFloat1`* | | 1 channel 32-bit floating point. |
| 0x17 |*`cudaResViewFormatFloat2`* | | 2 channel 32-bit floating point. |
| 0x18 |*`cudaResViewFormatFloat4`* | | 4 channel 32-bit floating point. |
| 0x19 |*`cudaResViewFormatUnsignedBlockCompressed1`* | | Block compressed 1. |
| 0x1a |*`cudaResViewFormatUnsignedBlockCompressed2`* | | Block compressed 2. |
| 0x1b |*`cudaResViewFormatUnsignedBlockCompressed3`* | | Block compressed 3. |
| 0x1c |*`cudaResViewFormatUnsignedBlockCompressed4`* | | Block compressed 4 unsigned. |
| 0x1d |*`cudaResViewFormatSignedBlockCompressed4`* | | Block compressed 4 signed. |
| 0x1e |*`cudaResViewFormatUnsignedBlockCompressed5`* | | Block compressed 5 unsigned. |
| 0x1f |*`cudaResViewFormatSignedBlockCompressed5`* | | Block compressed 5 signed. |
| 0x20 |*`cudaResViewFormatUnsignedBlockCompressed6H`* | | Block compressed 6 unsigned half-float. |
| 0x21 |*`cudaResViewFormatSignedBlockCompressed6H`* | | Block compressed 6 signed half-float. |
| 0x22 |*`cudaResViewFormatUnsignedBlockCompressed7`* | | Block compressed 7. |
| enum |***`cudaSharedMemConfig`*** |***`hipSharedMemConfig`*** | CUDA shared memory configuration. |
| 0 |*`cudaSharedMemBankSizeDefault`* |*`hipSharedMemBankSizeDefault`* | |
| 1 |*`cudaSharedMemBankSizeFourByte`* |*`hipSharedMemBankSizeFourByte`* | |
| 2 |*`cudaSharedMemBankSizeEightByte`* |*`hipSharedMemBankSizeEightByte`* | |
| enum |***`cudaSurfaceBoundaryMode`*** | | CUDA Surface boundary modes. |
| 0 |*`cudaBoundaryModeZero`* | | Zero boundary mode. |
| 1 |*`cudaBoundaryModeClamp`* | | Clamp boundary mode. |
| 2 |*`cudaBoundaryModeTrap`* | | Trap boundary mode. |
| enum |***`cudaSurfaceFormatMode`*** | | CUDA Surface format modes. |
| 0 |*`cudaFormatModeForced`* | | Forced format mode. |
| 1 |*`cudaFormatModeAuto`* | | Auto format mode. |
| enum |***`cudaTextureAddressMode`*** | | CUDA texture address modes. |
| 0 |*`cudaAddressModeWrap`* | | Wrapping address mode. |
| 1 |*`cudaAddressModeClamp`* | | Clamp to edge address mode. |
| 2 |*`cudaAddressModeMirror`* | | Mirror address mode. |
| 3 |*`cudaAddressModeBorder`* | | Border address mode. |
| enum |***`cudaTextureFilterMode`*** |***`hipTextureFilterMode`*** | Point filter mode. |
| 0 |*`cudaFilterModePoint`* |*`hipFilterModePoint`* | Linear filter mode. |
| 1 |*`cudaFilterModeLinear`* | | Clamp to edge address mode. |
| enum |***`cudaTextureReadMode`*** |***`hipTextureReadMode`*** | CUDA texture read modes. |
| 0 |*`cudaReadModeElementType`* |*`hipReadModeElementType`* | Read texture as specified element type. |
| 1 |*`cudaReadModeNormalizedFloat`* | | Read texture as normalized float. |
| struct | `cudaArray` | `hipArray` | CUDA array [opaque]. |
| typedef | `cudaArray_t` | `hipArray *` | CUDA array pointer. |
| typedef | `cudaArray_const_t` | `const hipArray *` | CUDA array (as source copy argument). |
| enum | `cudaError` | `hipError_t` | CUDA Error types. |
| typedef | `cudaError_t` | `hipError_t` | CUDA Error types. |
| typedef | `cudaEvent_t` | `hipEvent_t` | CUDA event types. |
| typedef | `cudaGraphicsResource_t` | | CUDA graphics resource types. |
| typedef | `cudaMipmappedArray_t` | | CUDA mipmapped array. |
| typedef | `cudaMipmappedArray_const_t` | | CUDA mipmapped array (as source argument). |
| enum |***`cudaOutputMode`*** | | CUDA Profiler Output modes. |
| 0x00 |*`cudaKeyValuePair`* | | Output mode Key-Value pair format. |
| 0x01 |*`cudaCSV`* | | Output mode Comma separated values format. |
| typedef | `cudaOutputMode_t` | | CUDA output file modes. |
| typedef | `cudaStream_t` | `hipStream_t` | CUDA stream. |
| typedef | `cudaSurfaceObject_t` | | An opaque value that represents a CUDA Surface object. |
| typedef | `cudaTextureObject_t` | | An opaque value that represents a CUDA texture object. |
| typedef | `CUuuid_stcudaUUID_t` | | CUDA UUID types. |
| define | `CUDA_IPC_HANDLE_SIZE` | | CUDA IPC Handle Size. |
| define | `cudaArrayCubemap` | | Must be set in cudaMalloc3DArray to create a cubemap CUDA array. |
| define | `cudaArrayDefault` | | Default CUDA array allocation flag. |
| define | `cudaArrayLayered` | | Must be set in cudaMalloc3DArray to create a layered CUDA array. |
| define | `cudaArraySurfaceLoadStore` | | Must be set in cudaMallocArray or cudaMalloc3DArray in order to bind surfaces to the CUDA array. |
| define | `cudaArrayTextureGather` | | Must be set in cudaMallocArray or cudaMalloc3DArray in order to perform texture gather operations on the CUDA array. |
| define | `cudaDeviceBlockingSync` | `hipDeviceScheduleBlockingSync` | Device flag - Use blocking synchronization. Deprecated as of CUDA 4.0 and replaced with cudaDeviceScheduleBlockingSync. |
| define | `cudaDeviceLmemResizeToMax` | | Device flag - Keep local memory allocation after launch. |
| define | `cudaDeviceMapHost` | | Device flag - Support mapped pinned allocations. |
| define | `cudaDeviceMask` | | Device flags mask. |
| define | `cudaDevicePropDontCare` | | Empty device properties. |
| define | `cudaDeviceScheduleAuto` | `hipDeviceScheduleAuto` | Device flag - Automatic scheduling. |
| define | `cudaDeviceScheduleBlockingSync` | `hipDeviceScheduleBlockingSync` | Device flag - Use blocking synchronization. |
| define | `cudaDeviceScheduleMask` | `hipDeviceScheduleMask` | Device schedule flags mask. |
| define | `cudaDeviceScheduleSpin` | `hipDeviceScheduleSpin` | Device flag - Spin default scheduling. |
| define | `cudaDeviceScheduleYield` | `hipDeviceScheduleYield` | Device flag - Yield default scheduling. |
| define | `cudaEventDefault` | `hipEventDefault` | Default event flag. |
| define | `cudaEventDisableTiming` | `hipEventDisableTiming` | Event will not record timing data. |
| define | `cudaEventInterprocess` | `hipEventInterprocess` | Event is suitable for interprocess use. cudaEventDisableTiming must be set. |
| define | `cudaHostAllocDefault` | `hipHostMallocDefault` | Default page-locked allocation flag. |
| define | `cudaHostAllocMapped` | `hipHostMallocMapped` | Map allocation into device space. |
| define | `cudaHostAllocPortable` | `hipHostMallocPortable` | Pinned memory accessible by all CUDA contexts. |
| define | `cudaHostAllocWriteCombined` | `hipHostMallocWriteCombined` | Write-combined memory. |
| define | `cudaHostRegisterDefault` | `hipHostRegisterDefault` | Default host memory registration flag. |
| define | `cudaHostRegisterIoMemory` | `hipHostRegisterIoMemory` | Memory-mapped I/O space. |
| define | `cudaHostRegisterMapped` | `hipHostRegisterMapped` | Map registered memory into device space. |
| define | `cudaHostRegisterPortable` | `hipHostRegisterPortable` | Pinned memory accessible by all CUDA contexts. |
| define | `cudaIpcMemLazyEnablePeerAccess` | `hipIpcMemLazyEnablePeerAccess` | Automatically enable peer access between remote devices as needed. |
| define | `cudaMemAttachGlobal` | | Memory can be accessed by any stream on any device. |
| define | `cudaMemAttachHost` | | Memory cannot be accessed by any stream on any device. |
| define | `cudaMemAttachSingle` | | Memory can only be accessed by a single stream on the associated device. |
| define | `cudaOccupancyDefault` | | Default behavior. |
| define | `cudaOccupancyDisableCachingOverride` | | Assume global caching is enabled and cannot be automatically turned off. |
| define | `cudaPeerAccessDefault` | | Default peer addressing enable flag. |
| define | `cudaStreamDefault` | `hipStreamDefault` | Default stream flag. |
| define | `cudaStreamLegacy` | | Default stream flag. |
| define | `cudaStreamNonBlocking` | `hipStreamNonBlocking` | Stream does not synchronize with stream 0 (the NULL stream). |
| define | `cudaStreamPerThread` | | Per-thread stream handle. |
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@@ -0,0 +1,508 @@
"""
Copyright (c) 2015-2017 Advanced Micro Devices, Inc. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
"""
1. This files uses Python3 to run
List of device functions:
acosf
acoshf
asinf
asinhf
atan2f
atanf
atanhf
cbrtf
ceilf
copysignf
cosf
coshf
cospif
cyl_bessel_i0f
cyl_bessel_i1f
erfcf
erfcinvf
erfcxf
erff
erfinvf
exp10f
exp2f
expf
expm1f
fabsf
fdimf
fdividef
floorf
fmaf
fmaxf
fminf
fmodf
frexpf
hypotf
ilogbf
isfinite
isinf
isnan
j0f
j1f
jnf
ldexpf
lgammaf
llrintf
llroundf
log10f
log1pf
logbf
lrintf
lroundf
modff
nanf
nearbyintf
nextafterf
norm3df
norm4df
normcdff
normcdfinvf
normf
powf
rcbrtf
remainderf
remquof
rhypotf
rintf
rnorm3df
rnorm4df
rnormf
roundf
rsqrtf
scalblnf
scalbnf
signbit
sincosf
sincospif
sinf
sinhf
sinpif
sqrtf
tanf
tanhf
tgammaf
truncf
y0f
y1f
ynf
acos
acosh
asin
asinh
atan
atan2
atanh
cbrt
ceil
copysign
cos
cosh
cospi
cyl_bessel_i0
cyl_bessel_i1
erf
erfc
erfcinv
erfcx
erfinv
exp
exp10
exp2
expm1
fabs
fdim
floor
fma
fmax
fmin
fmod
frexp
hypot
ilogb
isfinite
isinf
isnan
j0
j1
jn
ldexp
lgamma
llrint
llround
log
log10
log1p
log2
logb
lrint
lround
modf
nan
nearbyint
nextafter
norm
norm3d
norm4d
normcdf
normcdfinv
pow
rcbrt
remainder
remquo
rhypot
rint
rnorm
rnorm3d
rnorm4d
round
rsqrt
scalbln
scalbn
signbit
sin
sincos
sincospi
sinh
sinpi
sqrt
tan
tanh
tgamma
trunc
y0
y1
yn
__cosf
__exp10f
__expf
__fadd_rd
__fadd_rn
__fadd_ru
__fadd_rz
__fdiv_rd
__fdiv_rn
__fdiv_ru
__fdiv_rz
__fdividef
__fmaf_rd
__fmaf_rn
__fmaf_ru
__fmaf_rz
__fmul_rd
__fmul_rn
__fmul_ru
__fmul_rz
__frcp_rd
__frcp_rn
__frcp_ru
__frcp_rz
__frsqrt_rn
__fsqrt_rd
__fsqrt_rn
__fsqrt_ru
__fsqrt_rz
__fsub_rd
__fsub_rn
__fsub_ru
__log10f
__log2f
__logf
__powf
__saturatef
__sincosf
__sinf
__tanf
__dadd_rd
__dadd_rn
__dadd_ru
__dadd_rz
__ddiv_rd
__ddiv_rn
__ddiv_ru
__ddiv_rz
__dmul_rd
__dmul_rn
__dmul_ru
__dmul_rz
__drcp_rd
__drcp_rn
__drcp_ru
__drcp_rz
__dsqrt_rd
__dsqrt_rn
__dsqrt_ru
__dsqrt_rz
__dsub_rd
__dsub_rn
__dsub_ru
__dsub_rz
__fma_rd
__fma_rn
__fma_ru
__fma_rz
__brev
__brevll
__byte_perm
__clz
__clzll
__ffs
__ffsll
__hadd
__mul24
__mul64hi
__mulhi
__popc
__popcll
__rhadd
__sad
__uhadd
__umul24
__umul64hi
__umulhi
__urhadd
__usad
__double2float_rd
__double2float_rn
__double2float_ru
__double2float_rz
__double2hiint
__double2int_rd
__double2int_rn
__double2int_ru
__double2int_rz
__double2ll_rd
__double2ll_rn
__double2ll_ru
__double2ll_rz
__double2loint
__double2uint_rd
__double2uint_rn
__double2uint_ru
__double2uint_rz
__double2ull_rd
__double2ull_rn
__double2ull_ru
__double2ull_rz
__double_as_longlong
__float2half_rn
__half2float
__float2half_rn
__half2float
__float2int_rd
__float2int_rn
__float2int_ru
__float2int_rz
__float2ll_rd
__float2ll_rn
__float2ll_ru
__float2ll_rz
__float2uint_rd
__float2uint_rn
__float2uint_ru
__float2uint_rz
__float2ull_rd
__float2ull_rn
__float2ull_ru
__float2ull_rz
__float_as_int
__float_as_uint
__hiloint2double
__int2double_rn
__int2float_rd
__int2float_rn
__int2float_ru
__int2float_rz
__int_as_float
__ll2double_rd
__ll2double_rn
__ll2double_ru
__ll2double_rz
__ll2float_rd
__ll2float_rn
__ll2float_ru
__ll2float_rz
__longlong_as_double
__uint2double_rn
__uint2float_rd
__uint2float_rn
__uint2float_ru
__uint2float_rz
__uint_as_float
__ull2double_rd
__ull2double_rn
__ull2double_ru
__ull2double_rz
__ull2float_rd
__ull2float_rn
__ull2float_ru
__ull2float_rz
__heq
__hge
__hgt
__hisinf
__hisnan
__hle
__hlt
__hne
__hbeq2
__hbge2
__hbgt2
__hble2
__hblt2
__hbne2
__heq2
__hge2
__hgt2
__hisnan2
__hle2
__hlt2
__hne2
__float22half2_rn
__float2half
__float2half2_rn
__float2half_rd
__float2half_rn
__float2half_ru
__float2half_rz
__floats2half2_rn
__half22float2
__half2float
half2half2
__half2int_rd
__half2int_rn
__half2int_ru
__half2int_rz
__half2ll_rd
__half2ll_rn
__half2ll_ru
__half2ll_rz
__half2short_rd
__half2short_rn
__half2short_ru
__half2short_rz
__half2uint_rd
__half2uint_rn
__half2uint_ru
__half2uint_rz
__half2ull_rd
__half2ull_rn
__half2ull_ru
__half2ull_rz
__half2ushort_rd
__half2ushort_rn
__half2ushort_ru
__half2ushort_rz
__half_as_short
__half_as_ushort
__halves2half2
__high2float
__high2half
__high2half2
__highs2half2
__int2half_rd
__int2half_rn
__int2half_ru
__int2half_rz
__ll2half_rd
__ll2half_rn
__ll2half_ru
__ll2half_rz
__low2float
__low2half
__low2half2
__low2half2
__lowhigh2highlow
__lows2half2
__short2half_rd
__short2half_rn
__short2half_ru
__short2half_rz
__uint2half_rd
__uint2half_rn
__uint2half_ru
__uint2half_rz
__ull2half_rd
__ull2half_rn
__ull2half_ru
__ull2half_rz
__ushort2half_rd
__ushort2half_rn
__ushort2half_ru
__ushort2half_rz
__ushort_as_half
"""
# The dictionary is to place description of each device function. Expand it to all the device functions
deviceFuncDesc = {'acosf': "This function returns floating point of arc cosine from a floating point input"}
fnames = ["../../include/hip/hcc_detail/math_functions.h","../../include/hip/hcc_detail/device_functions.h","../../include/hip/hcc_detail/hip_fp16.h"]
markdownFileName = "./hip-math-api.md"
preamble = "# HIP MATH APIs Documentation \n"+\
"HIP supports most of the device functions supported by CUDA. Way to find the unsupported one is to search for the function and check its description\n" + \
"Note: This document is not human generated. Any changes to this file will be discarded. Please make changes to Python3 script docs/markdown/device_md_gen.py\n\n" + \
"## For Developers \n" + \
"If you add or fixed a device function, make sure to add a signature of the function and definition later.\n" + \
"For example, if you want to add `__device__ float __dotf(float4, float4)`, which does a dot product on 4 float vector components \n" + \
"The way to add to the header is, \n" + \
"```cpp \n" + \
"__device__ static float __dotf(float4, float4); \n" + \
"/*Way down in the file....*/\n" + \
"__device__ static inline float __dotf(float4 x, float4 y) { \n" + \
" /*implementation*/\n}\n" + \
"```\n\n" + \
"This helps python script to add the device function newly declared into markdown documentation (as it looks at functions with `;` at the end and `__device__` at the beginning)\n\n" + \
"The next step would be to add Description to `deviceFuncDesc` dictionary in python script.\n" + \
"From the above example, it can be writtern as,\n`deviceFuncDesc['__dotf'] = 'This functions takes 2 4 component float vector and outputs dot product across them'`\n\n"
def generateSnippet(name, description, signature):
return "### " + name + "\n" + \
"```cpp \n" + signature + "\n```\n" + \
"**Description:** " + description + "\n\n\n"
def getName(line):
l1 = line.split('(')
l2 = l1[0].split(' ')
return l2[-1]
with open(markdownFileName, 'w') as mdfd:
mdfd.truncate()
mdfd.write(preamble)
for fname in fnames:
with open(fname) as fd:
lines = fd.readlines()
for line in lines:
if line.find('HIP_FAST_MATH') != -1:
break;
if line.find('__device__') != -1 and line.find(';') != -1 and line.find('hip') == -1:
name = getName(line)
if line.find('//') == -1:
if name in deviceFuncDesc:
mdfd.write(generateSnippet(name, deviceFuncDesc[name], line))
else:
mdfd.write(generateSnippet(name, "Supported", line))
else:
mdfd.write(generateSnippet(name, "**NOT Supported**", line))
fd.close()
mdfd.close()
docs/markdown/hip-math-api.md
+3838
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Fichier diff supprimé car celui-ci est trop grand Voir la Diff
docs/markdown/hip_bugs.md
+221
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@@ -0,0 +1,221 @@
# HIP Bugs
<!-- toc -->
- [Errors related to undefined reference to `__hcLaunchKernel__***__grid_launch_parm**`](#errors-related-to-undefined-reference-to-__hclaunchkernel____grid_launch_parm)
- [What is the current limitation of HIP Generic Grid Launch method?](#what-is-the-current-limitation-of-hip-generic-grid-launch-method)
- [Errors related to `no matching constructor`](#errors-related-to-no-matching-constructor)
- [HIP is more restrictive in enforcing restrictions](#hip-is-more-restrictive-in-enforcing-restrictions)
<!-- tocstop -->
### Errors related to undefined reference to `__hcLaunchKernel__***__grid_launch_parm**`
Some common code practices may lead to hipcc generating a error with the form :
```
undefined reference to `__hcLaunchKernel__ZN15vecAddNamespace6vecAddIidEEv16grid_launch_parmPT0_S3_S3_T_
```
Or:
```
error: weak declaration cannot have internal linkage
```
Suggested workarounds:
- Avoid use of static with kernel definition:
```c++
static __global__ MyKernel
```
- Avoid defining kernels in anonymous namespace :
```c++
namespace {
__global__ MyKernel
}
```
### Can't find kernels inside dynamic linked library
HCC requires use of the "-Bdynamic" flag when creating a dynamic library which contains kernels. The dynamic flag causes the symbols to be created with a signature which allows HCC to discover and load the kernels in the dynamic library. This flag is often not set by default and must be added to the link step of the library. If not done, HCC will be unable to find the kernels defined in the library, and will emit a message such as:
```
HSADevice::CreateKernel(): Unable to create kernel"
```
To correct, add the following flag to hcc or hipcc:
```
$ hipcc -Wl,-Bsymbolic ...
```
### What is the current limitation of HIP Generic Grid Launch method?
1. __global__ functions cannot be marked as static or put in an unnamed namespace i.e. they cannot be given internal linkage (this would clash with __attribute__((weak)));
2. using the macro based dispatch mechanism i.e. hipLaunchKernel* only works for functions that take no more than 20 arguments (this limit can be increased up to 126, and is temporary until we can enable C++14 mode and use variadic generic lambdas); no such limitation applies do dispatching directly through grid_launch.
### Errors related to `no matching constructor`
The symptom is the compiler would complain about errors like `no matching constructor` for classes/structs passed as arguments into a GPU kernel. Often, this is caused by a design limitation in HCC where array-typed member variables inside a class/struct can’t be correctly passed into GPU kernels. To mitigate this issue, a custom serializer/deserializer pair is provided.
For example, `Foo` in the code snippets below contains an array-typed member variable `table`, which would fail the compiler if used as a kernel argument.
```
struct Foo {
float _data;
// table is an array, which makes foo
int table[3];
};
```
A workaround is to provide a custom serializer on host side which appends the contents of the array as kernel arguments, and a custome deserializaer on the device path to reconstruct the array inside the GPU kernels.
The deserializer can not be a function template, and should have scalar-typed parameters of the number equals to the length of the array-typed member variable. For example:
```
struct Foo {
float _data;
int _table[3];
#ifdef __HCC__
// user-provided CPU serializer
// Append the contents of the array member as kernel arguments
__attribute__((annotate(“serialize”)))
void __cxxamp_serialize(Kalmar::Serialize &s) const {
s.Append(sizeof(float), &_data);
for (int i = 0; i < 3; ++i)
s.Append(sizeof(int), &_table[i]);
}
// user-provided GPU deserializer
// table has 3 int elements, so deserializer must have 3 int parameters.
__attribute__((annotate(“user_deserialize”)))
Foo(float d, int x0, int x1, int x2) [[cpu]][[hc]] {
_data = d;
_table[0] = x0;
_table[1] = x1;
_table[2] = x2;
}
#endif
};
```
Rather than create serializer functions, another workaround is to pass the member fields from the structure as simple data types.
Note a class or struct can contain only one "user_deserialize" constructor.
For types which contain arrays which are based on template parameter, you can use partial template instantiation to implement one constructor per specialization.
However, an easier approach may be to create one user_deserializer which processes the maximum supported dimension.
This will take more memory in the structure and also require additional kernel arguments, but this may have little performance impact and the conversion is easier than partial template specialization. An example:
```
#define MAX_Dim 4
template<typename T, int Dim> struct MyArray {
T* dataPtr_;
//int size_[Dim]; // Original code with template-sized Dims
int size_[MAX_dim]; // Workaround code - allocate an array big enough for all dims so one serializer works.
...
#ifdef __HCC__
__attribute__((annotate("serialize")))
void __cxxamp_serialize(Kalmar::Serialize &s) const {
s.Append(sizeof(float), &_dataPtr);
for (int i=0; i<MAX_Dim; i++) {
s.Append(sizeof(size_[0]), &size_[i]);
}
}
__attribute__((annotate("user_deserialize")))
MyArray(T* data, int size0, int size1, int size2, int size3) [[cpu]][[hc]] {
data_ = data;
size_[0] = size0;
size_[1] = size1;
size_[2] = size2;
size_[3] = size3;
}
#endif
```
### HIP is more restrictive in enforcing restrictions
The language specification for HIP and CUDA forbid calling a
`__device__` function in a `__host__` context. In practice, you may observe
differences in the strictness of this restriction, with HIP exhibiting a tighter
adherence to the specification and thus less tolerant of infringing code. The
solution is to ensure that all functions which are called in a
`__device__` context are correctly annotated to reflect it. An interesting case
where these differences emerge is shown below. This relies on a the common
[C++ Member Detector idiom][1], as it would be implemented pre C++11):
```c++
#include <cassert>
#include <type_traits>
struct aye { bool a[1]; };
struct nay { bool a[2]; };
// Dual restriction is necessary in HIP if the detector is to work for
// __device__ contexts as well as __host__ ones. NVCC is less strict.
template<typename T>
__host__ __device__
const T& cref_t();
template<typename T>
struct Has_call_operator {
// Dual restriction is necessary in HIP if the detector is to work for
// __device__ contexts as well as __host__ ones. NVCC is less strict.
template<typename C>
__host__ __device__
static
aye test(
C const *,
typename std::enable_if<
(sizeof(cref_t<C>().operator()()) > 0)>::type* = nullptr);
static
nay test(...);
enum { value = sizeof(test(static_cast<T*>(0))) == sizeof(aye) };
};
template<typename T, typename U, bool callable = has_call_operator<U>::value>
struct Wrapper {
template<typename V>
V f() const { return T{1}; }
};
template<typename T, typename U>
struct Wrapper<T, U, true> {
template<typename V>
V f() const { return T{10}; }
};
// This specialisation will yield a compile-time error, if selected.
template<typename T, typename U>
struct Wrapper<T, U, false> {};
template<typename T>
struct Functor;
template<> struct Functor<float> {
__device__
float operator()() const { return 42.0f; }
};
__device__
void this_will_not_compile_if_detector_is_not_marked_device()
{
float f = Wrapper<float, Functor<float>>().f<float>();
}
__host__
void this_will_not_compile_if_detector_is_marked_device_only()
{
float f = Wrapper<float, Functor<float>>().f<float>();
}
```
[1]: https://en.wikibooks.org/wiki/More_C%2B%2B_Idioms/Member_Detector
docs/markdown/hip_faq.md
+39 -32
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@@ -4,13 +4,13 @@
- [What APIs and features does HIP support?](#what-apis-and-features-does-hip-support)
- [What is not supported?](#what-is-not-supported)
* [Run-time features](#run-time-features)
* [Runtime/Driver API features](#runtimedriver-api-features)
* [Kernel language features](#kernel-language-features)
- [Is HIP a drop-in replacement for CUDA?](#is-hip-a-drop-in-replacement-for-cuda)
- [What specific version of CUDA does HIP support?](#what-specific-version-of-cuda-does-hip-support)
- [What libraries does HIP support?](#what-libraries-does-hip-support)
- [How does HIP compare with OpenCL?](#how-does-hip-compare-with-opencl)
- [How does porting CUDA to HIP compare to porting CUDA to OpenCL?]
- [How does porting CUDA to HIP compare to porting CUDA to OpenCL?](#how-does-porting-cuda-to-hip-compare-to-porting-cuda-to-opencl)
- [What hardware does HIP support?](#what-hardware-does-hip-support)
- [Does Hipify automatically convert all source code?](#does-hipify-automatically-convert-all-source-code)
- [What is NVCC?](#what-is-nvcc)
@@ -23,9 +23,11 @@
- [On HCC, can I link HIP code with host code compiled with another compiler such as gcc, icc, or clang ?](#on-hcc-can-i-link-hip-code-with-host-code-compiled-with-another-compiler-such-as-gcc-icc-or-clang-)
- [HIP detected my platform (hcc vs nvcc) incorrectly - what should I do?](#hip-detected-my-platform-hcc-vs-nvcc-incorrectly---what-should-i-do)
- [Can I install both CUDA SDK and HCC on same machine?](#can-i-install-both-cuda-sdk-and-hcc-on-same-machine)
- [On CUDA, can I mix CUDA code with HIP code?](#on-cuda-can-i-mix-cuda-code-with-hip-code)
- [On HCC, can I use HC functionality with HIP?](#on-hcc-can-i-use-hc-functionality-with-hip)
- [How do I trace HIP application flow?](#how-do-i-trace-hip-application-flow)
* [Using CodeXL markers for HIP Functions](#using-codexl-markers-for-hip-functions)
* [Using HIP_TRACE_API](#using-hip_trace_api)
- [What if HIP generates error of "symbol multiply defined!" only on AMD machine?](#what-if-hip-generates-error-of-symbol-multiply-defined-only-on-amd-machine)
- [How do I disable HIP Generic Grid Launch option?](#how-do-i-disable-hip-generic-grid-launch-option)
<!-- tocstop -->
@@ -50,10 +52,9 @@ At a high-level, the following features are not supported:
- Textures
- Dynamic parallelism (CUDA 5.0)
- Managed memory (CUDA 6.5)
- Graphics interoperation with OpenGL or Direct3D
- Graphics interoperability with OpenGL or Direct3D
- CUDA Driver API (Under Development)
- CUDA IPC Functions (Under Development)
- CUDA array, mipmappedArray and pitched memory
- MemcpyToSymbol functions
- Queue priority controls
@@ -76,13 +77,13 @@ See the [API Support Table](CUDA_Runtime_API_functions_supported_by_HIP.md) for
### Is HIP a drop-in replacement for CUDA?
No. HIP provides porting tools which do most of the work do convert CUDA code into portable C++ code that uses the HIP APIs.
No. HIP provides porting tools which do most of the work to convert CUDA code into portable C++ code that uses the HIP APIs.
Most developers will port their code from CUDA to HIP and then maintain the HIP version.
HIP code provides the same performance as native CUDA code, plus the benefits of running on AMD platforms.
### What specific version of CUDA does HIP support?
HIP APIs and features do not map to a specific CUDA version. HIP provides a strong subset of functionality provided in CUDA, and the hipify tools can
scan code to identify any unsupported CUDA functions - this is very useful for identifying the specific features required by a given application.
HIP APIs and features do not map to a specific CUDA version. HIP provides a strong subset of functionality provided in CUDA, and the hipify tools can
scan code to identify any unsupported CUDA functions - this is useful for identifying the specific features required by a given application.
However, we can provide a rough summary of the features included in each CUDA SDK and the support level in HIP:
@@ -106,8 +107,8 @@ However, we can provide a rough summary of the features included in each CUDA SD
- TBD.
### What libraries does HIP support?
HIP includes growing support for the 4 key math libraries using hcBlas, hcFft, hcrng, and hcsparse).
These offer pointer-based memory interfaces (as opposed to opaque buffers) and can be easily interfaces with other HCC code. Developers should use conditional compliation if portability to nvcc systems is desired - using calls to cu* routines on one path and hc* routines on the other.
HIP includes growing support for the 4 key math libraries using hcBlas, hcFft, hcrng and hcsparse.
These offer pointer-based memory interfaces (as opposed to opaque buffers) and can be easily interfaced with other HCC applications. Developers should use conditional compilation if portability to nvcc systems is desired - using calls to cu* routines on one path and hc* routines on the other.
- [hcblas](https://bitbucket.org/multicoreware/hcblas)
- [hcfft](https://bitbucket.org/multicoreware/hcfft)
@@ -131,47 +132,47 @@ HIP offers several benefits over OpenCL:
### How does porting CUDA to HIP compare to porting CUDA to OpenCL?
Both HIP and CUDA are dialects of C++, and thus porting between them is relatively straightforward.
Both dialects support templates, classes, lambdas, and other C++ constructs.
As one example, the hipify tool was originally a perl script that used simple text conversions from CUDA to HIP.
HIP and CUDA provide similar math library calls as well. In summary, the HIP philospohy was to make the HIP language close enough to CUDA that the porting effort is relatively simple.
As one example, the hipify tool was originally a Perl script that used simple text conversions from CUDA to HIP.
HIP and CUDA provide similar math library calls as well. In summary, the HIP philosophy was to make the HIP language close enough to CUDA that the porting effort is relatively simple.
This reduces the potential for error, and also makes it easy to automate the translation. HIP's goal is to quickly get the ported program running on both platforms with little manual intervention,
so that the programmer can focus on performance optimizations.
There have been several tools that have attempted to convert CUDA into OpenCL, such as CU2CL. OpenCL is a C99-based kernel language (rather than C++) and also does not support single-source compilation.
As a result, the OpenCL syntax is quite different than CUDA, and the porting tools have to perform some heroic transformations to bridge this gap.
As a result, the OpenCL syntax is different from CUDA, and the porting tools have to perform some heroic transformations to bridge this gap.
The tools also struggle with more complex CUDA applications, in particular those that use templates, classes, or other C++ features inside the kernel.
### What hardware does HIP support?
- For AMD platforms, HIP runs on the same hardware that the HCC "hc" mode supports. See the ROCM documentation for the list of supported platforms.
- For Nvidia platforms, HIP requires Unified Memory and should run on a device which runs the CUDA SDK 6.0 or newer. We have tested the Nvidia Titan and K40.
- For AMD platforms, HIP runs on the same hardware that the HCC "hc" mode supports. See the ROCm documentation for the list of supported platforms.
- For Nvidia platforms, HIP requires Unified Memory and should run on any device supporting CUDA SDK 6.0 or newer. We have tested the Nvidia Titan and Tesla K40.
### Does Hipify automatically convert all source code?
Typically, Hipify can automatically convert almost all run-time code, and the coordinate indexing device code (i.e. threadIdx.x -> hipThreadIdx_x).
Typically, hipify can automatically convert almost all run-time code, and the coordinate indexing device code ( threadIdx.x -> hipThreadIdx_x ).
Most device code needs no additional conversion, since HIP and CUDA have similar names for math and built-in functions.
The hipify-clang tool will automatically modify the kernel signature as needed (automating a step that used to be done manually)
Additional porting may be required to deal with architecture feature queries or with CUDA capabilities that HIP doesn't support.
In general, developers should always expect to perform some platform-specific tuning and optimization.
### What is NVCC?
NVCC is Nvidia's compiler driver for compiling "CUDA C++" code into PTX or device code for Nvidia GPUs. It's a closed-source binary product that comes with CUDA SDKs.
NVCC is Nvidia's compiler driver for compiling "CUDA C++" code into PTX or device code for Nvidia GPUs. It's a closed-source binary compiler that is provided by the CUDA SDK.
### What is HCC?
HCC is AMD's compiler driver which compiles "heterogenous C++" code into HSAIL or GCN device code for AMD GPUs. It's an open-source compiler based on recent versions of CLANG/LLVM.
HCC is AMD's compiler driver which compiles "heterogeneous C++" code into HSAIL or GCN device code for AMD GPUs. It's an open-source compiler based on recent versions of CLANG/LLVM.
### Why use HIP rather than supporting CUDA directly?
While HIP is a strong subset of the CUDA, it is a subset. The HIP layer allows that subset to be clearly defined and documented.
Developers who code to the HIP API can be assured there code will remain portable across Nvidia and AMD platforms.
Developers who code to the HIP API can be assured their code will remain portable across Nvidia and AMD platforms.
In addition, HIP defines portable mechanisms to query architectural features, and supports a larger 64-bit wavesize which expands the return type for cross-lane functions like ballot and shuffle from 32-bit ints to 64-bit ints.
### Can I develop HIP code on an Nvidia CUDA platform?
Yes! HIP's CUDA path only exposes the APIs and functionality that work on both NVCC and HCC back-ends.
"Extra" APIs, parameters, and features which exist in CUDA but not in HCC will typically result in compile-time or run-time errors.
Developers need to use the HIP API for most accelerator code, and bracket any CUDA-specific code with appropriate ifdefs.
Yes. HIP's CUDA path only exposes the APIs and functionality that work on both NVCC and HCC back-ends.
"Extra" APIs, parameters, and features which exist in CUDA but not in HCC will typically result in compile- or run-time errors.
Developers need to use the HIP API for most accelerator code, and bracket any CUDA-specific code with preprocessor conditionals.
Developers concerned about portability should of course run on both platforms, and should expect to tune for performance.
In some cases CUDA has a richer set of modes for some APIs, and some C++ capabilities such as virtual functions - see the HIP @API documentation for more details.
### Can I develop HIP code on an AMD HCC platform?
Yes! HIP's HCC path only exposes the APIs and functions that work on both NVCC and HCC back ends. "Extra" APIs, parameters and features that appear in HCC but not CUDA will typically cause compile- or run-time errors. Developers must use the HIP API for most accelerator code and bracket any HCC-specific code with appropriate ifdefs. Those concerned about portability should, of course, test their code on both platforms and should tune it for performance. Typically, HCC supports a more modern set of C++11/C++14/C++17 features, so HIP developers who want portability should be careful when using advanced C++ features on the hc path.
Yes. HIP's HCC path only exposes the APIs and functions that work on both NVCC and HCC back ends. "Extra" APIs, parameters and features that appear in HCC but not CUDA will typically cause compile- or run-time errors. Developers must use the HIP API for most accelerator code and bracket any HCC-specific code with preprocessor conditionals. Those concerned about portability should, of course, test their code on both platforms and should tune it for performance. Typically, HCC supports a more modern set of C++11/C++14/C++17 features, so HIP developers who want portability should be careful when using advanced C++ features on the hc path.
### Can a HIP binary run on both AMD and Nvidia platforms?
HIP is a source-portable language that can be compiled to run on either the HCC or NVCC platform. HIP tools don't create a "fat binary" that can run on either platform, however.
@@ -184,9 +185,9 @@ A C++ dialect, hc is supported by the AMD HCC compiler. It provides C++ run time
### On HCC, can I link HIP code with host code compiled with another compiler such as gcc, icc, or clang ?
Yes! HIP/HCC generates the object code which conforms to the GCC ABI, and also links with libstdc++. This means you can compile host code with the compiler of your choice and link this
with GPU code compiler with HIP. Larger projects often contain a mixture of accelerator code (initially written in CUDA with nvcc) plus host code (compiled with gcc, icc, or clang). These projects
can convert the accelerator code to HIP, compile that code with hipcc, and link with object code from the preferred compiler.S
Yes. HIP/HCC generates the object code which conforms to the GCC ABI, and also links with libstdc++. This means you can compile host code with the compiler of your choice and link the generated object code
with GPU code compiled with HIP. Larger projects often contain a mixture of accelerator code (initially written in CUDA with nvcc) and host code (compiled with gcc, icc, or clang). These projects
can convert the accelerator code to HIP, compile that code with hipcc, and link with object code from their preferred compiler.
@@ -196,9 +197,9 @@ HIP will set the platform to HCC if it sees that the AMD graphics driver is inst
Sometimes this isn't what you want - you can force HIP to recognize the platform by setting HIP_PLATFORM to hcc (or nvcc)
```
export HIP_PLATFORM=hcc
```
One symptom of this problem is the message "error: 'unknown error'(11) at square.hipref.cpp:56". This can occur if you have a CUDA installation on an AMD platform, and HIP incorrectly detects the platform as nvcc. HIP may be able to compile the application using the nvcc tool-chain, but will generate this error at runtime since the platform does not have a CUDA device. The fix is to set HIP_PLATFORM=hcc and rebuild the issue.
One symptom of this problem is the message "error: 'unknown error'(11) at square.hipref.cpp:56". This can occur if you have a CUDA installation on an AMD platform, and HIP incorrectly detects the platform as nvcc. HIP may be able to compile the application using the nvcc tool-chain, but will generate this error at runtime since the platform does not have a CUDA device. The fix is to set HIP_PLATFORM=hcc and rebuild.
If you see issues related to incorrect platform detection, please file an issue with the GitHub issue tracker so we can improve HIP's platform detection logic.
@@ -207,7 +208,7 @@ Yes. You can use HIP_PLATFORM to choose which path hipcc targets. This configur
### On CUDA, can I mix CUDA code with HIP code?
Yes. Most HIP data structures (hipStream_t, hipEvent_t) are typedefs to CUDA equivalents and can be intermixed. Both CUDA and HIP use integer device ids .
Yes. Most HIP data structures (hipStream_t, hipEvent_t) are typedefs to CUDA equivalents and can be intermixed. Both CUDA and HIP use integer device ids.
One notable exception is that hipError_t is a new type, and cannot be used where a cudaError_t is expected. In these cases, refactor the code to remove the expectation. Alternatively, hip_runtime_api.h defines functions which convert between the error code spaces:
hipErrorToCudaError
@@ -218,10 +219,10 @@ If platform portability is important, use #ifdef __HIP_PLATFORM_NVCC__ to guard
### On HCC, can I use HC functionality with HIP?
Yes.
The code can include hc.hpp and use HC functions inside the kernel. A typical use case is to use AMD-specific hardware features such as the permute, swizzle, or DPP operations.
The code can include hc.hpp and use HC functions inside the kernel. A typical use-case is to use AMD-specific hardware features such as the permute, swizzle, or DPP operations.
The "-stdlib=libc++" must be passed to hipcc in order to compile hc.hpp. See the 'bit_extract' sample for an example.
Also these functions can be used to extract HCC acclerator and accelerator_view structures from the HIP deviceId and hipStream_t:
Also these functions can be used to extract HCC accelerator and accelerator_view structures from the HIP deviceId and hipStream_t:
hipHccGetAccelerator(int deviceId, hc::accelerator *acc);
hipError_t hipHccGetAcceleratorView(hipStream_t stream, hc::accelerator_view **av);
@@ -236,3 +237,9 @@ Unlike CUDA, in HCC, for functions defined in the header files, the keyword of "
Thus, if failed to define "static" keyword, you might see a lot of "symbol multiply defined!" errors at compilation.
The workaround is to explicitly add the keyword of "static" before any functions that were defined as "__forceinline__".
### How do I disable HIP Generic Grid Launch option?
Generic Grid Launch(GGL) is currently the default method for hip kernel launch.
To disable it and use the legancy grid launch method, please either change the default value of GENERIC_GRID_LAUNCH to 0 in the following to header files and rebuild HIP:
$HIP/include/hip/hcc_detail/hip_runtime_api.h
$HIP/include/hip/hcc_detail/host_defines.h
Or pass "-DGENERIC_GRID_LAUNCH=0" to hipcc at application compilation time.
docs/markdown/hip_kernel_language.md
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@@ -44,6 +44,7 @@
- [Pragma Unroll](#pragma-unroll)
- [In-Line Assembly](#in-line-assembly)
- [C++ Support](#c-support)
- [Kernel Compilation](#kernel-compilation)
<!-- tocstop -->
@@ -105,7 +106,7 @@ HIP parses the `__noinline__` and `__forceinline__` keywords and converts them t
```
// Example psuedocode introducing hipLaunchKernel:
// Example pseudo code introducing hipLaunchKernel:
__global__ MyKernel(hipLaunchParm lp, float *A, float *B, float *C, size_t N)
{
...
@@ -680,7 +681,7 @@ The user can specify the target for which the binary can be generated. HIP/HCC d
The file format for binary is `.co` which means Code Object. The following command builds the code object using `hipcc`.
`hipcc --genco --target-isa=[TARGET GPU] [INPUT FILE] -o [OUTPUT FILE]`
```[TARGET GPU] = fiji/hawaii
```[TARGET GPU] = gfx803/gfx701
[INPUT FILE] = Name of the file containing kernels
[OUTPUT FILE] = Name of the generated code object file```
docs/markdown/hip_performance.md
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@@ -6,18 +6,18 @@ Please note that this document lists possible ways for experimenting with HIP st
#### On Small BAR Setup
There are two possible ways to transfer data from Host to Device (H2D) and Device to Host(D2H)
There are two possible ways to transfer data from host-to-device (H2D) and device-to-host(D2H)
* Using Staging Buffers
* Using PinInPlace
#### On Large BAR Setup
There are three possible ways to transfer data from Host to Device (H2D)
There are three possible ways to transfer data from host-to-device (H2D)
* Using Staging Buffers
* Using PinInPlace
* Direct Memcpy
And there are two possible ways to transfer data from Device to Host (D2H)
And there are two possible ways to transfer data from device-to-host (D2H)
* Using Staging Buffers
* Using PinInPlace
docs/markdown/hip_porting_driver_api.md
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@@ -1,151 +1,119 @@
# Porting CUDA Driver API
## Introduction to the CUDA Driver and Runtime APIs
CUDA provides a separate CUDA Driver and Runtime APIs. The two APis have significant overlap in functionality:
CUDA provides a separate CUDA Driver and Runtime APIs. The two APIs have significant overlap in functionality:
- Both APIs support events, streams, memory management, memory copy, and error handling.
- Both APIs deliver similar performance.
- Driver APIs calls begin with the prefix `cu` while Runtime APIs begin with the prefix `cuda`. For example, the Driver API API contains `cuEventCreate` while the Runtime API contains `cudaEventCreate`, with similar functionality.
- The Driver API defines a different but largely overlapping error code code space than the Runtime API, and uses a different coding convention. For example, Driver API defines `CUDA_ERROR_INVALID_VALUE` while the Runtime API defines `cudaErrorInvalidValue`
- Both APIs deliver similar performance.
- Driver APIs calls begin with the prefix `cu` while Runtime APIs begin with the prefix `cuda`. For example, the Driver API API contains `cuEventCreate` while the Runtime API contains `cudaEventCreate`, with similar functionality.
- The Driver API defines a different but largely overlapping error code space than the Runtime API, and uses a different coding convention. For example, Driver API defines `CUDA_ERROR_INVALID_VALUE` while the Runtime API defines `cudaErrorInvalidValue`
The Driver API offers two additional pieces of functionality not provided by the Runtime API: cuModule and cuCtx APIs.
### cuModule API
The Module section of the Driver API provides additional control over how and when accelerator
code objects are loaded.
The Module section of the Driver API provides additional control over how and when accelerator code objects are loaded.
For example, the driver API allows code objects to be loaded from files or memory pointers.
Symbols for kernels or global data can be extracted from the loaded code objects.
In contrast, the Runtime API automatically loads and (if necessary) compiles all of the
kernels from a executable binary when run.
In contrast, the Runtime API automatically loads and (if necessary) compiles all of the kernels from an executable binary when run.
In this mode, NVCC must be used to compile kernel code so the automatic loading can function correctly.
Both Driver and Runtime APIs define a function for launching kernels (called `cuLaunchKernel` or `cudaLaunchKernel`.
The kernel arguments and the execution configuration (grid dimensions, group dimensions, dynamic shared memory, and stream) are passed as arguments to the launch function.
The Runtime additionally provides the `<<< >>>` syntax for launching kernels, which resembles
a special function call and is easier to use than explicit launch API (in particular with respect to
handling of kernel arguments).
However, this syntax is not standard C++ and is available only when NVCC is used to compile the host code.
The Runtime additionally provides the `<<< >>>` syntax for launching kernels, which resembles a special function call and is easier to use than explicit launch API (in particular with respect to handling of kernel arguments).
However, this syntax is not standard C++ and is available only when NVCC is used to compile the host code.
The Module features are useful in an environment which generate the code objects directly, such as a new
accelerator language front-end. Here, NVCC is not used. Instead, the environment may have a
different kernel language or different compilation flow.
The Module features are useful in an environment which generates the code objects directly, such as a new accelerator language front-end.
Here, NVCC is not used. Instead, the environment may have a different kernel language or different compilation flow.
Other environments have many kernels and do not want them to be all loaded automatically.
The Module functions can be used to load the generated code objects and launch kernels.
As we will see below, HIP defines a Module API which provides similar explict control over code
object managemenet.
As we will see below, HIP defines a Module API which provides similar explicit control over code object management.
### cuCtx API
The Driver API defines "Context" and "Devices" as separate entities.
Contexts contain a single device, and a device can theoretically have multiple contexts.
Each context contains a set of streams and events specific to the context.
Historically contexts also defined a unique address space for the GPU, though this may not longer be the case in Unified Memory platforms (since the CPU and all the devices in the same process share a single unified address space).
The Context APIs also provide a mechanism to switch between devices, which allowed
a single CPU thread to send commands to different GPUs. HIP as well as a recent versions
of CUDA Runtime provide other mechanisms to accomplish this feat - for example using streams or
`cudaSetDevice`.
The Driver API defines "Context" and "Devices" as separate entities.
Contexts contain a single device, and a device can theoretically have multiple contexts.
Each context contains a set of streams and events specific to the context.
Historically contexts also defined a unique address space for the GPU, though this may no longer be the case in Unified Memory platforms (since the CPU and all the devices in the same process share a single unified address space).
The Context APIs also provide a mechanism to switch between devices, which allowed a single CPU thread to send commands to different GPUs.
HIP as well as a recent versions of CUDA Runtime provide other mechanisms to accomplish this feat - for example using streams or `cudaSetDevice`.
The CUDA Runtime API unifies the Context API with the Device API. This simplifies the APIs
and has little loss of functionality since each Context can contain a single device,
and the benefits of multiple contexts has been replaced with other interfaces. HIP provides
a context API to facilitate easy porting from existing Driver codes.
In HIP, the Ctx functions largely provide an alternate syntax for changing the active device.
The CUDA Runtime API unifies the Context API with the Device API. This simplifies the APIs and has little loss of functionality since each Context can contain a single device, and the benefits of multiple contexts has been replaced with other interfaces.
HIP provides a context API to facilitate easy porting from existing Driver codes.
In HIP, the Ctx functions largely provide an alternate syntax for changing the active device.
Most new applications will prefer to use `hipSetDevice` or the stream APIs.
## HIP Module and Ctx APIs
Rather than present two separate APIs, HIP extends the HIP API with new APIs for Modules
and Ctx control.
Rather than present two separate APIs, HIP extends the HIP API with new APIs for Modules and Ctx control.
### hipModule API
Like the CUDA Driver API, the Module API provides additional control
over how code is loaded, including options to load code from files or from in-memory pointers.
NVCC and HCC target different architectures and use different code object formats : NVCC
is `cubin` or `ptx` files, while the HCC path is the `hsaco` format. The external
compilers which generate these code objects are responsible for generating and loading
the correct code object for each platform. Notably, there is not a fat binary format that
can contain code for both NVCC and HCC platforms. The following table summarizes the
formats used on each platform:
Like the CUDA Driver API, the Module API provides additional control over how code is loaded, including options to load code from files or from in-memory pointers.
NVCC and HCC target different architectures and use different code object formats: NVCC is `cubin` or `ptx` files, while the HCC path is the `hsaco` format.
The external compilers which generate these code objects are responsible for generating and loading the correct code object for each platform.
Notably, there is not a fat binary format that can contain code for both NVCC and HCC platforms. The following table summarizes the formats used on each platform:
| Format | APIs | NVCC | HCC |
| --- | --- | --- | --- |
| Format | APIs | NVCC | HCC |
| --- | --- | --- | --- |
| Code Object | hipModuleLoad, hipModuleLoadData | .cubin or PTX text | .hsaco |
| Fat Binary | hipModuleLoadFatBin | .fatbin | Under Development |
| Fat Binary | hipModuleLoadFatBin | .fatbin | Under Development |
hipcc uses NVCC and HCC to compile host codes. Both of these may embed code objects
into the final executable, and these code objects will be automatically loaded when
the application starts.
The hipModule API can be used to load additional code objects, and in this way
provides an extended capability to the automatically loaded code objects. HCC allows
both of these capabilities to be used together, if desired. Of course it is possible
to create a program with no kernels and thus no automatic loading.
`hipcc` uses NVCC and HCC to compile host codes. Both of these may embed code objects into the final executable, and these code objects will be automatically loaded when the application starts.
The hipModule API can be used to load additional code objects, and in this way provides an extended capability to the automatically loaded code objects.
HCC allows both of these capabilities to be used together, if desired. Of course it is possible to create a program with no kernels and thus no automatic loading.
### hipCtx API
HIP provides a `Ctx` API as a thin layer over the existing Device functions. This Ctx API
can be used to set the current context, or to query properties of the device associated with
the context. The current context is implicitly used by other APIs such as `hipStreamCreate`.
HIP provides a `Ctx` API as a thin layer over the existing Device functions. This Ctx API can be used to set the current context, or to query properties of the device associated with the context.
The current context is implicitly used by other APIs such as `hipStreamCreate`.
### hipify translation of CUDA Driver API
The hipify tool will convert CUDA Driver APIs for streams, events, memory management to
the equivalent HIP driver calls. For example, `cuEventCreate` will be translated to
`hipEventCreate`. Hipify also converts error code from the Driver namespace and coding
convention to the equivalent HIP error code. Thus, HIP unifies the APis for these common functions.
[hipify support for translating driver API is Under Development]
The hipify tool converts CUDA Driver APIs for streams, events, modules, devices, memory management, context, profiler to the equivalent HIP driver calls. For example, `cuEventCreate` will be translated to `hipEventCreate`.
Hipify also converts error code from the Driver namespace and coding convention to the equivalent HIP error code. Thus, HIP unifies the APIs for these common functions.
The memory copy APIs require additional explanation. The CUDA driver includes the memory
direction in the name of the API (ie `cuMemcpyH2D`) while the CUDA driver API provides
a single memory copy API with a parameter that specifies the direction and additionally
supports a "default" direction where the runtime determines the direction automatically.
HIP provides APis with both styles: for example, `hipMemcpyH2D` as well as `hipMemcpy`.
The first flavor may be faster in some cases since they avoid host overhead to detect the
different memory directions.
The memory copy API requires additional explanation. The CUDA driver includes the memory direction in the name of the API (ie `cuMemcpyH2D`) while the CUDA driver API provides a single memory copy API with a parameter that specifies the direction and additionally supports a "default" direction where the runtime determines the direction automatically.
HIP provides APIs with both styles: for example, `hipMemcpyH2D` as well as `hipMemcpy`.
The first flavor may be faster in some cases since they avoid host overhead to detect the different memory directions.
HIP defines a single error space, and uses camel-case for all errors (i.e. `hipErrorInvalidValue`).
HIP defines a single error space, and uses camel-case for all errors (i.e. `hipErrorInvalidValue`).
### HCC Implementation Notes
#### .hsaco
The .hsaco format used by HCC is described in more detail [here](https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc).
An example and blog that show how to use the format is [here](http://gpuopen.com/rocm-with-harmony-combining-opencl-hcc-hsa-in-a-single-program). hsaco can be generated by hcc + extractkernel tool,
cloc, the GCN assembler, or other tools.
An example and blog that show how to use the format is [here](http://gpuopen.com/rocm-with-harmony-combining-opencl-hcc-hsa-in-a-single-program). hsaco can be generated by hcc + extractkernel tool, cloc, the GCN assembler, or other tools.
#### Address Spaces
HCC defines a process-wide address space where the CPU and all devices allocate
addresses from a single unified pool. Thus addresses may be shared between contexts, and
unlike the original CUDA definition a new context does not create a new address space for
the device.
HCC defines a process-wide address space where the CPU and all devices allocate addresses from a single unified pool.
Thus addresses may be shared between contexts, and unlike the original CUDA definition a new context does not create a new address space for the device.
#### Using hipModuleLaunchKernel
`hipModuleLaunchKernel` is `cuLaunchKernel` in HIP world. It takes the same arguments as `cuLaunchKernel`. The argument `kernelParams` is not fully implemented for HCC. The workaround for it is, to use platform specific macros for each target. Or, `extra` argument can be used which works on both the platforms.
#### Additional Information
- HCC allocates staging buffers (used for unpinned copies) on a per-device basis.
- HCC creates a primary context when the HIP API is called. So in a pure driver API code, HIP/HCC will create a primary context while HIP/NVCC will have empty context stack. HIP/HCC will push primary context to context stack when it is empty. This can have subtle differences on applications which mix the runtime and driver APIs.
- HCC creates a primary context when the HIP API is called. So in a pure driver API code, HIP/HCC will create a primary context while HIP/NVCC will have empty context stack.
HIP/HCC will push primary context to context stack when it is empty. This can have subtle differences on applications which mix the runtime and driver APIs.
### NVCC Implementation Notes
#### Interoperation between HIP and CUDA Driver
CUDA applications may want to mix CUDA driver code with HIP code (see example below). This
table shows the type equivalence to enable this interaction.
|**HIP Type** |**CU Driver Type**| **CUDA Runtime Type** |
| ---- | ---- | ---- |
| hipModule | CUmodule | |
| hipFunction | CUfunction | |
| hipCtx_t | CUcontext | |
| hipDevice_t | CUdevice | |
| hipStream_t | CUstream | cudaStream_t |
| hipEvent_t | CUevent | cudaEvent_t |
| hipArray | CUarray | cudaArray |
CUDA applications may want to mix CUDA driver code with HIP code (see example below). This table shows the type equivalence to enable this interaction.
|**HIP Type** |**CU Driver Type**|**CUDA Runtime Type**|
| ---- | ---- | ---- |
| hipModule | CUmodule | |
| hipFunction | CUfunction | |
| hipCtx_t | CUcontext | |
| hipDevice_t | CUdevice | |
| hipStream_t | CUstream | cudaStream_t |
| hipEvent_t | CUevent | cudaEvent_t |
| hipArray | CUarray | cudaArray |
#### Compilation Flags
The hipModule interface does not support the hipModuleLoadEx function, which is used to control PTX compilaton options.
The hipModule interface does not support the `cuModuleLoadDataEx` function, which is used to control PTX compilation options.
HCC does not use PTX and does not support the same compilation options.
In fact, HCC code objects always contain fully compiled ISA and do not require additional compilation as part of the load step.
Code which requires this functionaly should use platform-specific coding, calling `cuModuleLoadEx`
on the NVCC path and hipModuleLoad on the hcc path. For example:
Code which requires this functionally should use platform-specific coding, calling `cuModuleLoadDataEx` on the NVCC path and `hipModuleLoadData` on the hcc path.
For example:
```
hipModule module;
@@ -240,7 +208,7 @@ int main(){
HIP_LAUNCH_PARAM_END
};
hipModuleLaunchKernel(Function, 1, 1, 1, LEN, 1, 1, 0, 0, NULL, (void**)&con fig);
hipModuleLaunchKernel(Function, 1, 1, 1, LEN, 1, 1, 0, 0, NULL, (void**)&config);
hipMemcpyDtoH(B, Bd, SIZE);
for(uint32_t i=0;i<LEN;i++){
@@ -253,5 +221,4 @@ int main(){
return 0;
}
```
docs/markdown/hip_porting_guide.md
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@@ -1,5 +1,5 @@
# HIP Porting Guide
In addition to providing a portable C++ programmming environement for GPUs, HIP is designed to ease
In addition to providing a portable C++ programming environment for GPUs, HIP is designed to ease
the porting of existing CUDA code into the HIP environment. This section describes the available tools
and provides practical suggestions on how to port CUDA code and work through common issues.
@@ -21,6 +21,7 @@ and provides practical suggestions on how to port CUDA code and work through com
* [Device-Architecture Properties](#device-architecture-properties)
* [Table of Architecture Properties](#table-of-architecture-properties)
- [Finding HIP](#finding-hip)
- [hipLaunchKernel](#hiplaunchkernel)
- [Compiler Options](#compiler-options)
- [Linking Issues](#linking-issues)
* [Linking With hipcc](#linking-with-hipcc)
@@ -31,9 +32,11 @@ and provides practical suggestions on how to port CUDA code and work through com
* [Using a Standard C++ Compiler](#using-a-standard-c-compiler)
+ [cuda.h](#cudah)
* [Choosing HIP File Extensions](#choosing-hip-file-extensions)
* [Workarounds](#workarounds)
+ [warpSize](#warpsize)
+ [Textures and Cache Control](#textures-and-cache-control)
- [Workarounds](#workarounds)
* [warpSize](#warpsize)
- [memcpyToSymbol](#memcpytosymbol)
- [threadfence_system](#threadfence_system)
* [Textures and Cache Control](#textures-and-cache-control)
- [More Tips](#more-tips)
* [HIPTRACE Mode](#hiptrace-mode)
* [Environment Variables](#environment-variables)
@@ -166,10 +169,10 @@ Both nvcc and hcc make two passes over the code: one for host code and one for d
```
// #ifdef __CUDA_ARCH__
#ifdef __HIP_DEVICE_COMPILE__
#if __HIP_DEVICE_COMPILE__
```
Unlike `__CUDA_ARCH__`, the `__HIP_DEVICE_COMPILE__` value is 0 or 1, and it doesn’t represent the feature capability of the target device.
Unlike `__CUDA_ARCH__`, the `__HIP_DEVICE_COMPILE__` value is 1 or undefined, and it doesn’t represent the feature capability of the target device.
### Compiler Defines: Summary
@@ -178,11 +181,11 @@ Unlike `__CUDA_ARCH__`, the `__HIP_DEVICE_COMPILE__` value is 0 or 1, and it doe
|HIP-related defines:|
|`__HIP_PLATFORM_HCC___`| Defined | Undefined | Defined if targeting hcc platform; undefined otherwise |
|`__HIP_PLATFORM_NVCC___`| Undefined | Defined | Defined if targeting nvcc platform; undefined otherwise |
|`__HIP_DEVICE_COMPILE__` | 1 if compiling for device; 0 if compiling for host |1 if compiling for device; 0 if compiling for host | Undefined
|`__HIP_DEVICE_COMPILE__` | 1 if compiling for device; undefined if compiling for host |1 if compiling for device; undefined if compiling for host | Undefined
|`__HIPCC__` | Defined | Defined | Undefined
|`__HIP_ARCH_*` | 0 or 1 depending on feature support (see below) | 0 or 1 depending on feature support (see below) | 0
|nvcc-related defines:|
|`__CUDACC__` | Undefined | Defined if compiling for Cuda device; undefined otherwise | Undefined
|`__CUDACC__` | Undefined | Defined if source code is compiled by nvcc; undefined otherwise | Undefined
|`__NVCC__` | Undefined | Defined | Undefined
|`__CUDA_ARCH__` | Undefined | Unsigned representing compute capability (e.g., "130") if in device code; 0 if in host code | Undefined
|hcc-related defines:|
@@ -553,7 +556,7 @@ If you pass a ".cu" file, hcc will attempt to compile it as a Cuda language file
### HIP Environment Variables
On the HCC path, HIP provides a number of environment variables that control the behavior of HIP. Some of these are useful for appliction development (for example HIP_VISIBLE_DEVICES, HIP_LAUNCH_BLOCKING),
On the HCC path, HIP provides a number of environment variables that control the behavior of HIP. Some of these are useful for application development (for example HIP_VISIBLE_DEVICES, HIP_LAUNCH_BLOCKING),
some are useful for performance tuning or experimentation (for example HIP_STAGING*), and some are useful for debugging (HIP_DB). You can see the environment variables supported by HIP as well as
their current values and usage with the environment var "HIP_PRINT_ENV" - set this and then run any HIP application. For example:
docs/markdown/hip_profiling.md
+120 -27
Voir le fichier
@@ -4,26 +4,32 @@ This section describes the profiling and debugging capabilities that HIP provide
Profiling information can viewed in the CodeXL visualization tool or printed directly to stderr as the application runs.
This document starts with some of the general capabilities of CodeXL and then describes some of the additional HIP marker and debug features.
* [CodeXL Profiling](#codexl-profiling)
* [Collecting and Viewing Traces](#collecting-and-viewing-traces)
* [Using rocm-profiler timestamp profiling](#using-rocm-profiler-timestamp-profiling)
* [Using rocm-profiler performance counter collection:](#using-rocm-profiler-performance-counter-collection)
* [Using CodeXL to view profiling results:](#using-codexl-to-view-profiling-results)
* [More information on CodeXL](#more-information-on-codexl)
* [HIP Markers](#hip-markers)
* [Profiling HIP APIs](#profiling-hip-apis)
* [Adding markers to applications](#adding-markers-to-applications)
* [Additional HIP Profiling Features](#additional-hip-profiling-features)
* [Demangling C Kernel Names](#demangling-c-kernel-names)
* [Controlling when profiling starts and ends](#controlling-when-profiling-starts-and-ends)
* [Reducing timeline trace output file size](#reducing-timeline-trace-output-file-size)
* [How to enable profiling at HIP build time](#how-to-enable-profiling-at-hip-build-time)
* [Tracing and Debug](#tracing-and-debug)
* [Tracing HIP APIs](#tracing-hip-apis)
* [Color](#color)
* [Using HIP_DB](#using-hip_db)
* [Using ltrace](#using-ltrace)
* [Chicken bits](#chicken-bits)
<!-- toc -->
- [CodeXL Profiling](#codexl-profiling)
* [Collecting and Viewing Traces](#collecting-and-viewing-traces)
+ [Using rocm-profiler timestamp profiling](#using-rocm-profiler-timestamp-profiling)
+ [Using rocm-profiler performance counter collection:](#using-rocm-profiler-performance-counter-collection)
+ [Using CodeXL to view profiling results:](#using-codexl-to-view-profiling-results)
+ [More information on CodeXL](#more-information-on-codexl)
* [HIP Markers](#hip-markers)
+ [Profiling HIP APIs](#profiling-hip-apis)
+ [Adding markers to applications](#adding-markers-to-applications)
* [Additional HIP Profiling Features](#additional-hip-profiling-features)
+ [Demangling C++ Kernel Names](#demangling-c-kernel-names)
+ [Controlling when profiling starts and ends](#controlling-when-profiling-starts-and-ends)
+ [Reducing timeline trace output file size](#reducing-timeline-trace-output-file-size)
+ [How to enable profiling at HIP build time](#how-to-enable-profiling-at-hip-build-time)
- [Tracing and Debug](#tracing-and-debug)
* [Tracing HIP APIs](#tracing-hip-apis)
+ [Color](#color)
* [Using HIP_DB](#using-hip_db)
* [Using ltrace](#using-ltrace)
* [Chicken bits](#chicken-bits)
* [Debugging HIP Applications](#debugging-hip-applications)
* [General Debugging Tips](#general-debugging-tips)
<!-- tocstop -->
## CodeXL Profiling
@@ -92,11 +98,11 @@ HIP_PROFILE_API supports two levels of information.
#### Adding markers to applications
Markers can be used to define application-specific events that will be recorded in the ATP file and displayed in the CodeXL gui.
Markers can be used to define application-specific events that will be recorded in the ATP file and displayed in the CodeXL GUI.
This can be particularly useful for visualizing how the higher-level phases of application behavior relate to the lower level HIP APIs, kernel launches, and data transfers.
For example, an instrumented machine learning framework could show the beginning and ending of each layer in the network.
Markers have a specific begin and end time, and can be nested. Nested calls are displayed hierarchically in the CodeXL gui, with each level of the hierarchy occupying a different row.
Markers have a specific begin and end time, and can be nested. Nested calls are displayed hierarchically in the CodeXL GUI, with each level of the hierarchy occupying a different row.
The HIP APis are defined in "hip_profile.h":
```
@@ -131,7 +137,7 @@ The HIP marker API is only supported on ROCm platform. The marker macros are de
This [HIP sample](samples/2_Cookbook/2_Profiler/) shows the profiler marker API used in a small application.
More information on the marker API can be found in the profiler header file and PDF in a ROCM installation:
More information on the marker API can be found in the profiler header file and PDF in a ROCm installation:
- /opt/rocm/profiler/CXLActivityLogger/include/CXLActivityLogger.h
- /opt/rocm/profiler/CXLActivityLogger/doc/CXLActivityLogger.pdf
@@ -185,7 +191,7 @@ $ nvprof --profile-from-start-off ...
This feature is under development.
#### Reducing timeline trace output file size
If the application is already recording the HIP APIs, the HSA APIs are somewhat redundant and the ATP file size can be substantially reduced by not recording these APIs. HIP includes a text file that lists all of the HSA APis and can assist in this filtering:
If the application is already recording the HIP APIs, the HSA APIs are somewhat redundant and the ATP file size can be substantially reduced by not recording these APIs. HIP includes a text file that lists all of the HSA APIs and can assist in this filtering:
```
$ rocm-profiler -F hip/bin/hsa-api-filter-cxl.txt
@@ -273,7 +279,7 @@ None will disable use of color control codes for both the opening and closing an
This flag is primarily targeted to assist HIP development team in the development of the HIP runtime, but in some situations may be useful to HIP application developers as well.
The HIP debug information is designed to print important information during the execution of a HIP API. HIP provides
different color-coded levels of debug informaton:
different color-coded levels of debug information:
- api : Print the beginning and end of each HIP API, including the arguments and return codes. This is equivalent to setting HIP_TRACE_API=1.
- sync : Print multi-thread and other synchronization debug information.
- copy : Print which engine is doing the copy, which copy flavor is selected, information on source and destination memory.
@@ -315,7 +321,7 @@ libhsa-runtime64.so.1->hsaKmtDeregisterMemory(0x7f7776d3e010, 0x7f7776d3e010, 0x
```
Some key information from the trace above.
- The trace snippet shows the execution of a hipMemcpy API, bracketed by the first and last message in the trace output. The messages show the thread id and API sequence number (`1.17`). ltrace output intermixes messages from all threads, so the HIP debug information can be useful to determine which threads are executing.
- Thy trace snippet shows the execution of a hipMemcpy API, bracketed by the first and last message in the trace output. The messages show the thread id and API sequence number (`1.17`). ltrace output intermixes messages from all threads, so the HIP debug information can be useful to determine which threads are executing.
- The code flows through HIP APIs into ROCr (HSA) APIs (hsa*) and into the thunk (hsaKmt*) calls.
- The HCC runtime is "libmcwamp_hsa.so" and the HSA/ROCr runtime is "libhsa-runtime64.so".
- In this particular case, the memory copy is for unpinned memory, and the selected copy algorithm is to pin the host memory "in-place" before performing the copy. The signaling APIs and calls to pin ("lock", "register") the memory are readily apparent in the trace output.
@@ -335,8 +341,95 @@ HIP provides 3 environment variables in the HIP_*_BLOCKING family. These introd
These options cause HCC to serialize. Useful if you have libraries or code which is calling HCC kernels directly rather than using HIP.
- HCC_SERIALZIE_KERNELS : 0x1=pre-serialize before each kernel launch, 0x2=post-serialize after each kernel launch., 0x3= pre- and post- serialize.
- HCC_SERIALIZE_COPY : 0x1=pre-serialize before each async copy, 0x2=post-serialize after each async copy., 0x3= pre- and post- serialize.0
- HCC_SERIALIZE_COPY : 0x1=pre-serialize before each async copy, 0x2=post-serialize after each async copy., 0x3= pre- and post- serialize.
- HSA_ENABLE_SDMA=0 : Causes host-to-device and device-to-host copies to use compute shader blit kernels rather than the dedicated DMA copy engines. Compute shader copies have low latency (typically < 5us) and can achieve approximately 80% of the bandwidth of the DMA copy engine. This flag is useful to isolate issues with the hardware copy engines.
- HSA_ENABLE_INTERRUPT=0 : Causes completion signals to be detected with memory-based polling rather than interrupts. Can be useful to diagnose interrupt storm issues in the driver.
- HSA_DISABLE_CACHE=1 : Disables the GPU L2 data cache.
### Debugging HIP Applications
- The variable "tls_tidInfo" contains the API sequence number (_apiSeqNum)- a monotonically increasing count of the HIP APIs called from this thread. This can be useful for setting conditional breakpoints. Also, each new HIP thread is mapped to monotically increasing shortTid ID. Both of these fields are displayed in the HIP debug info.
```
(gdb) p tls_tidInfo
$32 = {_shortTid = 1, _apiSeqNum = 803}
```
- HCC tracks all of the application memory allocations, including those from HIP and HC's "am_alloc".
If the HCC runtime is built with debug information (HCC_RUNTIME_DEBUG=ON when building HCC), then calling the function 'hc::am_memtracker_print()' will show all memory allocations.
An optional argument specifies a void * targetPointer - the print routine will mark the allocation which contains the specified pointer with "-->" in the printed output.
This example shows a sample GDB session where we print the memory allocated by this process and mark a specified address by using the gdb "call" function..
The gdb syntax also supports using the variable name (in this case 'dst'):
```
(gdb) p dst
$33 = (void *) 0x5ec7e9000
(gdb) call hc::am_memtracker_print(dst)
TargetAddress:0x5ec7e9000
0x504cfc000-0x504cfc00f:: allocSeqNum:1 hostPointer:0x504cfc000 devicePointer:0x504cfc000 sizeBytes:16 isInDeviceMem:0 isAmManaged:1 appId:0 appAllocFlags:0 appPtr:(nil)
...
-->0x5ec7e9000-0x5f7e28fff:: allocSeqNum:488 hostPointer:(nil) devicePointer:0x5ec7e9000 sizeBytes:191102976 isInDeviceMem:1 isAmManaged:1 appId:0 appAllocFlags:0 appPtr:(nil)
```
To debug an explicit address, cast the address to (void*) :
```
(gdb) call hc::am_memtracker_print((void*)0x508c7f000)
```
- Debugging GPUVM fault.
For example:
```
Memory access fault by GPU node-1 on address 0x5924000. Reason: Page not present or supervisor privilege.
Program received signal SIGABRT, Aborted.
[Switching to Thread 0x7fffdffb5700 (LWP 14893)]
0x00007ffff2057c37 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
56 ../nptl/sysdeps/unix/sysv/linux/raise.c: No such file or directory.
(gdb) bt
#0 0x00007ffff2057c37 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
#1 0x00007ffff205b028 in __GI_abort () at abort.c:89
#2 0x00007ffff6f960eb in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
#3 0x00007ffff6f99ea5 in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
#4 0x00007ffff6f78107 in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
#5 0x00007ffff744f184 in start_thread (arg=0x7fffdffb5700) at pthread_create.c:312
#6 0x00007ffff211b37d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:111
(gdb) info threads
Id Target Id Frame
4 Thread 0x7fffdd521700 (LWP 14895) "caffe" pthread_cond_wait@@GLIBC_2.3.2 () at ../nptl/sysdeps/unix/sysv/linux/x86_64/pthread_cond_wait.S:185
3 Thread 0x7fffddd22700 (LWP 14894) "caffe" pthread_cond_wait@@GLIBC_2.3.2 () at ../nptl/sysdeps/unix/sysv/linux/x86_64/pthread_cond_wait.S:185
* 2 Thread 0x7fffdffb5700 (LWP 14893) "caffe" 0x00007ffff2057c37 in __GI_raise (sig=sig@entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56
1 Thread 0x7ffff7fa6ac0 (LWP 14892) "caffe" 0x00007ffff6f934d5 in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
(gdb) thread 1
[Switching to thread 1 (Thread 0x7ffff7fa6ac0 (LWP 14892))]
#0 0x00007ffff6f934d5 in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
(gdb) bt
#0 0x00007ffff6f934d5 in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
#1 0x00007ffff6f929ba in ?? () from /opt/rocm/hsa/lib/libhsa-runtime64.so.1
#2 0x00007fffe080beca in HSADispatch::waitComplete() () from /opt/rocm/hcc/lib/libmcwamp_hsa.so
#3 0x00007fffe080415f in HSADispatch::dispatchKernelAsync(Kalmar::HSAQueue*, void const*, int, bool) () from /opt/rocm/hcc/lib/libmcwamp_hsa.so
#4 0x00007fffe080238e in Kalmar::HSAQueue::dispatch_hsa_kernel(hsa_kernel_dispatch_packet_s const*, void const*, unsigned long, hc::completion_future*) () from /opt/rocm/hcc/lib/libmcwamp_hsa.so
#5 0x00007ffff7bb7559 in hipModuleLaunchKernel () from /opt/rocm/hip/lib/libhip_hcc.so
#6 0x00007ffff2e6cd2c in mlopen::HIPOCKernel::run (this=0x7fffffffb5a8, args=0x7fffffffb2a8, size=80) at /root/MIOpen/src/hipoc/hipoc_kernel.cpp:15
...
```
### General Debugging Tips
- The fault will be caught by the runtime but was actually generated by an asynchronous command running on the GPU. So, the GDB backtrace will show a path in the runtime, ie inside "GI_Raise" as shown in the example above.
- To determine the true location of the fault, force the kernels to execute synchronously by seeing the environment variables HCC_SERIALIZE_KERNEL=3 HCC_SERIALIZE_COPY=3. This will force HCC to wait for the kernel to finish executing before retuning. If the fault occurs during the execution of a kernel, you can see the code which launched the kernel inside the backtrace. A bit of guesswork is required to determine which thread is actually causing the issue - typically it will the thread which is waiting inside the libhsa-runtime64.so.
- VM faults inside kernels can be caused byi:
- incorrect code (ie a for loop which extends past array boundaries), i
- memory issues - kernel arguments which are invalid (null pointers, unregistered host pointers, bad pointers).
- synchronization issues
- compiler issues (incorrect code generation from the compiler)
- runtime issues
-- General debug tips:
- 'gdb --args' can be used to conviently pass the executable and arguments to gdb.
- From inside GDB, you can set environment variables "set env". Note the command does not use an '=' sign:
```
(gdb) set env HIP_DB 1
```
Setting HIP_PRINT_ENV=1 and then running a HIP application will print the HIP environment variables, their current values, and usage info.
Setting HCC_PRINT_ENV=1 and then running a HCC application will print the HCC environment variables, their current values, and usage info.
docs/markdown/hip_terms2.md
+1 -1
Voir le fichier
@@ -13,7 +13,7 @@ The default device can be set with hipSetDevice.
- hcc = Heterogeneous Compute Compiler (https://bitbucket.org/multicoreware/hcc/wiki/Home).
- hipify - tool to convert CUDA(R) code to portable C++ code.
- hipconfig - tool to report various confoguration properties of the target platform.
- hipconfig - tool to report various configuration properties of the target platform.
- nvcc = nvcc compiler, do not capitalize.
- hcc = heterogeneous compute compiler, do not capitalize.