From dce2a864ba8a8a15cc3779e56826fc69308f1b4b Mon Sep 17 00:00:00 2001 From: Jay Cornwall Date: Thu, 2 Feb 2017 18:15:11 -0600 Subject: [PATCH] Fix Gfx9 write pointer setup Should point directly to amd_queue_t.write_dispatch_id. Only noticeable with HWS enabled which is not yet stable. Change-Id: I169906d45225379a3ca2729ff04d298fdbb9a9fb [ROCm/ROCR-Runtime commit: 28f51d5808cf80ed672520fe9618cf91541ed01b] --- .../runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp index 6ca1ccfba0..27a05cdb54 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp @@ -147,8 +147,14 @@ AqlQueue::AqlQueue(GpuAgent* agent, size_t req_size_pkts, HSAuint32 node_id, // Initialize and map a HW AQL queue. HsaQueueResource queue_rsrc = {0}; queue_rsrc.Queue_read_ptr_aql = (uint64_t*)&amd_queue_.read_dispatch_id; - queue_rsrc.Queue_write_ptr_aql = - (uint64_t*)&amd_queue_.max_legacy_doorbell_dispatch_id_plus_1; + + if (doorbell_type_ == 2) { + // Hardware write pointer supports AQL semantics. + queue_rsrc.Queue_write_ptr_aql = (uint64_t*)&amd_queue_.write_dispatch_id; + } else { + // Map hardware write pointer to a software proxy. + queue_rsrc.Queue_write_ptr_aql = (uint64_t*)&amd_queue_.max_legacy_doorbell_dispatch_id_plus_1; + } HSAKMT_STATUS kmt_status; kmt_status = hsaKmtCreateQueue(node_id, HSA_QUEUE_COMPUTE_AQL, 100,