Enable fp8 support (#1101)
* initial checkin
* resolve cr comments
* resolve the build issue
* fix the data correctless issue
* update fp8 header file and update the unit test for fp8 support
* remove fp16 from fp8 headers
* fix ut issue and catch up the latest code from develop
* udate according to cr comments
* update ut according to cr comments
* update num floats for each SumPostDiv from 4 to 6
* update fp8 header file name
* fix the typo
[ROCm/rccl commit: 6777e65c1d]
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@@ -1,6 +1,7 @@
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/*************************************************************************
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* Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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* Modifications Copyright (c) 2019-2023 Advanced Micro Devices, Inc. All rights reserved.
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* Modifications Copyright (c) Microsoft Corporation. Licensed under the MIT License.
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*
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* See LICENSE.txt for license information
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************************************************************************/
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@@ -1556,9 +1557,13 @@ static ncclResult_t hostToDevRedOp(
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half f16;
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float f32;
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double f64;
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#if defined(RCCL_BFLOAT16)
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rccl_bfloat16 bf16;
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#endif
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#if defined(RCCL_BFLOAT16)
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rccl_bfloat16 bf16;
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#endif
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#if defined(RCCL_FLOAT8)
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rccl_float8 fp8_e4m3;
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rccl_bfloat8 fp8_e5m2;
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#endif
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void *ptr;
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};
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u64 = 0;
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@@ -1594,12 +1599,22 @@ static ncclResult_t hostToDevRedOp(
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opFull->op = ncclDevPreMulSum;
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f16 = __float2half(float(1.0/comm->nRanks)); // __double2half not supported pre CUDA 11.x
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break;
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#if defined(RCCL_BFLOAT16)
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#if defined(RCCL_BFLOAT16)
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case ncclBfloat16:
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opFull->op = ncclDevPreMulSum;
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bf16 = (rccl_bfloat16)(float(1.0/comm->nRanks));
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break;
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#endif
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#endif
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#if defined(RCCL_FLOAT8)
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case ncclFp8E4M3:
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opFull->op = ncclDevPreMulSum;
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fp8_e4m3 = static_cast<rccl_float8>(float(1.0/comm->nRanks));
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break;
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case ncclFp8E5M2:
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opFull->op = ncclDevPreMulSum;
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fp8_e5m2 = static_cast<rccl_bfloat8>(float(1.0/comm->nRanks));
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break;
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#endif
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case ncclFloat32:
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opFull->op = ncclDevPreMulSum;
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f32 = float(1.0/comm->nRanks);
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