kfdtest: Move KFDMemoryTest shaders to ShaderStore
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I3335ca1f9dbe849233cf85253e0e92b56a20b8c9
[ROCm/ROCR-Runtime commit: c926d83b5a]
This commit is contained in:
Graham Sider
committed by
Harish Kasiviswanathan
Harish Kasiviswanathan
parent
e67ec56091
commit
e628983aed
@@ -63,3 +63,228 @@ const char *AtomicIncIsa = R"(
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s_waitcnt 0
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s_endpgm
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)";
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/**
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* KFDMemoryTest
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*/
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const char *ScratchCopyDwordIsa = R"(
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.text
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// Copy the parameters from scalar registers to vector registers
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.if (.amdgcn.gfx_generation_number >= 9)
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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v_mov_b32 v2, s2
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v_mov_b32 v3, s3
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.else
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v_mov_b32_e32 v0, s0
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v_mov_b32_e32 v1, s1
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v_mov_b32_e32 v2, s2
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v_mov_b32_e32 v3, s3
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.endif
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// Setup the scratch parameters. This assumes a single 16-reg block
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.if (.amdgcn.gfx_generation_number >= 10)
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s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
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s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
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.elseif (.amdgcn.gfx_generation_number == 9)
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s_mov_b32 flat_scratch_lo, s4
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s_mov_b32 flat_scratch_hi, s5
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.else
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s_mov_b32 flat_scratch_lo, 8
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s_mov_b32 flat_scratch_hi, 0
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.endif
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// Copy a dword between the passed addresses
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flat_load_dword v4, v[0:1] slc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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flat_store_dword v[2:3], v4 slc
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s_endpgm
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)";
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/* Continuously poll src buffer and check buffer value
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* After src buffer is filled with specific value (0x5678,
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* by host program), fill dst buffer with specific
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* value(0x5678) and quit
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*/
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const char *PollMemoryIsa = R"(
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.text
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// Assume src address in s0, s1, and dst address in s2, s3
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s_movk_i32 s18, 0x5678
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.if (.amdgcn.gfx_generation_number >= 10)
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v_mov_b32 v0, s2
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v_mov_b32 v1, s3
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v_mov_b32 v2, 0x5678
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.endif
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LOOP:
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s_load_dword s16, s[0:1], 0x0 glc
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s_cmp_eq_i32 s16, s18
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s_cbranch_scc0 LOOP
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.if (.amdgcn.gfx_generation_number >= 10)
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flat_store_dword v[0:1], v2 slc
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.else
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s_store_dword s18, s[2:3], 0x0 glc
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.endif
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s_endpgm
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)";
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/* Similar to PollMemoryIsa except that the buffer
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* polled can be Non-coherant memory. SCC system-level
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* cache coherence is not supported in scalar (smem) path.
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* Use vmem operations with scc
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*
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* Note: Only works on Aldebaran, and even then the scc modifier
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* has been defeatured. This shader is more or less
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* deprecated.
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*/
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const char *PollNCMemoryIsa = R"(
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.text
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// Assume src address in s0, s1, and dst address in s2, s3
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v_mov_b32 v6, 0x5678
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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LOOP:
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flat_load_dword v4, v[0:1] scc
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v_cmp_eq_u32 vcc, v4, v6
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s_cbranch_vccz LOOP
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v_mov_b32 v0, s2
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v_mov_b32 v1, s3
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flat_store_dword v[0:1], v6 scc
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s_endpgm
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)";
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/* Input: A buffer of at least 3 dwords.
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* DW0: used as a signal. 0xcafe means it is signaled
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* DW1: Input buffer for device to read.
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* DW2: Output buffer for device to write.
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* Once receive signal, device will copy DW1 to DW2
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* This shader continously poll the signal buffer,
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* Once signal buffer is signaled, it copies input buffer
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* to output buffer
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*/
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const char *CopyOnSignalIsa = R"(
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.text
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// Assume input buffer in s0, s1
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.if (.amdgcn.gfx_generation_number >= 10)
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s_add_u32 s2, s0, 0x8
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s_addc_u32 s3, s1, 0x0
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s_mov_b32 s18, 0xcafe
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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v_mov_b32 v4, s2
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v_mov_b32 v5, s3
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.else
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s_mov_b32 s18, 0xcafe
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.endif
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POLLSIGNAL:
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s_load_dword s16, s[0:1], 0x0 glc
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s_cmp_eq_i32 s16, s18
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s_cbranch_scc0 POLLSIGNAL
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s_load_dword s17, s[0:1], 0x4 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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.if (.amdgcn.gfx_generation_number >= 10)
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v_mov_b32 v2, s17
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flat_store_dword v[4:5], v2 glc
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.else
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s_store_dword s17, s[0:1], 0x8 glc
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.endif
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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s_endpgm
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)";
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/* Continuously poll the flag at src buffer
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* After the flag of s[0:1] is 1 filled,
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* copy the value from s[0:1]+4 to dst buffer
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*
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* Note: Only works on GFX9 (only used in
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* aldebaran tests)
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*/
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const char *PollAndCopyIsa = R"(
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.text
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// Assume src buffer in s[0:1] and dst buffer in s[2:3]
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.if (.amdgcn.gfx_generation_number == 9 && .amdgcn.gfx_generation_stepping == 10)
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// Path for Aldebaran
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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v_mov_b32 v18, 0x1
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LOOP_ALDBRN:
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flat_load_dword v16, v[0:1] glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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v_cmp_eq_i32 vcc, v16, v18
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s_cbranch_vccz LOOP_ALDBRN
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buffer_invl2
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s_load_dword s17, s[0:1], 0x4 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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s_store_dword s17, s[2:3], 0x0 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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buffer_wbl2
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.else
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s_movk_i32 s18, 0x1
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LOOP:
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s_load_dword s16, s[0:1], 0x0 glc
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s_cmp_eq_i32 s16, s18
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s_cbranch_scc0 LOOP
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s_load_dword s17, s[0:1], 0x4 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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s_store_dword s17, s[2:3], 0x0 glc
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.endif
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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s_endpgm
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)";
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/* Input0: A buffer of at least 2 dwords.
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* DW0: used as a signal. Write 0x1 to signal
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* DW1: Write the value from 2nd input buffer
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* for other device to read.
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* Input1: A buffer of at least 2 dwords.
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* DW0: used as the value to be written.
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*
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* Note: Only works on Aldebaran
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*/
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const char *WriteFlagAndValueIsa = R"(
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.text
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// Assume two inputs buffer in s[0:1] and s[2:3]
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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s_load_dword s18, s[2:3], 0x0 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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s_store_dword s18, s[0:1], 0x4 glc
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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buffer_wbl2
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s_waitcnt vmcnt(0) & lgkmcnt(0)
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v_mov_b32 v16, 0x1
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flat_store_dword v[0:1], v16 glc
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s_endpgm
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)";
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/* Input0: A buffer of at least 2 dwords.
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* DW0: used as a signal. Write 0xcafe to signal
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* DW1: Write to this buffer for other device to read.
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* Input1: mmio base address
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*/
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const char *WriteAndSignalIsa = R"(
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.text
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// Assume input buffer in s0, s1
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.if (.amdgcn.gfx_generation_number >= 10)
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s_add_u32 s4, s0, 0x4
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s_addc_u32 s5, s1, 0x0
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v_mov_b32 v0, s0
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v_mov_b32 v1, s1
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v_mov_b32 v2, s2
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v_mov_b32 v3, s3
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v_mov_b32 v4, s4
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v_mov_b32 v5, s5
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v_mov_b32 v18, 0xbeef
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flat_store_dword v[4:5], v18 glc
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v_mov_b32 v18, 0x1
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flat_store_dword v[2:3], v18 glc
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v_mov_b32 v18, 0xcafe
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flat_store_dword v[0:1], v18 glc
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.else
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s_mov_b32 s18, 0xbeef
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s_store_dword s18, s[0:1], 0x4 glc
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s_mov_b32 s18, 0x1
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s_store_dword s18, s[2:3], 0 glc
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s_mov_b32 s18, 0xcafe
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s_store_dword s18, s[0:1], 0x0 glc
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.endif
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s_endpgm
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)";
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