From e70cadd514f34df13f9d6786c54b11917be7b02e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mirza=20Halil=C4=8Devi=C4=87?= <109971222+mirza-halilcevic@users.noreply.github.com> Date: Thu, 28 Dec 2023 16:41:42 +0100 Subject: [PATCH] EXSWHTEC-262 - Implement tests for atomic add operations #393 Change-Id: I11ff4658ef2076b25e0bdb91bbcd4f436b0fbd27 --- catch/unit/atomics/CMakeLists.txt | 9 + catch/unit/atomics/atomicAdd.cc | 167 +++++++++++ .../atomics/atomicAdd_negative_kernels.cc | 219 ++++++++++++++ .../atomics/atomicAdd_negative_kernels_rtc.hh | 273 ++++++++++++++++++ catch/unit/atomics/atomicAdd_system.cc | 177 ++++++++++++ catch/unit/atomics/safeAtomicAdd.cc | 123 ++++++++ catch/unit/atomics/unsafeAtomicAdd.cc | 124 ++++++++ 7 files changed, 1092 insertions(+) create mode 100644 catch/unit/atomics/atomicAdd.cc create mode 100644 catch/unit/atomics/atomicAdd_negative_kernels.cc create mode 100644 catch/unit/atomics/atomicAdd_negative_kernels_rtc.hh create mode 100644 catch/unit/atomics/atomicAdd_system.cc create mode 100644 catch/unit/atomics/safeAtomicAdd.cc create mode 100644 catch/unit/atomics/unsafeAtomicAdd.cc diff --git a/catch/unit/atomics/CMakeLists.txt b/catch/unit/atomics/CMakeLists.txt index bba917bc2f..f7ab04b3b6 100644 --- a/catch/unit/atomics/CMakeLists.txt +++ b/catch/unit/atomics/CMakeLists.txt @@ -38,6 +38,10 @@ set(TEST_SRC atomic_builtins.cc acquire_release.cc sequential_consistency.cc + atomicAdd.cc + atomicAdd_system.cc + unsafeAtomicAdd.cc + safeAtomicAdd.cc atomicExch.cc atomicExch_system.cc __hip_atomic_fetch_and.cc @@ -47,6 +51,7 @@ set(TEST_SRC ) if(HIP_PLATFORM MATCHES "nvidia") + set_source_files_properties(atomicAdd_system.cc PROPERTIES COMPILE_FLAGS "-gencode arch=compute_60,code=sm_60 -gencode arch=compute_70,code=sm_70 -gencode arch=compute_80,code=sm_80") set_source_files_properties(atomicExch_system.cc PROPERTIES COMPILE_FLAGS "-gencode arch=compute_60,code=sm_60 -gencode arch=compute_70,code=sm_70 -gencode arch=compute_80,code=sm_80") set_source_files_properties(atomicAnd_system.cc PROPERTIES COMPILE_FLAGS "-gencode arch=compute_60,code=sm_60 -gencode arch=compute_70,code=sm_70 -gencode arch=compute_80,code=sm_80") set_source_files_properties(atomicOr_system.cc PROPERTIES COMPILE_FLAGS "-gencode arch=compute_60,code=sm_60 -gencode arch=compute_70,code=sm_70 -gencode arch=compute_80,code=sm_80") @@ -95,6 +100,10 @@ add_test(NAME Unit_AtomicBuiltins_Negative_Parameters COMMAND python3 ${CMAKE_CURRENT_SOURCE_DIR}/../compileAndCaptureOutput.py ${CMAKE_CURRENT_SOURCE_DIR} ${HIP_PLATFORM} ${HIP_PATH} atomic_builtins_kernels.cc 60 27) # Should be 35 warnings, see EXSWHTEC-309 +add_test(NAME Unit_atomicAdd_Negative_Parameters + COMMAND python3 ${CMAKE_CURRENT_SOURCE_DIR}/../compileAndCaptureOutput.py + ${CMAKE_CURRENT_SOURCE_DIR} ${HIP_PLATFORM} ${HIP_PATH} + atomicAdd_negative_kernels.cc 48) # SWDEV-435667: Below 2 tests failed in stress test on 01/12/23 #add_test(NAME Unit_atomicExch_Negative_Parameters diff --git a/catch/unit/atomics/atomicAdd.cc b/catch/unit/atomics/atomicAdd.cc new file mode 100644 index 0000000000..76eef23ac8 --- /dev/null +++ b/catch/unit/atomics/atomicAdd.cc @@ -0,0 +1,167 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "arithmetic_common.hh" +#include "atomicAdd_negative_kernels_rtc.hh" + +#include + +/** + * @addtogroup atomicAdd atomicAdd + * @{ + * @ingroup AtomicsTest + */ + +/** + * Test Description + * ------------------------ + * - Executes a single kernel on a single device wherein all threads will perform an atomic + * addition on a target memory location. Each thread will add the same value to the memory location, + * storing the return value into a separate output array slot corresponding to it. Once complete, + * the output array and target memory is validated to contain all the expected values. Several + * memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of atomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Shared memory + * - Several grid and block dimension combinations (only one block is used for shared memory). + * Test source + * ------------------------ + * - unit/atomics/atomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_atomicAdd_Positive", "", int, unsigned int, unsigned long, + unsigned long long, float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceSingleKernelTest(1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, cache_line_size); + } + } +} + +/** + * Test Description + * ------------------------ + * - Executes a kernel two times concurrently on a single device wherein all threads will perform + * an atomic addition on a target memory location. Each thread will add the same value to the memory + * location, storing the return value into a separate output array slot corresponding to it. Once + * complete, the output array and target memory is validated to contain all the expected values. + * Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of atomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/atomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_atomicAdd_Positive_Multi_Kernel", "", int, unsigned int, unsigned long, + unsigned long long, float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceMultipleKernelTest(2, 1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + cache_line_size); + } + } +} + +/** + * Test Description + * ------------------------ + * - RTCs kernels that pass combinations of arguments of invalid types for all overloads of + * atomicAdd. + * Test source + * ------------------------ + * - unit/atomics/atomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEST_CASE("Unit_atomicAdd_Negative_Parameters_RTC") { + hiprtcProgram program{}; + + const auto program_source = GENERATE(kAtomicAdd_int, kAtomicAdd_uint, kAtomicAdd_ulong, + kAtomicAdd_ulonglong, kAtomicAdd_float, kAtomicAdd_double); + HIPRTC_CHECK( + hiprtcCreateProgram(&program, program_source, "atomicAdd_negative.cc", 0, nullptr, nullptr)); + hiprtcResult result{hiprtcCompileProgram(program, 0, nullptr)}; + + // Get the compile log and count compiler error messages + size_t log_size{}; + HIPRTC_CHECK(hiprtcGetProgramLogSize(program, &log_size)); + std::string log(log_size, ' '); + HIPRTC_CHECK(hiprtcGetProgramLog(program, log.data())); + int error_count{0}; + + int expected_error_count{8}; + std::string error_message{"error:"}; + + size_t n_pos = log.find(error_message, 0); + while (n_pos != std::string::npos) { + ++error_count; + n_pos = log.find(error_message, n_pos + 1); + } + + HIPRTC_CHECK(hiprtcDestroyProgram(&program)); + HIPRTC_CHECK_ERROR(result, HIPRTC_ERROR_COMPILATION); + REQUIRE(error_count == expected_error_count); +} diff --git a/catch/unit/atomics/atomicAdd_negative_kernels.cc b/catch/unit/atomics/atomicAdd_negative_kernels.cc new file mode 100644 index 0000000000..e0e8112cdf --- /dev/null +++ b/catch/unit/atomics/atomicAdd_negative_kernels.cc @@ -0,0 +1,219 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include + +class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} +}; + +/* int atomicAdd(int* address, int val) */ +__global__ void atomicAdd_int_v1(int* address, int* result) { *result = atomicAdd(&address, 1234); } + +__global__ void atomicAdd_int_v2(int* address, int* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_int_v3(int* address, int* result) { *result = atomicAdd(1234, 1234); } + +__global__ void atomicAdd_int_v4(Dummy* address, int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_int_v5(char* address, int* result) { *result = atomicAdd(address, 1234); } + +__global__ void atomicAdd_int_v6(short* address, int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_int_v7(long* address, int* result) { *result = atomicAdd(address, 1234); } + +__global__ void atomicAdd_int_v8(long long* address, int* result) { + *result = atomicAdd(address, 1234); +} + +/* unsigned int atomicAdd(unsigned int* address, unsigned int val) */ +__global__ void atomicAdd_uint_v1(unsigned int* address, unsigned int* result) { + *result = atomicAdd(&address, 1234); +} + +__global__ void atomicAdd_uint_v2(unsigned int* address, unsigned int* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_uint_v3(unsigned int* address, unsigned int* result) { + *result = atomicAdd(1234, 1234); +} + +__global__ void atomicAdd_uint_v4(Dummy* address, unsigned int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_uint_v5(char* address, unsigned int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_uint_v6(short* address, unsigned int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_uint_v7(long* address, unsigned int* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_uint_v8(long long* address, unsigned int* result) { + *result = atomicAdd(address, 1234); +} + +/* atomicAdd(unsigned long* address, unsigned long val) */ +__global__ void atomicAdd_ulong_v1(unsigned long* address, unsigned long* result) { + *result = atomicAdd(&address, 1234); +} + +__global__ void atomicAdd_ulong_v2(unsigned long* address, unsigned long* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_ulong_v3(unsigned long* address, unsigned long* result) { + *result = atomicAdd(1234, 1234); +} + +__global__ void atomicAdd_ulong_v4(Dummy* address, unsigned long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulong_v5(char* address, unsigned long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulong_v6(short* address, unsigned long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulong_v7(long* address, unsigned long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulong_v8(long long* address, unsigned long* result) { + *result = atomicAdd(address, 1234); +} + +/* atomicAdd(unsigned long long* address, unsigned long long val) */ +__global__ void atomicAdd_ulonglong_v1(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(&address, 1234); +} + +__global__ void atomicAdd_ulonglong_v2(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_ulonglong_v3(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(1234, 1234); +} + +__global__ void atomicAdd_ulonglong_v4(Dummy* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulonglong_v5(char* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulonglong_v6(short* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulonglong_v7(long* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); +} + +__global__ void atomicAdd_ulonglong_v8(long long* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); +} + +/* atomicAdd(float* address, float val) */ +__global__ void atomicAdd_float_v1(float* address, float* result) { + *result = atomicAdd(&address, 1234.f); +} + +__global__ void atomicAdd_float_v2(float* address, float* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_float_v3(float* address, float* result) { + *result = atomicAdd(1234.f, 1234.f); +} + +__global__ void atomicAdd_float_v4(Dummy* address, float* result) { + *result = atomicAdd(address, 1234.f); +} + +__global__ void atomicAdd_float_v5(char* address, float* result) { + *result = atomicAdd(address, 1234.f); +} + +__global__ void atomicAdd_float_v6(short* address, float* result) { + *result = atomicAdd(address, 1234.f); +} + +__global__ void atomicAdd_float_v7(long* address, float* result) { + *result = atomicAdd(address, 1234.f); +} + +__global__ void atomicAdd_float_v8(long long* address, float* result) { + *result = atomicAdd(address, 1234); +} + +/* atomicAdd(double* address, double val) */ +__global__ void atomicAdd_double_v1(double* address, double* result) { + *result = atomicAdd(&address, 1234.0); +} + +__global__ void atomicAdd_double_v2(double* address, double* result) { + *result = atomicAdd(address, address); +} + +__global__ void atomicAdd_double_v3(double* address, double* result) { + *result = atomicAdd(1234.0, 1234.0); +} + +__global__ void atomicAdd_double_v4(Dummy* address, double* result) { + *result = atomicAdd(address, 1234.0); +} + +__global__ void atomicAdd_double_v5(char* address, double* result) { + *result = atomicAdd(address, 1234.0); +} + +__global__ void atomicAdd_double_v6(short* address, double* result) { + *result = atomicAdd(address, 1234.0); +} + +__global__ void atomicAdd_double_v7(long* address, double* result) { + *result = atomicAdd(address, 1234.0); +} + +__global__ void atomicAdd_double_v8(long long* address, double* result) { + *result = atomicAdd(address, 1234.0); +} diff --git a/catch/unit/atomics/atomicAdd_negative_kernels_rtc.hh b/catch/unit/atomics/atomicAdd_negative_kernels_rtc.hh new file mode 100644 index 0000000000..c5141d03bc --- /dev/null +++ b/catch/unit/atomics/atomicAdd_negative_kernels_rtc.hh @@ -0,0 +1,273 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#pragma once + +/* +Negative kernels used for the atomics negative Test Cases that are using RTC. +*/ + +static constexpr auto kAtomicAdd_int{ + R"( + __global__ void atomicAdd_int_v1(int* address, int* result) { + *result = atomicAdd(&address, 1234); + } + + __global__ void atomicAdd_int_v2(int* address, int* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_int_v3(int* address, int* result) { + *result = atomicAdd(1234, 1234); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_int_v4(Dummy* address, int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_int_v5(char* address, int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_int_v6(short* address, int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_int_v7(long* address, int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_int_v8(long long* address, int* result) { + *result = atomicAdd(address, 1234); + } + )"}; + +static constexpr auto kAtomicAdd_uint{ + R"( + __global__ void atomicAdd_uint_v1(unsigned int* address, unsigned int* result) { + *result = atomicAdd(&address, 1234); + } + + __global__ void atomicAdd_uint_v2(unsigned int* address, unsigned int* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_uint_v3(unsigned int* address, unsigned int* result) { + *result = atomicAdd(1234, 1234); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_uint_v4(Dummy* address, unsigned int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_uint_v5(char* address, unsigned int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_uint_v6(short* address, unsigned int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_uint_v7(long* address, unsigned int* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_uint_v8(long long* address, unsigned int* result) { + *result = atomicAdd(address, 1234); + } + )"}; + +static constexpr auto kAtomicAdd_ulong{ + R"( + __global__ void atomicAdd_ulong_v1(unsigned long* address, unsigned long* result) { + *result = atomicAdd(&address, 1234); + } + + __global__ void atomicAdd_ulong_v2(unsigned long* address, unsigned long* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_ulong_v3(unsigned long* address, unsigned long* result) { + *result = atomicAdd(1234, 1234); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_ulong_v4(Dummy* address, unsigned long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulong_v5(char* address, unsigned long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulong_v6(short* address, unsigned long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulong_v7(long* address, unsigned long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulong_v8(long long* address, unsigned long* result) { + *result = atomicAdd(address, 1234); + } + )"}; + +static constexpr auto kAtomicAdd_ulonglong{ + R"( + __global__ void atomicAdd_ulonglong_v1(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(&address, 1234); + } + + __global__ void atomicAdd_ulonglong_v2(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_ulonglong_v3(unsigned long long* address, unsigned long long* result) { + *result = atomicAdd(1234, 1234); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_ulonglong_v4(Dummy* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulonglong_v5(char* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulonglong_v6(short* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulonglong_v7(long* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); + } + + __global__ void atomicAdd_ulonglong_v8(long long* address, unsigned long long* result) { + *result = atomicAdd(address, 1234); + } + )"}; + +static constexpr auto kAtomicAdd_float{ + R"( + __global__ void atomicAdd_float_v1(float* address, float* result) { + *result = atomicAdd(&address, 1234.f); + } + + __global__ void atomicAdd_float_v2(float* address, float* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_float_v3(float* address, float* result) { + *result = atomicAdd(1234.f, 1234.f); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_float_v4(Dummy* address, float* result) { + *result = atomicAdd(address, 1234.f); + } + + __global__ void atomicAdd_float_v5(char* address, float* result) { + *result = atomicAdd(address, 1234.f); + } + + __global__ void atomicAdd_float_v6(short* address, float* result) { + *result = atomicAdd(address, 1234.f); + } + + __global__ void atomicAdd_float_v7(long* address, float* result) { + *result = atomicAdd(address, 1234.f); + } + + __global__ void atomicAdd_float_v8(long long* address, float* result) { + *result = atomicAdd(address, 1234); + } + )"}; + +static constexpr auto kAtomicAdd_double{ + R"( + __global__ void atomicAdd_double_v1(double* address, double* result) { + *result = atomicAdd(&address, 1234.0); + } + + __global__ void atomicAdd_double_v2(double* address, double* result) { + *result = atomicAdd(address, address); + } + + __global__ void atomicAdd_double_v3(double* address, double* result) { + *result = atomicAdd(1234.0, 1234.0); + } + + class Dummy { + public: + __device__ Dummy() {} + __device__ ~Dummy() {} + }; + + __global__ void atomicAdd_double_v4(Dummy* address, double* result) { + *result = atomicAdd(address, 1234.0); + } + + __global__ void atomicAdd_double_v5(char* address, double* result) { + *result = atomicAdd(address, 1234.0); + } + + __global__ void atomicAdd_double_v6(short* address, double* result) { + *result = atomicAdd(address, 1234.0); + } + + __global__ void atomicAdd_double_v7(long* address, double* result) { + *result = atomicAdd(address, 1234.0); + } + + __global__ void atomicAdd_double_v8(long long* address, double* result) { + *result = atomicAdd(address, 1234.0); + } + )"}; diff --git a/catch/unit/atomics/atomicAdd_system.cc b/catch/unit/atomics/atomicAdd_system.cc new file mode 100644 index 0000000000..c51ce0ad1f --- /dev/null +++ b/catch/unit/atomics/atomicAdd_system.cc @@ -0,0 +1,177 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "arithmetic_common.hh" + +#include + +/** + * @addtogroup atomicAdd_system atomicAdd_system + * @{ + * @ingroup AtomicsTest + */ + +/** + * Test Description + * ------------------------ + * - Executes a kernel two times concurrently on a two devices wherein all threads will perform + * an atomic addition on a target memory location. Each thread will add the same value to the memory + * location, storing the return value into a separate output array slot corresponding to it. Once + * complete, the output array and target memory is validated to contain all the expected values. + * Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of atomicAdd_system + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/atomicAdd_system.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_atomicAdd_system_Positive_Peer_GPUs", "", int, unsigned int, unsigned long, + unsigned long long, float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, 1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, warp_size, sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, warp_size, cache_line_size); + } + } +} + +/** + * Test Description + * ------------------------ + * - Executes a kernel on a single device wherein all threads will perform + * an atomic addition on a target memory location. Each thread will add the same value to the memory + * location, storing the return value into a separate output array slot corresponding to it. While + * the kernel is running, the host performs atomic additions, in 4 threads, on the same memory + * location(s). Once complete, the output array and target memory is validated to contain all the + * expected values. Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of atomicAdd_system + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/atomicAdd_system.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_atomicAdd_system_Positive_Host_And_GPU", "", int, unsigned int, + unsigned long, unsigned long long, float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 1, 1, 1, sizeof(TestType), 4); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 1, 1, warp_size, sizeof(TestType), 4); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 1, 1, warp_size, cache_line_size, 4); + } + } +} + +/** + * Test Description + * ------------------------ + * - Executes a kernel two times on two devices wherein all threads will perform + * an atomic addition on a target memory location. Each thread will add the same value to the memory + * location, storing the return value into a separate output array slot corresponding to it. While + * the kernel is running, the host performs atomic additions, in 4 threads, on the same memory + * location(s). Once complete, the output array and target memory is validated to contain all the + * expected values. Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of atomicAdd_system + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/atomicAdd_system.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_atomicAdd_system_Positive_Host_And_Peer_GPUs", "", int, unsigned int, + unsigned long, unsigned long long, float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, 1, sizeof(TestType), 4); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, warp_size, sizeof(TestType), 4); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + MultipleDeviceMultipleKernelAndHostTest( + 2, 2, warp_size, cache_line_size, 4); + } + } +} diff --git a/catch/unit/atomics/safeAtomicAdd.cc b/catch/unit/atomics/safeAtomicAdd.cc new file mode 100644 index 0000000000..cfc760a7ce --- /dev/null +++ b/catch/unit/atomics/safeAtomicAdd.cc @@ -0,0 +1,123 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "arithmetic_common.hh" + +#include + +/** + * @addtogroup safeAtomicAdd safeAtomicAdd + * @{ + * @ingroup AtomicsTest + */ + +/** + * Test Description + * ------------------------ + * - Executes a single kernel on a single device wherein all threads will perform an atomic + * addition on a target memory location. Each thread will add the same value to the memory location, + * storing the return value into a separate output array slot corresponding to it. Once complete, + * the output array and target memory is validated to contain all the expected values. Several + * memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of safeAtomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Shared memory + * - Several grid and block dimension combinations (only one block is used for shared memory). + * Test source + * ------------------------ + * - unit/atomics/safeAtomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_safeAtomicAdd_Positive", "", float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceSingleKernelTest(1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, + sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, cache_line_size); + } + } +} + +/** + * Test Description + * ------------------------ + * - Executes a kernel two times concurrently on a single device wherein all threads will + * perform an atomic addition on a target memory location. Each thread will add the same value to + * the memory location, storing the return value into a separate output array slot corresponding + * to it. Once complete, the output array and target memory is validated to contain all the + * expected values. Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of safeAtomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/safeAtomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_safeAtomicAdd_Positive_Multi_Kernel", "", float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceMultipleKernelTest(2, 1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + cache_line_size); + } + } +} diff --git a/catch/unit/atomics/unsafeAtomicAdd.cc b/catch/unit/atomics/unsafeAtomicAdd.cc new file mode 100644 index 0000000000..8c717c7bf5 --- /dev/null +++ b/catch/unit/atomics/unsafeAtomicAdd.cc @@ -0,0 +1,124 @@ +/* +Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. +*/ + +#include "arithmetic_common.hh" + +#include + +/** + * @addtogroup unsafeAtomicAdd unsafeAtomicAdd + * @{ + * @ingroup AtomicsTest + */ + +/** + * Test Description + * ------------------------ + * - Executes a single kernel on a single device wherein all threads will perform an atomic + * addition on a target memory location. Each thread will add the same value to the memory location, + * storing the return value into a separate output array slot corresponding to it. Once complete, + * the output array and target memory is validated to contain all the expected values. Several + * memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of unsafeAtomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Shared memory + * - Several grid and block dimension combinations (only one block is used for shared memory). + * Test source + * ------------------------ + * - unit/atomics/unsafeAtomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_unsafeAtomicAdd_Positive", "", float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceSingleKernelTest(1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, + sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceSingleKernelTest(warp_size, + cache_line_size); + } + } +} + +/** + * Test Description + * ------------------------ + * - Executes a kernel two times concurrently on a single device wherein all threads will + * perform an atomic addition on a target memory location. Each thread will add the same value to + * the memory location, storing the return value into a separate output array slot corresponding + * to it. Once complete, the output array and target memory is validated to contain all the + * expected values. Several memory access patterns are tested: + * -# All threads add to a single, compile time deducible, memory location + * -# Each thread targets an array containing warp_size elements, using tid % warp_size + * for indexing + * -# Same as the above, but the elements are spread out by L1 cache line size bytes. + * + * - The test is run for: + * - All overloads of unsafeAtomicAdd + * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory + * - Several grid and block dimension combinations. + * Test source + * ------------------------ + * - unit/atomics/unsafeAtomicAdd.cc + * Test requirements + * ------------------------ + * - HIP_VERSION >= 5.2 + */ +TEMPLATE_TEST_CASE("Unit_unsafeAtomicAdd_Positive_Multi_Kernel", "", float, double) { + int warp_size = 0; + HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); + const auto cache_line_size = 128u; + + for (auto current = 0; current < cmd_options.iterations; ++current) { + DYNAMIC_SECTION("Same address " << current) { + SingleDeviceMultipleKernelTest(2, 1, sizeof(TestType)); + } + + DYNAMIC_SECTION("Adjacent addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + sizeof(TestType)); + } + + DYNAMIC_SECTION("Scattered addresses " << current) { + SingleDeviceMultipleKernelTest(2, warp_size, + cache_line_size); + } + } +}