Patch from github.

At the moment it is not possible to build ROCr with Clang. This is
a spurious limitation. The present PR addresses it by guarding GCC
only flags and by fixing some additional warnings that Clang triggers;
one of said warnings did outline a rather interesting issue with math
being done on void*s. - AlexVlx

Void ptr arithmetic had already been fixed in amd-master branch.

Change-Id: I5ee97e20b5c40b10dd73facecabe75f02ba46462

runtime/hsa-runtime/core/inc/host_queue.h

@@ -162,7 +162,7 @@ class HostQueue : public Queue {
   void operator delete(void*, void*) {}
 
  protected:
-  bool _IsA(Queue::rtti_t id) const { return id == &rtti_id_; }
+  bool _IsA(Queue::rtti_t id) const override { return id == &rtti_id_; }
 
  private:
   static int rtti_id_;

runtime/hsa-runtime/core/inc/intercept_queue.h

@@ -122,7 +122,7 @@ class QueueWrapper : public Queue {
   void SetProfiling(bool enabled) override { wrapped->SetProfiling(enabled); }
 
  protected:
-  void do_set_public_handle(hsa_queue_t* handle) {
+  void do_set_public_handle(hsa_queue_t* handle) override {
     public_handle_ = handle;
     wrapped->set_public_handle(wrapped.get(), handle);
   }
@@ -243,12 +243,12 @@ class InterceptQueue : public QueueProxy, private LocalSignal, public DoorbellSi
   /// @brief Update signal value using Relaxed semantics
   ///
   /// @param value Value of signal to update with
-  void StoreRelaxed(hsa_signal_value_t value);
+  void StoreRelaxed(hsa_signal_value_t value) override;
 
   /// @brief Update signal value using Release semantics
   ///
   /// @param value Value of signal to update with
-  void StoreRelease(hsa_signal_value_t value) {
+  void StoreRelease(hsa_signal_value_t value) override {
     std::atomic_thread_fence(std::memory_order_release);
     StoreRelaxed(value);
   }
@@ -257,7 +257,7 @@ class InterceptQueue : public QueueProxy, private LocalSignal, public DoorbellSi
   static __forceinline bool IsType(core::Queue* queue) { return queue->IsType(&rtti_id_); }
 
  protected:
-  bool _IsA(Queue::rtti_t id) const { return id == &rtti_id_; }
+  bool _IsA(Queue::rtti_t id) const override { return id == &rtti_id_; }
 
  private:
   static int rtti_id_;

runtime/hsa-runtime/core/runtime/amd_blit_sdma.cpp

@@ -2,24 +2,24 @@
 //
 // The University of Illinois/NCSA
 // Open Source License (NCSA)
-// 
+//
 // Copyright (c) 2014-2015, Advanced Micro Devices, Inc. All rights reserved.
-// 
+//
 // Developed by:
-// 
+//
 //                 AMD Research and AMD HSA Software Development
-// 
+//
 //                 Advanced Micro Devices, Inc.
-// 
+//
 //                 www.amd.com
-// 
+//
 // Permission is hereby granted, free of charge, to any person obtaining a copy
 // of this software and associated documentation files (the "Software"), to
 // deal with the Software without restriction, including without limitation
 // the rights to use, copy, modify, merge, publish, distribute, sublicense,
 // and/or sell copies of the Software, and to permit persons to whom the
 // Software is furnished to do so, subject to the following conditions:
-// 
+//
 //  - Redistributions of source code must retain the above copyright notice,
 //    this list of conditions and the following disclaimers.
 //  - Redistributions in binary form must reproduce the above copyright
@@ -29,7 +29,7 @@
 //    nor the names of its contributors may be used to endorse or promote
 //    products derived from this Software without specific prior written
 //    permission.
-// 
+//
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -730,7 +730,7 @@ void BlitSdma<RingIndexTy, HwIndexMonotonic, SizeToCountOffset>::BuildCopyRectCo
     Ex. range->x=71, assume max range is 16 elements:  We can break at 64 giving tiles:
     [0,63], [64-70] (width 64 & 7).  64 is covered by element 4 (16B) and 7 is covered by element 0
     (1B).  Exactly covering 71 requires using element 0.
-  
+
   Base addresses in each tile must be DWORD aligned, if not then the offset from an aligned address
   must be represented in elements.  This may reduce the size of the element, but since elements are
   integer multiples of each other this is harmless.

runtime/hsa-runtime/core/runtime/intercept_queue.cpp

@@ -63,7 +63,7 @@ static const uint16_t kBarrierHeader = (HSA_PACKET_TYPE_BARRIER_AND << HSA_PACKE
     (HSA_FENCE_SCOPE_NONE << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE) |
     (HSA_FENCE_SCOPE_NONE << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE);
 
-static const hsa_barrier_and_packet_t kBarrierPacket = {kInvalidHeader, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const hsa_barrier_and_packet_t kBarrierPacket = {kInvalidHeader, 0, 0, {}, 0, {}};
 
 int InterceptQueue::rtti_id_ = 0;