Event counter support
XGMI related events are supported Change-Id: If17036fe890c8be45da3654353599821b5828c14
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Chris Freehill committed
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@@ -0,0 +1,304 @@
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/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2019, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
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* of this software and associated documentation files (the "Software"), to
|
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* deal with the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
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*
|
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* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimers.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimers in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
* - Neither the names of <Name of Development Group, Name of Institution>,
|
||||
* nor the names of its contributors may be used to endorse or promote
|
||||
* products derived from this Software without specific prior written
|
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* permission.
|
||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include <iostream>
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#include <bitset>
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#include <string>
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#include <algorithm>
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#include <vector>
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#include "gtest/gtest.h"
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#include "rocm_smi/rocm_smi.h"
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#include "rocm_smi_test/functional/perf_cntr_read_write.h"
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#include "rocm_smi_test/test_common.h"
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PerfCntrEvtGrp::PerfCntrEvtGrp(rsmi_event_group_t grp, uint32_t first,
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uint32_t last, std::string name) : grp_(grp), first_evt_(first),
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last_evt_(last), name_(name) {
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num_events_ = last_evt_ - first_evt_ + 1;
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}
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PerfCntrEvtGrp::~PerfCntrEvtGrp() {}
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// Add new event groups to test here
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#define PC_EVT_GRP(SHRT, NAME) \
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PerfCntrEvtGrp(RSMI_EVNT_GRP_##SHRT, RSMI_EVNT_##SHRT##_FIRST, \
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RSMI_EVNT_##SHRT##_LAST, NAME)
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static const std::vector<PerfCntrEvtGrp> s_event_groups = {
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PC_EVT_GRP(XGMI, "XGMI")
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};
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TestPerfCntrReadWrite::TestPerfCntrReadWrite() : TestBase() {
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set_title("RSMI Performance Counter Read/Write Test");
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set_description("The Performance counter tests verify that performance"
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" counters can be controlled and read properly.");
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}
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TestPerfCntrReadWrite::~TestPerfCntrReadWrite(void) {
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}
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void TestPerfCntrReadWrite::SetUp(void) {
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TestBase::SetUp();
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return;
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}
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void TestPerfCntrReadWrite::DisplayTestInfo(void) {
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TestBase::DisplayTestInfo();
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}
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void TestPerfCntrReadWrite::DisplayResults(void) const {
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TestBase::DisplayResults();
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return;
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}
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void TestPerfCntrReadWrite::Close() {
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// This will close handles opened within rsmitst utility calls and call
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// rsmi_shut_down(), so it should be done after other hsa cleanup
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TestBase::Close();
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}
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#define RSMI_EVNT_ENUM_FIRST(GRP_NAME) RSMI_EVNT_##GRP_NAME##_FIRST
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#define RSMI_EVNT_ENUM_LAST(GRP_NAME) RSMI_EVNT_##GRP_NAME##_LAST
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// Refactor this to handle different event groups once we have > 1 event group
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void
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TestPerfCntrReadWrite::testEventsIndividually(uint32_t dv_ind) {
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rsmi_event_handle_t evt_handle;
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rsmi_status_t ret;
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rsmi_counter_value_t val;
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std::cout << "****************************" << std::endl;
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std::cout << "Test each event individually" << std::endl;
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std::cout << "****************************" << std::endl;
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for (PerfCntrEvtGrp grp : s_event_groups) {
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if (rsmi_dev_counter_group_supported(dv_ind, grp.group())
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== RSMI_STATUS_NOT_SUPPORTED) {
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continue;
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}
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IF_VERB(STANDARD) {
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std::cout << "Testing Event Group " << grp.name() << std::endl;
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}
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for (uint32_t evnt = grp.first_evt(); evnt <= grp.last_evt(); ++evnt) {
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IF_VERB(STANDARD) {
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std::cout << "\tTesting Event Type " << evnt << std::endl;
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}
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IF_VERB(STANDARD) {
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std::cout << "\t\tCreating event..." << std::endl;
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}
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ret = rsmi_dev_counter_create(dv_ind,
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static_cast<rsmi_event_type_t>(evnt), &evt_handle);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\t\tStart Counting..." << std::endl;
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}
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ret = rsmi_counter_control(evt_handle, RSMI_CNTR_CMD_START, nullptr);
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CHK_ERR_ASRT(ret)
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sleep(1);
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IF_VERB(STANDARD) {
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std::cout << "\t\tStop Counting..." << std::endl;
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}
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ret = rsmi_counter_control(evt_handle, RSMI_CNTR_CMD_STOP, nullptr);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\t\tRead Counter..." << std::endl;
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}
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ret = rsmi_counter_read(evt_handle, &val);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\t\tSuccessfully read value: " << std::endl;
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std::cout << "\t\t\tValue: " << val.value << std::endl;
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std::cout << "\t\t\tTime Enabled: " << val.time_enabled << std::endl;
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std::cout << "\t\t\tTime Running: " << val.time_running << std::endl;
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}
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IF_VERB(STANDARD) {
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std::cout << "\t\tRe-start Counting..." << std::endl;
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}
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ret = rsmi_counter_control(evt_handle, RSMI_CNTR_CMD_START, nullptr);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\t\tRead free-running Counter..." << std::endl;
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}
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ret = rsmi_counter_read(evt_handle, &val);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\t\tSuccessfully read value: " << std::endl;
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std::cout << "\t\t\tValue: " << val.value << std::endl;
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std::cout << "\t\t\tTime Enabled: " << val.time_enabled << std::endl;
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std::cout << "\t\t\tTime Running: " << val.time_running << std::endl;
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}
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ret = rsmi_dev_counter_destroy(evt_handle);
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CHK_ERR_ASRT(ret)
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}
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}
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}
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// Refactor this to handle different event groups once we have > 1 event group
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void
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TestPerfCntrReadWrite::testEventsSimultaneously(uint32_t dv_ind) {
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rsmi_event_handle_t evt_handle[RSMI_EVNT_XGMI_LAST -
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RSMI_EVNT_XGMI_FIRST + 1];
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rsmi_status_t ret;
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rsmi_counter_value_t val;
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uint32_t avail_counters;
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std::cout << "****************************" << std::endl;
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std::cout << "Test events simultaneously" << std::endl;
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std::cout << "****************************" << std::endl;
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for (PerfCntrEvtGrp grp : s_event_groups) {
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if (rsmi_dev_counter_group_supported(dv_ind, grp.group())
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== RSMI_STATUS_NOT_SUPPORTED) {
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std::cout << "\tEvent Group" << grp.name() <<
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" is not supported. Skipping." << std::endl;
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continue;
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}
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IF_VERB(STANDARD) {
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std::cout << "Testing Event Group " << grp.name() << std::endl;
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}
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ret = rsmi_counter_available_counters_get(dv_ind, grp.group(),
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&avail_counters);
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std::cout << "Available Counters: " << avail_counters << std::endl;
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CHK_ERR_ASRT(ret)
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uint32_t tmp;
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for (uint32_t evnt = grp.first_evt(); evnt <= grp.last_evt();
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evnt += avail_counters) {
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IF_VERB(STANDARD) {
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std::cout << "\tTesting Event Type " << evnt << std::endl;
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}
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IF_VERB(STANDARD) {
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std::cout << "\tCreating events..." << std::endl;
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}
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for (uint32_t j = 0; j < avail_counters; ++j) {
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tmp = static_cast<rsmi_event_type_t>(evnt + j);
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IF_VERB(STANDARD) {
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std::cout << "\tEvent Type " << tmp << std::endl;
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}
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ret = rsmi_dev_counter_create(dv_ind,
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static_cast<rsmi_event_type_t>(tmp), &evt_handle[tmp]);
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CHK_ERR_ASRT(ret)
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}
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IF_VERB(STANDARD) {
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std::cout << "\tStart Counters..." << std::endl;
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}
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uint32_t tmp_cntrs;
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for (uint32_t j = 0; j < avail_counters; ++j) {
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tmp = static_cast<rsmi_event_type_t>(evnt + j);
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ret = rsmi_counter_control(evt_handle[tmp], RSMI_CNTR_CMD_START,
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nullptr);
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CHK_ERR_ASRT(ret)
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ret = rsmi_counter_available_counters_get(dv_ind, grp.group(),
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&tmp_cntrs);
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CHK_ERR_ASRT(ret)
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ASSERT_EQ(tmp_cntrs, (avail_counters - j -1));
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}
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sleep(5);
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IF_VERB(STANDARD) {
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std::cout << "\tStop Counters..." << std::endl;
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}
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for (uint32_t j = 0; j < avail_counters; ++j) {
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tmp = static_cast<rsmi_event_type_t>(evnt + j);
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ret = rsmi_counter_control(evt_handle[tmp], RSMI_CNTR_CMD_STOP,
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nullptr);
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CHK_ERR_ASRT(ret)
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}
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IF_VERB(STANDARD) {
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std::cout << "\tRead Counters..." << std::endl;
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}
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for (uint32_t j = 0; j < avail_counters; ++j) {
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tmp = static_cast<rsmi_event_type_t>(evnt + j);
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ret = rsmi_counter_read(evt_handle[tmp], &val);
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CHK_ERR_ASRT(ret)
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IF_VERB(STANDARD) {
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std::cout << "\tCounter: " << tmp << std::endl;
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std::cout << "\tSuccessfully read value: " << std::endl;
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std::cout << "\t\tValue: " << val.value << std::endl;
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std::cout << "\t\tTime Enabled: " << val.time_enabled << std::endl;
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std::cout << "\t\tTime Running: " << val.time_running << std::endl;
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}
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}
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for (uint32_t j = 0; j < avail_counters; ++j) {
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tmp = static_cast<rsmi_event_type_t>(evnt + j);
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ret = rsmi_dev_counter_destroy(evt_handle[tmp]);
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CHK_ERR_ASRT(ret)
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}
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}
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}
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}
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void TestPerfCntrReadWrite::Run(void) {
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TestBase::Run();
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for (uint32_t dv_ind = 0; dv_ind < num_monitor_devs(); ++dv_ind) {
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PrintDeviceHeader(dv_ind);
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testEventsIndividually(dv_ind);
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testEventsSimultaneously(dv_ind);
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}
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}
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@@ -0,0 +1,98 @@
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/*
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* =============================================================================
|
||||
* ROC Runtime Conformance Release License
|
||||
* =============================================================================
|
||||
* The University of Illinois/NCSA
|
||||
* Open Source License (NCSA)
|
||||
*
|
||||
* Copyright (c) 2019, Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Developed by:
|
||||
*
|
||||
* AMD Research and AMD ROC Software Development
|
||||
*
|
||||
* Advanced Micro Devices, Inc.
|
||||
*
|
||||
* www.amd.com
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to
|
||||
* deal with the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimers.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimers in
|
||||
* the documentation and/or other materials provided with the distribution.
|
||||
* - Neither the names of <Name of Development Group, Name of Institution>,
|
||||
* nor the names of its contributors may be used to endorse or promote
|
||||
* products derived from this Software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS WITH THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
#ifndef TESTS_ROCM_SMI_TEST_FUNCTIONAL_PERF_CNTR_READ_WRITE_H_
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#define TESTS_ROCM_SMI_TEST_FUNCTIONAL_PERF_CNTR_READ_WRITE_H_
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#include <string>
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#include "rocm_smi_test/test_base.h"
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class TestPerfCntrReadWrite : public TestBase {
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public:
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TestPerfCntrReadWrite();
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// @Brief: Destructor for test case of TestPerfCntrReadWrite
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virtual ~TestPerfCntrReadWrite();
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// @Brief: Setup the environment for measurement
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virtual void SetUp();
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// @Brief: Core measurement execution
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virtual void Run();
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// @Brief: Clean up and retrive the resource
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virtual void Close();
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// @Brief: Display results
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virtual void DisplayResults() const;
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// @Brief: Display information about what this test does
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virtual void DisplayTestInfo(void);
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private:
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void testEventsIndividually(uint32_t dv_ind);
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void testEventsSimultaneously(uint32_t dv_ind);
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};
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class PerfCntrEvtGrp {
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public:
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explicit PerfCntrEvtGrp(rsmi_event_group_t grp,
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uint32_t first, uint32_t last, std::string name);
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~PerfCntrEvtGrp();
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|
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rsmi_event_group_t group(void) const { return grp_;}
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uint32_t first_evt(void) const {return first_evt_;}
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uint32_t last_evt(void) const {return last_evt_;}
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uint32_t num_events(void) const {return num_events_;}
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std::string name(void) const { return name_;}
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private:
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rsmi_event_group_t grp_;
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uint32_t first_evt_;
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uint32_t last_evt_;
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uint32_t num_events_;
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std::string name_;
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};
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#endif // TESTS_ROCM_SMI_TEST_FUNCTIONAL_PERF_CNTR_READ_WRITE_H_
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@@ -72,6 +72,7 @@
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#include "functional/err_cnt_read.h"
|
||||
#include "functional/mem_util_read.h"
|
||||
#include "functional/id_info_read.h"
|
||||
#include "rocm_smi_test/functional/perf_cntr_read_write.h"
|
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|
||||
static RSMITstGlobals *sRSMIGlvalues = nullptr;
|
||||
|
||||
@@ -198,7 +199,10 @@ TEST(rsmitstReadOnly, TestIdInfoRead) {
|
||||
TestIdInfoRead tst;
|
||||
RunGenericTest(&tst);
|
||||
}
|
||||
|
||||
TEST(rsmitstreadWrite,TestPerfCntrReadWrite) {
|
||||
TestPerfCntrReadWrite tst;
|
||||
RunGenericTest(&tst);
|
||||
}
|
||||
int main(int argc, char** argv) {
|
||||
::testing::InitGoogleTest(&argc, argv);
|
||||
|
||||
|
||||
Reference in new issue
Block a user