SWDEV-434298 - Change copy buffer kernel
The new copy kernel can limit the number of launched workgoups. It can copy in chunks of 16 bytes or 4 bytes. Workgoup size is increased to 512 or 1024 Change-Id: Ic3fefa2d5bda6afebd1acc4d41ad310b138af6df
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@@ -911,7 +911,7 @@ bool KernelBlitManager::copyBufferToImage(device::Memory& srcMemory, device::Mem
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// Step 2. Initiate compute transfer with all staging buffers
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for (uint i = 0; i < MaxXferBuffers; ++i) {
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if (copySize > 0) {
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if (!copyBufferToImageKernel(*xferBuf[i], dstMemory, xferSrc, dst, xferRect, false,
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if (!copyBufferToImageKernel(*xferBuf[i], dstMemory, xferSrc, dst, xferRect, false,
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0UL, 0UL, copyMetadata)) {
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transfer = false;
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break;
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@@ -2276,74 +2276,57 @@ bool KernelBlitManager::copyBuffer(device::Memory& srcMemory, device::Memory& ds
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bool result = false;
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if (!gpuMem(srcMemory).isHostMemDirectAccess() && !gpuMem(dstMemory).isHostMemDirectAccess()) {
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uint blitType = BlitCopyBuffer;
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size_t dim = 1;
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size_t globalWorkOffset[3] = {0, 0, 0};
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size_t globalWorkSize = 0;
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size_t localWorkSize = 0;
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constexpr uint32_t kBlitType = BlitCopyBuffer;
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constexpr uint32_t kMaxAlignment = 2 * sizeof(uint64_t);
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amd::Coord3D size(sizeIn[0]);
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const static uint CopyBuffAlignment[3] = {16, 4, 1};
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amd::Coord3D size(sizeIn[0], sizeIn[1], sizeIn[2]);
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// Check alignments for source and destination
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bool aligned = ((srcOrigin[0] % kMaxAlignment) == 0) && ((dstOrigin[0] % kMaxAlignment) == 0);
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uint32_t aligned_size = (aligned) ? kMaxAlignment : sizeof(uint32_t);
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uint i;
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for (i = 0; i < sizeof(CopyBuffAlignment) / sizeof(uint); i++) {
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// Check source alignments
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bool aligned = ((srcOrigin[0] % CopyBuffAlignment[i]) == 0);
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// Check destination alignments
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aligned &= ((dstOrigin[0] % CopyBuffAlignment[i]) == 0);
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// Check copy size alignment in the first dimension
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aligned &= ((sizeIn[0] % CopyBuffAlignment[i]) == 0);
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if (aligned) {
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if (CopyBuffAlignment[i] != 1) {
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blitType = BlitCopyBufferAligned;
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}
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break;
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}
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}
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uint32_t remain;
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if (blitType == BlitCopyBufferAligned) {
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size.c[0] /= CopyBuffAlignment[i];
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} else {
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remain = size[0] % 4;
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size.c[0] /= 4;
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size.c[0] += 1;
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}
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// Setup copy size accordingly to the alignment
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uint32_t remainder = size[0] % aligned_size;
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size.c[0] /= aligned_size;
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size.c[0] += (remainder != 0) ? 1 : 0;
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// Program the dispatch dimensions
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localWorkSize = 256;
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globalWorkSize = amd::alignUp(size[0], 256);
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const size_t localWorkSize = (aligned) ? 512 : 1024;
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size_t globalWorkSize = std::min(dev().settings().limit_blit_wg_ * localWorkSize, size[0]);
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globalWorkSize = amd::alignUp(globalWorkSize, localWorkSize);
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// Program kernels arguments for the blit operation
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Memory* mem = &gpuMem(srcMemory);
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setArgument(kernels_[blitType], 0, sizeof(cl_mem), &mem);
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setArgument(kernels_[kBlitType], 0, sizeof(cl_mem), &mem);
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mem = &gpuMem(dstMemory);
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setArgument(kernels_[blitType], 1, sizeof(cl_mem), &mem);
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setArgument(kernels_[kBlitType], 1, sizeof(cl_mem), &mem);
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// Program source origin
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uint64_t srcOffset = srcOrigin[0] / CopyBuffAlignment[i];
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setArgument(kernels_[blitType], 2, sizeof(srcOffset), &srcOffset);
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uint64_t srcOffset = srcOrigin[0];
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setArgument(kernels_[kBlitType], 2, sizeof(srcOffset), &srcOffset);
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// Program destinaiton origin
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uint64_t dstOffset = dstOrigin[0] / CopyBuffAlignment[i];
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setArgument(kernels_[blitType], 3, sizeof(dstOffset), &dstOffset);
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uint64_t dstOffset = dstOrigin[0];
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setArgument(kernels_[kBlitType], 3, sizeof(dstOffset), &dstOffset);
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uint64_t copySize = size[0];
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setArgument(kernels_[blitType], 4, sizeof(copySize), ©Size);
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uint64_t copySize = sizeIn[0];
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setArgument(kernels_[kBlitType], 4, sizeof(copySize), ©Size);
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if (blitType == BlitCopyBufferAligned) {
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int32_t alignment = CopyBuffAlignment[i];
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setArgument(kernels_[blitType], 5, sizeof(alignment), &alignment);
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} else {
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setArgument(kernels_[blitType], 5, sizeof(remain), &remain);
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}
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setArgument(kernels_[kBlitType], 5, sizeof(remainder), &remainder);
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setArgument(kernels_[kBlitType], 6, sizeof(aligned_size), &aligned_size);
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// End pointer is the aligned copy size
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uint64_t end_ptr = dstMemory.virtualAddress() + sizeIn[0] - remainder;
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setArgument(kernels_[kBlitType], 7, sizeof(end_ptr), &end_ptr);
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uint32_t next_chunk = globalWorkSize;
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setArgument(kernels_[kBlitType], 8, sizeof(next_chunk), &next_chunk);
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// Create ND range object for the kernel's execution
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amd::NDRangeContainer ndrange(1, globalWorkOffset, &globalWorkSize, &localWorkSize);
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amd::NDRangeContainer ndrange(1, nullptr, &globalWorkSize, &localWorkSize);
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// Execute the blit
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address parameters = kernels_[blitType]->parameters().values();
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result = gpu().submitKernelInternal(ndrange, *kernels_[blitType], parameters);
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address parameters = kernels_[kBlitType]->parameters().values();
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result = gpu().submitKernelInternal(ndrange, *kernels_[kBlitType], parameters);
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} else {
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result = DmaBlitManager::copyBuffer(srcMemory, dstMemory, srcOrigin, dstOrigin, sizeIn, entire, copyMetadata);
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}
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@@ -2359,10 +2342,10 @@ bool KernelBlitManager::fillImage(device::Memory& memory, const void* pattern,
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amd::ScopedLock k(lockXferOps_);
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bool result = false;
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constexpr size_t kFillImageThreshold = 256 * 256;
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// Use host fill if memory has direct access and image is small
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if (setup_.disableFillImage_ ||
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(gpuMem(memory).isHostMemDirectAccess() &&
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(gpuMem(memory).isHostMemDirectAccess() &&
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(size.c[0] * size.c[1] * size.c[2]) <= kFillImageThreshold)) {
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gpu().releaseGpuMemoryFence();
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