RCCL 2.4 update
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@@ -1,5 +1,6 @@
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/*************************************************************************
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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* Modifications Copyright (c) 2019 Advanced Micro Devices, Inc. All rights reserved.
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*
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* See LICENSE.txt for license information
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************************************************************************/
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@@ -9,9 +10,10 @@
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#include "collectives.h"
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template<int UNROLL, class FUNC, typename T>
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__attribute__((noinline))
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__device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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const int tid = threadIdx.x;
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const int nthreads = blockDim.x - 1;
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const int nthreads = blockDim.x;
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const int bid = args->bid;
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struct ncclDevComm* comm = args->comm;
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struct ncclChannel* channel = comm->channels+blockIdx.x;
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@@ -21,6 +23,11 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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const int stepSize = channel->buffSize / (sizeof(T)*NCCL_STEPS);
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const int chunkSize = stepSize * ALLREDUCE_CHUNKSTEPS;
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const ssize_t loopSize = args->nChannels*(ssize_t)chunkSize;
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#ifdef ENABLE_PROFILING
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auto devProf = comm->devProf;
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uint64_t clk, t0 = 0ULL, ws, wr;
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if (tid == 0) clk = clock64();
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#endif
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// Compute pointers
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const T * __restrict__ thisInput = (const T*)args->ThisInput;
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@@ -44,7 +51,9 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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offset = chunkOffset + slice * realChunkSize;
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nelem = min(realChunkSize, size-offset);
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INIT_COUNTER;
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prims.send(thisInput+offset, nelem);
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ACCUMULATE_COUNTER(send);
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// k-2 steps: reduce and copy to next GPU
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for (int j=2; j<nranks; ++j) {
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@@ -52,7 +61,9 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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offset = chunkOffset + slice * realChunkSize;
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nelem = min(realChunkSize, size-offset);
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INIT_COUNTER;
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prims.recvReduceSend(thisInput+offset, nelem);
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ACCUMULATE_COUNTER(recvReduceSend);
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}
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// step k-1: reduce this buffer and data, which will produce the final
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@@ -61,7 +72,9 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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offset = chunkOffset + slice * realChunkSize;
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nelem = min(realChunkSize, size-offset);
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INIT_COUNTER;
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prims.directRecvReduceCopySend(thisInput+offset, thisOutput+offset, offset, nelem);
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ACCUMULATE_COUNTER(directRecvReduceCopySend);
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// k-2 steps: copy to next GPU
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for (int j=1; j<nranks-1; ++j) {
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@@ -69,7 +82,9 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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offset = chunkOffset + slice * realChunkSize;
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nelem = min(realChunkSize, size-offset);
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INIT_COUNTER;
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prims.directRecvCopySend(thisOutput+offset, offset, nelem);
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ACCUMULATE_COUNTER(directRecvCopySend);
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}
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// Make final copy from buffer to dest.
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@@ -78,14 +93,20 @@ __device__ void ncclAllReduceRingKernel(struct CollectiveArgs* args) {
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nelem = min(realChunkSize, size-offset);
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// Final wait/copy.
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INIT_COUNTER;
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prims.directRecv(thisOutput+offset, offset, nelem);
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ACCUMULATE_COUNTER(directRecv);
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}
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#ifdef ENABLE_PROFILING
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if (tid == 0) __atomic_fetch_add(&(devProf->total_cycle), clock64() - clk, __ATOMIC_SEQ_CST);
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#endif
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}
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template<int UNROLL, class FUNC, typename T>
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__attribute__((noinline))
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__device__ void ncclAllReduceTreeKernel(struct CollectiveArgs* args) {
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const int tid = threadIdx.x;
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const int nthreads = blockDim.x - 1;
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const int nthreads = blockDim.x;
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const int bid = args->bid;
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struct ncclDevComm* comm = args->comm;
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struct ncclChannel* channel = comm->channels+blockIdx.x;
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@@ -135,6 +156,7 @@ __device__ void ncclAllReduceTreeKernel(struct CollectiveArgs* args) {
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}
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template<int UNUSED, class FUNC, typename T>
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__attribute__((noinline))
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__device__ void ncclAllReduceRingLLKernel(struct CollectiveArgs* args) {
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const int tid = threadIdx.x;
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const int bid = args->bid;
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@@ -210,6 +232,7 @@ __device__ void ncclAllReduceRingLLKernel(struct CollectiveArgs* args) {
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}
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template<int UNUSED, class FUNC, typename T>
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__attribute__((noinline))
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__device__ void ncclAllReduceTreeLLKernel(struct CollectiveArgs* args) {
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const int tid = threadIdx.x;
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const int nthreads = args->nThreads;
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