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SWDEV-443760 - Enable device kern args

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- Implement workaround to ensure HDP writes are done by writing and
reading the HDP MMIO register.
- Implement the same workaround for graphs, we no longer need sentinel
write/readback

Change-Id: I0d3027b46a1f61131ec62e3c8c669ff5184fa6b2
This commit is contained in:
Saleel Kudchadker committed 2024-02-20 02:03:14 -05:00
1 parent 81b8598af9
commit f138e0d113
5 files changed
+21 -40
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rocclr/device/rocm/rocvirtual.cpp
+9 -14
View File
@@ -1376,8 +1376,9 @@ bool VirtualGPU::initPool(size_t kernarg_pool_size) {
kernarg_pool_size_ = kernarg_pool_size;
kernarg_pool_chunk_end_ = kernarg_pool_size_ / KernelArgPoolNumSignal;
active_chunk_ = 0;
if (HIP_FORCE_DEV_KERNARG && roc_device_.info().largeBar_) {
kernarg_pool_base_ = reinterpret_cast<address>(roc_device_.deviceLocalAlloc(kernarg_pool_size_));
if (dev().settings().device_kernel_args_ && roc_device_.info().largeBar_) {
kernarg_pool_base_ =
reinterpret_cast<address>(roc_device_.deviceLocalAlloc(kernarg_pool_size_));
} else {
kernarg_pool_base_ = reinterpret_cast<address>(roc_device_.hostAlloc(kernarg_pool_size_, 0,
Device::MemorySegment::kKernArg));
@@ -3208,8 +3209,7 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes,
}
}
constexpr uint64_t kSentinel = 0xdeadbeefdeadbeefull;
const auto pcieKernargs = !dev().isXgmi() && HIP_FORCE_DEV_KERNARG;
const auto pcieKernargs = !dev().isXgmi() && dev().settings().device_kernel_args_;
address argBuffer = hidden_arguments;
// Find all parameters for the current kernel
@@ -3218,8 +3218,7 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes,
if(vcmd != nullptr && vcmd->getCapturingState()) {
argBuffer = vcmd->getKernArgOffset();
} else {
const auto kernargSize = gpuKernel.KernargSegmentByteSize() +
sizeof(kSentinel) * pcieKernargs;
const auto kernargSize = gpuKernel.KernargSegmentByteSize();
argBuffer = reinterpret_cast<address>(allocKernArg(kernargSize,
gpuKernel.KernargSegmentAlignment()));
}
@@ -3228,11 +3227,7 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes,
std::min(gpuKernel.KernargSegmentByteSize(),
signature.paramsSize()));
if (pcieKernargs) {
nontemporalMemcpy(argBuffer + gpuKernel.KernargSegmentByteSize(),
&kSentinel, sizeof(kSentinel));
if (dev().settings().host_hdp_flush_) {
*dev().info().hdpMemFlushCntl = 1u;
}
*dev().info().hdpMemFlushCntl = 1u;
}
}
@@ -3295,9 +3290,9 @@ bool VirtualGPU::submitKernelInternal(const amd::NDRangeContainer& sizes,
aql_packet->setup = sizes.dimensions() << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS;
}
if (pcieKernargs) {
__builtin_ia32_mfence();
while (*reinterpret_cast<volatile decltype(kSentinel)*>(
argBuffer + gpuKernel.KernargSegmentByteSize()) != kSentinel);
if (*dev().info().hdpMemFlushCntl != UINT32_MAX) {
LogError("Unexpected HDP Register readback value!");
}
}
if (vcmd == nullptr) {
// Dispatch the packet