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SWDEV-502480 - Update documentation from GitHub 2024-12-05

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Change-Id: I179814351b77935aff55e8ae47dd322a3e15a868
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Istvan Kiss
2024-12-15 19:31:35 +01:00
parent 15e2512f02
commit f39c7a3150
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docs/understand/hardware_implementation.rst
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@@ -26,11 +26,10 @@ according to the :ref:`SIMT model<programming_model_simt>`, together with the
necessary registers and caches.
The threads are executed in groupings called warps. The amount of threads
making up a warp is architecture dependent.
On AMD GPUs the warp size is commonly 64 threads, except in RDNA
architectures which can utilize a warp size of 32 or 64 respectively.
The warp size of supported AMD GPUs is listed in the :doc:`rocm:reference/gpu-arch-specs`.
NVIDIA GPUs have a warp size of 32.
making up a warp is architecture dependent. On AMD GPUs the warp size is
commonly 64 threads, except in RDNA architectures which can utilize a warp size
of 32 or 64 respectively. The warp size of supported AMD GPUs is listed in the
:doc:`rocm:reference/gpu-arch-specs`. NVIDIA GPUs have a warp size of 32.
In contrast to CPUs, GPUs generally do not employ complex cache structures or
control logic, like branch prediction or out-of-order execution, but instead