2.16.5-1
Add support for 400Gbit NDR network adapters (CX7) Handle EINTR in socket poll() function Add NCCL_PROGRESS_APPENDOP_FREQ to control op append overhead Resource cleanup fixes Fix double free in case of init failure Fix crash in ncclCommAbort Revert AMD speed commit
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+10
-5
@@ -731,6 +731,11 @@ float speedArrayInter[] = { 48.0, 30.0, 28.0, 24.0, 22.0, 18.0, 15.0, 12.0, 10.0
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#define NSPEEDSINTRA (sizeof(speedArrayIntra)/sizeof(float))
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#define NSPEEDSINTER (sizeof(speedArrayInter)/sizeof(float))
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float sm90SpeedArrayIntra[] = { 66.0, 33.0, 24.0, 20.0, 15.0, 12.0, 6.0, 3.0 };
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float sm90SpeedArrayInter[] = { 48.0, 45.0, 30.0, 24.0, 15.0, 12.0, 6.0, 3.0, 2.4, 1.2, 0.24, 0.12 };
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#define NSPEEDSINTRA_SM90 (sizeof(sm90SpeedArrayIntra)/sizeof(float))
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#define NSPEEDSINTER_SM90 (sizeof(sm90SpeedArrayInter)/sizeof(float))
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NCCL_PARAM(CrossNic, "CROSS_NIC", 2);
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ncclResult_t ncclTopoCompute(ncclTopoSystem* system, struct ncclTopoGraph* graph) {
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@@ -771,11 +776,11 @@ ncclResult_t ncclTopoCompute(ncclTopoSystem* system, struct ncclTopoGraph* graph
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int nspeeds = 0;
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float* speedArray = NULL;
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if (system->nodes[NET].count == 0) {
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nspeeds = NSPEEDSINTRA;
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speedArray = speedArrayIntra;
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nspeeds = ccMin >= 90 ? NSPEEDSINTRA_SM90 : NSPEEDSINTRA;
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speedArray = ccMin >= 90 ? sm90SpeedArrayIntra : speedArrayIntra;
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} else {
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nspeeds = NSPEEDSINTER;
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speedArray = speedArrayInter;
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nspeeds = ccMin >= 90 ? NSPEEDSINTER_SM90 : NSPEEDSINTER;
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speedArray = ccMin >= 90 ? sm90SpeedArrayInter : speedArrayInter;
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}
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int pass = 1;
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int speedIndex = 0;
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@@ -890,7 +895,7 @@ done:
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graph->nChannels = 1;
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}
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if (graph->bwIntra >= 25.0) {
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if ((ccMin <= 80 && graph->bwIntra >= 25.0) || (ccMin <= 90 && graph->bwIntra >= 50.0)) {
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int dupChannels = std::min(graph->nChannels*2, graph->maxChannels);
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memcpy(graph->intra+graph->nChannels*ngpus, graph->intra, (dupChannels-graph->nChannels)*ngpus*sizeof(int));
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memcpy(graph->inter+graph->nChannels*2,graph->inter, (dupChannels-graph->nChannels)*2*sizeof(int));
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@@ -72,9 +72,6 @@ static ncclResult_t ncclTopoGetInterCpuBw(struct ncclTopoNode* cpu, float* bw) {
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if (cpu->cpu.arch == NCCL_TOPO_CPU_ARCH_X86 && cpu->cpu.vendor == NCCL_TOPO_CPU_VENDOR_INTEL) {
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*bw = cpu->cpu.model == NCCL_TOPO_CPU_TYPE_SKL ? SKL_QPI_BW : QPI_BW;
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}
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if (cpu->cpu.arch == NCCL_TOPO_CPU_ARCH_X86 && cpu->cpu.vendor == NCCL_TOPO_CPU_VENDOR_AMD) {
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*bw = AMD_BW;
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}
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if (cpu->cpu.arch == NCCL_TOPO_CPU_ARCH_X86 && cpu->cpu.vendor == NCCL_TOPO_CPU_VENDOR_ZHAOXIN) {
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*bw = cpu->cpu.model == NCCL_TOPO_CPU_TYPE_YONGFENG ? YONGFENG_ZPI_BW : ZPI_BW;
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}
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@@ -18,7 +18,6 @@
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#define PCI_BW 12.0 // PCI Gen3 x16
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#define QPI_BW 6.0
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#define SKL_QPI_BW 9.0
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#define AMD_BW 16.0
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#define ZPI_BW 6.0
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#define YONGFENG_ZPI_BW 9.0
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#define P9_BW 32.0
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