Move perfmon_configs dir into omniperf_soc dir. Rename config dirs for clarity

Signed-off-by: colramos-amd <colramos@amd.com>

src/omniperf_soc/profile_configs/gfx900/pmc_cpc_perf.txt

@@ -0,0 +1,15 @@
+pmc: GRBM_COUNT  GRBM_GUI_ACTIVE        SQ_CYCLES       SQ_BUSY_CYCLES      SQ_WAVES     
+
+pmc: CPC_CPC_STAT_BUSY      CPC_CPC_STAT_IDLE
+pmc: CPC_CPC_TCIU_BUSY      CPC_CPC_TCIU_IDLE
+pmc: CPC_CPC_STAT_STALL     CPC_UTCL1_STALL_ON_TRANSLATION                   
+pmc: CPC_CPC_UTCL2IU_BUSY    CPC_CPC_UTCL2IU_IDLE    
+pmc: CPC_CPC_UTCL2IU_STALL   CPC_ME1_BUSY_FOR_PACKET_DECODE  
+pmc: CPC_ME1_DC0_SPI_BUSY
+
+range:
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_cpf_perf.txt

@@ -0,0 +1,13 @@
+pmc: GRBM_COUNT                 GRBM_GUI_ACTIVE                 SQ_CYCLES                       SQ_BUSY_CYCLES                  SQ_WAVES         
+
+pmc: CPF_CPF_STAT_BUSY                          CPF_CPF_STAT_STALL
+pmc: CPF_CPF_TCIU_BUSY                          CPF_CPF_TCIU_STALL
+pmc: CPF_CPF_STAT_IDLE                          CPF_CPF_TCIU_IDLE
+pmc: CPF_CMP_UTCL1_STALL_ON_TRANSLATION          
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_spi_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT             GRBM_GUI_ACTIVE            SQ_CYCLES                   SQ_BUSY_CYCLES            SQ_WAVES                   GRBM_SPI_BUSY
+
+pmc: SPI_CSN_WINDOW_VALID   SPI_CSN_BUSY               SPI_CSN_NUM_THREADGROUPS    SPI_CSN_WAVE              SPI_RA_REQ_NO_ALLOC        SPI_RA_REQ_NO_ALLOC_CSN     
+pmc: SPI_RA_RES_STALL_CSN   SPI_RA_TMP_STALL_CSN       SPI_RA_WAVE_SIMD_FULL_CSN   SPI_RA_VGPR_SIMD_FULL_CSN SPI_RA_SGPR_SIMD_FULL_CSN  SPI_RA_LDS_CU_FULL_CSN 
+pmc: SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN   SPI_RA_WVLIM_STALL_CSN      SPI_SWC_CSC_WR            SPI_VWC_CSC_WR             SPI_RA_BULKY_CU_FULL_CSN
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf1.txt

@@ -0,0 +1,31 @@
+#SQ
+pmc: GRBM_COUNT                    GRBM_GUI_ACTIVE                                     SQ_INSTS_VMEM_WR        SQ_INSTS_VMEM_RD       SQ_INSTS_VMEM            SQ_INSTS_SALU              SQ_INSTS_VSKIPPED         
+pmc: SQ_INSTS_SMEM                 SQ_INSTS_FLAT               SQ_INSTS_LDS            SQ_INSTS_GDS            SQ_INSTS_EXP_GDS       SQ_INSTS_BRANCH          SQ_INSTS_SENDMSG           SQ_INSTS    
+pmc: SQ_WAVE_CYCLES                SQ_WAIT_ANY                 SQ_WAIT_INST_ANY        SQ_ACTIVE_INST_ANY      SQ_CYCLES              SQ_BUSY_CYCLES           SQ_BUSY_CU_CYCLES          SQ_INSTS_VALU
+pmc: SQ_ACTIVE_INST_VMEM           SQ_ACTIVE_INST_LDS          SQ_ACTIVE_INST_VALU     SQ_ACTIVE_INST_SCA      SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC      SQ_ACTIVE_INST_FLAT        SQ_INST_CYCLES_VMEM_WR
+pmc: SQ_INST_CYCLES_VMEM_RD        SQ_INST_CYCLES_SMEM         SQ_INST_CYCLES_SALU     SQ_THREAD_CYCLES_VALU   SQ_IFETCH              SQ_LDS_BANK_CONFLICT     SQ_LDS_ADDR_CONFLICT       SQ_LDS_UNALIGNED_STALL
+pmc: SQ_WAVES                      SQ_WAVES_EQ_64              SQ_WAVES_LT_64          SQ_WAVES_LT_48          SQ_WAVES_LT_32         SQ_WAVES_LT_16           SQ_ITEMS                   SQ_INSTS_VSKIPPED      
+pmc: SQ_LDS_MEM_VIOLATIONS         SQ_LDS_ATOMIC_RETURN        SQ_LDS_IDX_ACTIVE       SQ_WAVES_RESTORED       SQ_WAVES_SAVED         SQ_INSTS_SMEM_NORM                           
+
+
+#SQ:MI200
+#pmc: SQ_INSTS_MFMA              SQ_INSTS_VALU_MFMA_I8         SQ_INSTS_VALU_MFMA_F16      SQ_INSTS_VALU_MFMA_BF16       SQ_INSTS_VALU_MFMA_F32        SQ_INSTS_VALU_MFMA_F64        SQ_VALU_MFMA_BUSY_CYCLES    
+#pmc: SQ_INSTS_FLAT_LDS_ONLY     SQ_INSTS_VALU_MFMA_MOPS_I8    SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16  SQ_INSTS_VALU_MFMA_MOPS_F32   SQ_INSTS_VALU_MFMA_MOPS_F64  
+
+#SQC
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+
+
+########################################
+# Filtering
+########################################
+range: 
+gpu: 
+kernel: 
+
+
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf2.txt

@@ -0,0 +1,12 @@
+#################################################
+# VMEM latency
+#################################################
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf3.txt

@@ -0,0 +1,13 @@
+#################################################
+# SMEM latency
+#################################################
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf4.txt

@@ -0,0 +1,11 @@
+#################################################
+# ifetch latency
+#################################################
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+kernel: 
+
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf6.txt

@@ -0,0 +1,15 @@
+#################################################
+# LDS latency
+#################################################
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+
+kernel: 
+
+
+
+
+
+

src/omniperf_soc/profile_configs/gfx900/pmc_sq_perf8.txt

@@ -0,0 +1,7 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES 
+
+gpu: 
+range: 
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx900/pmc_sqc_perf1.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+range: 
+gpu:  
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx900/pmc_ta_perf.txt

@@ -0,0 +1,37 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES 
+
+pmc: TA_TA_BUSY_sum                      TA_SH_FIFO_BUSY_sum                 
+pmc: TA_SH_FIFO_CMD_BUSY_sum             TA_SH_FIFO_ADDR_BUSY_sum            
+pmc: TA_SH_FIFO_DATA_BUSY_sum            TA_SH_FIFO_DATA_SFIFO_BUSY_sum      
+pmc: TA_SH_FIFO_DATA_TFIFO_BUSY_sum      TA_SQ_TA_CMD_CYCLES_sum             
+pmc: TA_SP_TA_ADDR_CYCLES_sum            TA_SP_TA_DATA_CYCLES_sum 
+
+
+# Starvation
+pmc: TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum          TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum
+pmc: TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum          TA_TA_SH_FIFO_STARVED_sum
+
+
+
+# buffer access
+pmc: TA_BUFFER_WAVEFRONTS_sum                   TA_BUFFER_READ_WAVEFRONTS_sum
+pmc: TA_BUFFER_WRITE_WAVEFRONTS_sum             TA_BUFFER_ATOMIC_WAVEFRONTS_sum
+pmc: TA_BUFFER_TOTAL_CYCLES_sum                 TA_BUFFER_COALESCABLE_WAVEFRONTS_sum
+pmc: TA_BUFFER_COALESCED_READ_CYCLES_sum        TA_BUFFER_COALESCED_WRITE_CYCLES_sum
+
+
+# stalls
+pmc: TA_ADDR_STALLED_BY_TC_CYCLES_sum    TA_TOTAL_WAVEFRONTS_sum
+pmc: TA_ADDR_STALLED_BY_TD_CYCLES_sum    TA_DATA_STALLED_BY_TC_CYCLES_sum    
+
+# flat accesses
+pmc: TA_FLAT_WAVEFRONTS_sum              TA_FLAT_READ_WAVEFRONTS_sum         
+pmc: TA_FLAT_WRITE_WAVEFRONTS_sum        TA_FLAT_ATOMIC_WAVEFRONTS_sum       
+pmc: TA_FLAT_COALESCEABLE_WAVEFRONTS_sum 
+
+
+range: 
+
+gpu:
+
+kernel: 

src/omniperf_soc/profile_configs/gfx900/pmc_tcc2_perf.txt

@@ -0,0 +1,26 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_WAVES
+
+# MI50: no TCC_RW_REQ
+pmc: TCC_CYCLE[0]           TCC_HIT[0]                  TCC_MISS[0]  TCC_CYCLE[1]                   TCC_HIT[1]                  TCC_MISS[1]  TCC_CYCLE[2]                   TCC_HIT[2]                  TCC_MISS[2]  TCC_CYCLE[3]                TCC_HIT[3]                  TCC_MISS[3]  TCC_CYCLE[4]                   TCC_HIT[4]                  TCC_MISS[4]  TCC_CYCLE[5]                   TCC_HIT[5]                  TCC_MISS[5]  TCC_CYCLE[6]                   TCC_HIT[6]                  TCC_MISS[6]  TCC_CYCLE[7]   TCC_HIT[7]                  TCC_MISS[7]  TCC_CYCLE[8]                   TCC_HIT[8]                  TCC_MISS[8]  TCC_CYCLE[9]                   TCC_HIT[9]                  TCC_MISS[9]  TCC_CYCLE[10]                  TCC_HIT[10]                 TCC_MISS[10] TCC_CYCLE[11]                  TCC_HIT[11]                 TCC_MISS[11] TCC_CYCLE[12]                  TCC_HIT[12]                 TCC_MISS[12] TCC_CYCLE[13]                  TCC_HIT[13]                 TCC_MISS[13] TCC_CYCLE[14]                  TCC_HIT[14]                 TCC_MISS[14] TCC_CYCLE[15]                  TCC_HIT[15]                 TCC_MISS[15] 
+
+
+
+pmc: TCC_REQ[0]                     TCC_READ[0]                 TCC_WRITE[0]                TCC_ATOMIC[0]   TCC_REQ[1]                     TCC_READ[1]                 TCC_WRITE[1]                TCC_ATOMIC[1]   TCC_REQ[2]                     TCC_READ[2]                 TCC_WRITE[2]                TCC_ATOMIC[2]   TCC_REQ[3]                     TCC_READ[3]                 TCC_WRITE[3]                TCC_ATOMIC[3]   TCC_REQ[4]                     TCC_READ[4]                 TCC_WRITE[4]                TCC_ATOMIC[4]   TCC_REQ[5]                     TCC_READ[5]                 TCC_WRITE[5]                TCC_ATOMIC[5]   TCC_REQ[6]                     TCC_READ[6]                 TCC_WRITE[6]                TCC_ATOMIC[6]   TCC_REQ[7]                     TCC_READ[7]                 TCC_WRITE[7]                TCC_ATOMIC[7]   TCC_REQ[8]                     TCC_READ[8]                 TCC_WRITE[8]                TCC_ATOMIC[8]   TCC_REQ[9]                     TCC_READ[9]                 TCC_WRITE[9]                TCC_ATOMIC[9]   TCC_REQ[10]                    TCC_READ[10]                TCC_WRITE[10]               TCC_ATOMIC[10]  TCC_REQ[11]                    TCC_READ[11]                TCC_WRITE[11]               TCC_ATOMIC[11]  TCC_REQ[12]                    TCC_READ[12]                TCC_WRITE[12]               TCC_ATOMIC[12]  TCC_REQ[13]                    TCC_READ[13]                TCC_WRITE[13]               TCC_ATOMIC[13]  TCC_REQ[14]                    TCC_READ[14]                TCC_WRITE[14]               TCC_ATOMIC[14]  TCC_REQ[15]                    TCC_READ[15]                TCC_WRITE[15]               TCC_ATOMIC[15]  
+
+
+
+pmc: TCC_EA_RDREQ[0]                TCC_EA_RDREQ_32B[0]         TCC_EA_WRREQ[0]             TCC_EA_WRREQ_64B[0]   TCC_EA_RDREQ[1]                TCC_EA_RDREQ_32B[1]         TCC_EA_WRREQ[1]             TCC_EA_WRREQ_64B[1]   TCC_EA_RDREQ[2]                TCC_EA_RDREQ_32B[2]         TCC_EA_WRREQ[2]             TCC_EA_WRREQ_64B[2]   TCC_EA_RDREQ[3]                TCC_EA_RDREQ_32B[3]         TCC_EA_WRREQ[3]             TCC_EA_WRREQ_64B[3]   TCC_EA_RDREQ[4]                TCC_EA_RDREQ_32B[4]         TCC_EA_WRREQ[4]             TCC_EA_WRREQ_64B[4]   TCC_EA_RDREQ[5]                TCC_EA_RDREQ_32B[5]         TCC_EA_WRREQ[5]             TCC_EA_WRREQ_64B[5]   TCC_EA_RDREQ[6]                TCC_EA_RDREQ_32B[6]         TCC_EA_WRREQ[6]             TCC_EA_WRREQ_64B[6]   TCC_EA_RDREQ[7]                TCC_EA_RDREQ_32B[7]         TCC_EA_WRREQ[7]             TCC_EA_WRREQ_64B[7]   TCC_EA_RDREQ[8]                TCC_EA_RDREQ_32B[8]         TCC_EA_WRREQ[8]             TCC_EA_WRREQ_64B[8]   TCC_EA_RDREQ[9]                TCC_EA_RDREQ_32B[9]         TCC_EA_WRREQ[9]             TCC_EA_WRREQ_64B[9]   TCC_EA_RDREQ[10]               TCC_EA_RDREQ_32B[10]        TCC_EA_WRREQ[10]            TCC_EA_WRREQ_64B[10]  TCC_EA_RDREQ[11]               TCC_EA_RDREQ_32B[11]        TCC_EA_WRREQ[11]            TCC_EA_WRREQ_64B[11]  TCC_EA_RDREQ[12]               TCC_EA_RDREQ_32B[12]        TCC_EA_WRREQ[12]            TCC_EA_WRREQ_64B[12]  TCC_EA_RDREQ[13]               TCC_EA_RDREQ_32B[13]        TCC_EA_WRREQ[13]            TCC_EA_WRREQ_64B[13]  TCC_EA_RDREQ[14]               TCC_EA_RDREQ_32B[14]        TCC_EA_WRREQ[14]            TCC_EA_WRREQ_64B[14]  TCC_EA_RDREQ[15]               TCC_EA_RDREQ_32B[15]        TCC_EA_WRREQ[15]            TCC_EA_WRREQ_64B[15]  
+
+
+pmc: TCC_EA_ATOMIC[0]               TCC_EA_RDREQ_LEVEL[0]       TCC_EA_WRREQ_LEVEL[0]       TCC_EA_ATOMIC_LEVEL[0]  TCC_EA_ATOMIC[1]               TCC_EA_RDREQ_LEVEL[1]       TCC_EA_WRREQ_LEVEL[1]       TCC_EA_ATOMIC_LEVEL[1]  TCC_EA_ATOMIC[2]               TCC_EA_RDREQ_LEVEL[2]       TCC_EA_WRREQ_LEVEL[2]       TCC_EA_ATOMIC_LEVEL[2]  TCC_EA_ATOMIC[3]               TCC_EA_RDREQ_LEVEL[3]       TCC_EA_WRREQ_LEVEL[3]       TCC_EA_ATOMIC_LEVEL[3]  TCC_EA_ATOMIC[4]               TCC_EA_RDREQ_LEVEL[4]       TCC_EA_WRREQ_LEVEL[4]       TCC_EA_ATOMIC_LEVEL[4]  TCC_EA_ATOMIC[5]               TCC_EA_RDREQ_LEVEL[5]       TCC_EA_WRREQ_LEVEL[5]       TCC_EA_ATOMIC_LEVEL[5]  TCC_EA_ATOMIC[6]               TCC_EA_RDREQ_LEVEL[6]       TCC_EA_WRREQ_LEVEL[6]       TCC_EA_ATOMIC_LEVEL[6]  TCC_EA_ATOMIC[7]               TCC_EA_RDREQ_LEVEL[7]       TCC_EA_WRREQ_LEVEL[7]       TCC_EA_ATOMIC_LEVEL[7]  TCC_EA_ATOMIC[8]               TCC_EA_RDREQ_LEVEL[8]       TCC_EA_WRREQ_LEVEL[8]       TCC_EA_ATOMIC_LEVEL[8]  TCC_EA_ATOMIC[9]               TCC_EA_RDREQ_LEVEL[9]       TCC_EA_WRREQ_LEVEL[9]       TCC_EA_ATOMIC_LEVEL[9]  TCC_EA_ATOMIC[10]              TCC_EA_RDREQ_LEVEL[10]      TCC_EA_WRREQ_LEVEL[10]      TCC_EA_ATOMIC_LEVEL[10] TCC_EA_ATOMIC[11]              TCC_EA_RDREQ_LEVEL[11]      TCC_EA_WRREQ_LEVEL[11]      TCC_EA_ATOMIC_LEVEL[11] TCC_EA_ATOMIC[12]              TCC_EA_RDREQ_LEVEL[12]      TCC_EA_WRREQ_LEVEL[12]      TCC_EA_ATOMIC_LEVEL[12] TCC_EA_ATOMIC[13]              TCC_EA_RDREQ_LEVEL[13]      TCC_EA_WRREQ_LEVEL[13]      TCC_EA_ATOMIC_LEVEL[13] TCC_EA_ATOMIC[14]              TCC_EA_RDREQ_LEVEL[14]      TCC_EA_WRREQ_LEVEL[14]      TCC_EA_ATOMIC_LEVEL[14] TCC_EA_ATOMIC[15]              TCC_EA_RDREQ_LEVEL[15]      TCC_EA_WRREQ_LEVEL[15]      TCC_EA_ATOMIC_LEVEL[15] 
+
+
+pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0]   TCC_EA_RDREQ_GMI_CREDIT_STALL[0]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]  TCC_EA_RDREQ_IO_CREDIT_STALL[1]   TCC_EA_RDREQ_GMI_CREDIT_STALL[1]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]  TCC_EA_RDREQ_IO_CREDIT_STALL[2]   TCC_EA_RDREQ_GMI_CREDIT_STALL[2]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]  TCC_EA_RDREQ_IO_CREDIT_STALL[3]   TCC_EA_RDREQ_GMI_CREDIT_STALL[3]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]  TCC_EA_RDREQ_IO_CREDIT_STALL[4]   TCC_EA_RDREQ_GMI_CREDIT_STALL[4]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]  TCC_EA_RDREQ_IO_CREDIT_STALL[5]   TCC_EA_RDREQ_GMI_CREDIT_STALL[5]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]  TCC_EA_RDREQ_IO_CREDIT_STALL[6]   TCC_EA_RDREQ_GMI_CREDIT_STALL[6]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]  TCC_EA_RDREQ_IO_CREDIT_STALL[7]   TCC_EA_RDREQ_GMI_CREDIT_STALL[7]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]  TCC_EA_RDREQ_IO_CREDIT_STALL[8]   TCC_EA_RDREQ_GMI_CREDIT_STALL[8]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]  TCC_EA_RDREQ_IO_CREDIT_STALL[9]   TCC_EA_RDREQ_GMI_CREDIT_STALL[9]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]  TCC_EA_RDREQ_IO_CREDIT_STALL[10]  TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11]  TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12]  TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13]  TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14]  TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15]  TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] 
+
+
+pmc: TCC_EA_WRREQ_IO_CREDIT_STALL[0]   TCC_EA_WRREQ_GMI_CREDIT_STALL[0]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]  TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[1]   TCC_EA_WRREQ_GMI_CREDIT_STALL[1]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]  TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[2]   TCC_EA_WRREQ_GMI_CREDIT_STALL[2]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]  TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[3]   TCC_EA_WRREQ_GMI_CREDIT_STALL[3]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]  TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[4]   TCC_EA_WRREQ_GMI_CREDIT_STALL[4]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]  TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[5]   TCC_EA_WRREQ_GMI_CREDIT_STALL[5]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]  TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[6]   TCC_EA_WRREQ_GMI_CREDIT_STALL[6]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]  TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[7]   TCC_EA_WRREQ_GMI_CREDIT_STALL[7]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]  TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[8]   TCC_EA_WRREQ_GMI_CREDIT_STALL[8]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]  TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[9]   TCC_EA_WRREQ_GMI_CREDIT_STALL[9]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]  TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[10]  TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[11]  TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[12]  TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[13]  TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[14]  TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[15]  TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] 
+
+gpu: 
+kernel: 
+range: 
+

src/omniperf_soc/profile_configs/gfx900/pmc_tcc_perf.txt

@@ -0,0 +1,19 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_WAVES 
+
+pmc: TCC_CYCLE_sum                          TCC_BUSY_sum                          TCC_PROBE_sum                          TCC_PROBE_ALL_sum 
+pmc: TCC_NC_REQ_sum                         TCC_UC_REQ_sum                        TCC_CC_REQ_sum                         
+pmc: TCC_REQ_sum                            TCC_STREAMING_REQ_sum                 TCC_HIT_sum                            TCC_MISS_sum
+pmc: TCC_READ_sum                           TCC_WRITE_sum                         TCC_ATOMIC_sum                         TCC_WRITEBACK_sum
+pmc: TCC_EA_WRREQ_sum                       TCC_EA_WRREQ_64B_sum                  TCC_EA_WR_UNCACHED_32B_sum 
+pmc: TCC_EA_WRREQ_STALL_sum                 TCC_EA_WRREQ_IO_CREDIT_STALL_sum      TCC_EA_WRREQ_GMI_CREDIT_STALL_sum      TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
+pmc: TCC_TOO_MANY_EA_WRREQS_STALL_sum       TCC_EA_ATOMIC_sum                     TCC_EA_RDREQ_sum                       TCC_EA_RDREQ_32B_sum
+pmc: TCC_EA_RD_UNCACHED_32B_sum             TCC_EA_RDREQ_IO_CREDIT_STALL_sum      TCC_EA_RDREQ_GMI_CREDIT_STALL_sum      TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum
+pmc:                                        TCC_NORMAL_WRITEBACK_sum              TCC_ALL_TC_OP_WB_WRITEBACK_sum         TCC_NORMAL_EVICT_sum
+pmc: TCC_ALL_TC_OP_INV_EVICT_sum            TCC_EA_RDREQ_DRAM_sum                 TCC_EA_WRREQ_DRAM_sum                    
+pmc: TCC_EA_RDREQ_LEVEL_sum                 TCC_EA_WRREQ_LEVEL_sum                TCC_EA_ATOMIC_LEVEL_sum
+
+gpu: 
+kernel: 
+
+range: 
+

src/omniperf_soc/profile_configs/gfx900/pmc_tcp_perf.txt

@@ -0,0 +1,18 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_BUSY_CU_CYCLES       SQ_WAVES        SQ_WAVE_CYCLES
+
+pmc: TCP_GATE_EN1_sum                        TCP_GATE_EN2_sum                        TCP_TD_TCP_STALL_CYCLES_sum                     TCP_TCR_TCP_STALL_CYCLES_sum
+pmc: TCP_READ_TAGCONFLICT_STALL_CYCLES_sum   TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum  TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum         TCP_TA_TCP_STATE_READ_sum
+pmc: TCP_VOLATILE_sum                        TCP_TOTAL_ACCESSES_sum                  TCP_TOTAL_READ_sum                              TCP_TOTAL_WRITE_sum
+pmc: TCP_TOTAL_ATOMIC_WITH_RET_sum           TCP_TOTAL_ATOMIC_WITHOUT_RET_sum        TCP_TOTAL_WRITEBACK_INVALIDATES_sum             TCP_TOTAL_CACHE_ACCESSES_sum
+pmc: TCP_UTCL1_TRANSLATION_MISS_sum          TCP_UTCL1_TRANSLATION_HIT_sum           TCP_UTCL1_PERMISSION_MISS_sum                   TCP_UTCL1_REQUEST_sum
+pmc: TCP_TCP_LATENCY_sum                     TCP_TCC_READ_REQ_LATENCY_sum            TCP_TCC_WRITE_REQ_LATENCY_sum                   TCP_TCC_READ_REQ_sum
+pmc: TCP_TCC_WRITE_REQ_sum                   TCP_TCC_ATOMIC_WITH_RET_REQ_sum         TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum              TCP_TCC_NC_READ_REQ_sum
+pmc: TCP_TCC_NC_WRITE_REQ_sum                TCP_TCC_NC_ATOMIC_REQ_sum               TCP_TCC_UC_READ_REQ_sum                         TCP_TCC_UC_WRITE_REQ_sum
+pmc: TCP_TCC_UC_ATOMIC_REQ_sum               TCP_TCC_CC_READ_REQ_sum                 TCP_TCC_CC_WRITE_REQ_sum                        TCP_TCC_CC_ATOMIC_REQ_sum
+pmc:       				                								  	     TCP_PENDING_STALL_CYCLES_sum
+
+#pmc: TCA_CYCLE_sum                           TCA_BUSY_sum
+
+gpu: 
+kernel: 
+range: 

src/omniperf_soc/profile_configs/gfx900/pmc_td_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+pmc: TD_TD_BUSY_sum                          TD_TC_STALL_sum
+pmc: TD_COALESCABLE_WAVEFRONT_sum            TD_LOAD_WAVEFRONT_sum
+pmc: TD_ATOMIC_WAVEFRONT_sum                 TD_STORE_WAVEFRONT_sum
+
+
+
+gpu:
+range: 
+kernel: 
+

src/omniperf_soc/profile_configs/gfx906/pmc_cpc_perf.txt

@@ -0,0 +1,15 @@
+pmc: GRBM_COUNT  GRBM_GUI_ACTIVE        SQ_CYCLES       SQ_BUSY_CYCLES      SQ_WAVES     
+
+pmc: CPC_CPC_STAT_BUSY      CPC_CPC_STAT_IDLE
+pmc: CPC_CPC_TCIU_BUSY      CPC_CPC_TCIU_IDLE
+pmc: CPC_CPC_STAT_STALL     CPC_UTCL1_STALL_ON_TRANSLATION                   
+pmc: CPC_CPC_UTCL2IU_BUSY    CPC_CPC_UTCL2IU_IDLE    
+pmc: CPC_CPC_UTCL2IU_STALL   CPC_ME1_BUSY_FOR_PACKET_DECODE  
+pmc: CPC_ME1_DC0_SPI_BUSY
+
+range:
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_cpf_perf.txt

@@ -0,0 +1,13 @@
+pmc: GRBM_COUNT                 GRBM_GUI_ACTIVE                 SQ_CYCLES                       SQ_BUSY_CYCLES                  SQ_WAVES         
+
+pmc: CPF_CPF_STAT_BUSY                          CPF_CPF_STAT_STALL
+pmc: CPF_CPF_TCIU_BUSY                          CPF_CPF_TCIU_STALL
+pmc: CPF_CPF_STAT_IDLE                          CPF_CPF_TCIU_IDLE
+pmc: CPF_CMP_UTCL1_STALL_ON_TRANSLATION          
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_spi_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT             GRBM_GUI_ACTIVE            SQ_CYCLES                   SQ_BUSY_CYCLES            SQ_WAVES                   GRBM_SPI_BUSY
+
+pmc: SPI_CSN_WINDOW_VALID   SPI_CSN_BUSY               SPI_CSN_NUM_THREADGROUPS    SPI_CSN_WAVE              SPI_RA_REQ_NO_ALLOC        SPI_RA_REQ_NO_ALLOC_CSN     
+pmc: SPI_RA_RES_STALL_CSN   SPI_RA_TMP_STALL_CSN       SPI_RA_WAVE_SIMD_FULL_CSN   SPI_RA_VGPR_SIMD_FULL_CSN SPI_RA_SGPR_SIMD_FULL_CSN  SPI_RA_LDS_CU_FULL_CSN 
+pmc: SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN   SPI_RA_WVLIM_STALL_CSN      SPI_SWC_CSC_WR            SPI_VWC_CSC_WR             SPI_RA_BULKY_CU_FULL_CSN
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf1.txt

@@ -0,0 +1,31 @@
+#SQ
+pmc: GRBM_COUNT                    GRBM_GUI_ACTIVE                                     SQ_INSTS_VMEM_WR        SQ_INSTS_VMEM_RD       SQ_INSTS_VMEM            SQ_INSTS_SALU              SQ_INSTS_VSKIPPED         
+pmc: SQ_INSTS_SMEM                 SQ_INSTS_FLAT               SQ_INSTS_LDS            SQ_INSTS_GDS            SQ_INSTS_EXP_GDS       SQ_INSTS_BRANCH          SQ_INSTS_SENDMSG           SQ_INSTS    
+pmc: SQ_WAVE_CYCLES                SQ_WAIT_ANY                 SQ_WAIT_INST_ANY        SQ_ACTIVE_INST_ANY      SQ_CYCLES              SQ_BUSY_CYCLES           SQ_BUSY_CU_CYCLES          SQ_INSTS_VALU
+pmc: SQ_ACTIVE_INST_VMEM           SQ_ACTIVE_INST_LDS          SQ_ACTIVE_INST_VALU     SQ_ACTIVE_INST_SCA      SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC      SQ_ACTIVE_INST_FLAT        SQ_INST_CYCLES_VMEM_WR
+pmc: SQ_INST_CYCLES_VMEM_RD        SQ_INST_CYCLES_SMEM         SQ_INST_CYCLES_SALU     SQ_THREAD_CYCLES_VALU   SQ_IFETCH              SQ_LDS_BANK_CONFLICT     SQ_LDS_ADDR_CONFLICT       SQ_LDS_UNALIGNED_STALL
+pmc: SQ_WAVES                      SQ_WAVES_EQ_64              SQ_WAVES_LT_64          SQ_WAVES_LT_48          SQ_WAVES_LT_32         SQ_WAVES_LT_16           SQ_ITEMS                   SQ_INSTS_VSKIPPED      
+pmc: SQ_LDS_MEM_VIOLATIONS         SQ_LDS_ATOMIC_RETURN        SQ_LDS_IDX_ACTIVE       SQ_WAVES_RESTORED       SQ_WAVES_SAVED         SQ_INSTS_SMEM_NORM                           
+
+
+#SQ:MI200
+#pmc: SQ_INSTS_MFMA              SQ_INSTS_VALU_MFMA_I8         SQ_INSTS_VALU_MFMA_F16      SQ_INSTS_VALU_MFMA_BF16       SQ_INSTS_VALU_MFMA_F32        SQ_INSTS_VALU_MFMA_F64        SQ_VALU_MFMA_BUSY_CYCLES    
+#pmc: SQ_INSTS_FLAT_LDS_ONLY     SQ_INSTS_VALU_MFMA_MOPS_I8    SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16  SQ_INSTS_VALU_MFMA_MOPS_F32   SQ_INSTS_VALU_MFMA_MOPS_F64  
+
+#SQC
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+
+
+########################################
+# Filtering
+########################################
+range: 
+gpu: 
+kernel: 
+
+
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf2.txt

@@ -0,0 +1,12 @@
+#################################################
+# VMEM latency
+#################################################
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf3.txt

@@ -0,0 +1,13 @@
+#################################################
+# SMEM latency
+#################################################
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf4.txt

@@ -0,0 +1,11 @@
+#################################################
+# ifetch latency
+#################################################
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+kernel: 
+
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf6.txt

@@ -0,0 +1,15 @@
+#################################################
+# LDS latency
+#################################################
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+
+kernel: 
+
+
+
+
+
+

src/omniperf_soc/profile_configs/gfx906/pmc_sq_perf8.txt

@@ -0,0 +1,7 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES 
+
+gpu: 
+range: 
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx906/pmc_sqc_perf1.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+range: 
+gpu:  
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx906/pmc_ta_perf.txt

@@ -0,0 +1,25 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES 
+
+pmc: TA_TA_BUSY_sum                     
+
+# buffer access
+pmc: TA_BUFFER_WAVEFRONTS_sum                   TA_BUFFER_READ_WAVEFRONTS_sum
+pmc: TA_BUFFER_WRITE_WAVEFRONTS_sum             TA_BUFFER_ATOMIC_WAVEFRONTS_sum
+pmc: TA_BUFFER_TOTAL_CYCLES_sum                 
+pmc: TA_BUFFER_COALESCED_READ_CYCLES_sum        TA_BUFFER_COALESCED_WRITE_CYCLES_sum
+
+
+# stalls
+pmc: TA_ADDR_STALLED_BY_TC_CYCLES_sum    TA_TOTAL_WAVEFRONTS_sum
+pmc: TA_ADDR_STALLED_BY_TD_CYCLES_sum    TA_DATA_STALLED_BY_TC_CYCLES_sum    
+
+# flat accesses
+pmc: TA_FLAT_WAVEFRONTS_sum              TA_FLAT_READ_WAVEFRONTS_sum         
+pmc: TA_FLAT_WRITE_WAVEFRONTS_sum        TA_FLAT_ATOMIC_WAVEFRONTS_sum 
+
+
+range: 
+
+gpu:
+
+kernel: 

src/omniperf_soc/profile_configs/gfx906/pmc_tcc2_perf.txt

@@ -0,0 +1,26 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_WAVES
+
+# MI50: no TCC_RW_REQ
+pmc: TCC_CYCLE[0]           TCC_HIT[0]                  TCC_MISS[0]  TCC_CYCLE[1]                   TCC_HIT[1]                  TCC_MISS[1]  TCC_CYCLE[2]                   TCC_HIT[2]                  TCC_MISS[2]  TCC_CYCLE[3]                TCC_HIT[3]                  TCC_MISS[3]  TCC_CYCLE[4]                   TCC_HIT[4]                  TCC_MISS[4]  TCC_CYCLE[5]                   TCC_HIT[5]                  TCC_MISS[5]  TCC_CYCLE[6]                   TCC_HIT[6]                  TCC_MISS[6]  TCC_CYCLE[7]   TCC_HIT[7]                  TCC_MISS[7]  TCC_CYCLE[8]                   TCC_HIT[8]                  TCC_MISS[8]  TCC_CYCLE[9]                   TCC_HIT[9]                  TCC_MISS[9]  TCC_CYCLE[10]                  TCC_HIT[10]                 TCC_MISS[10] TCC_CYCLE[11]                  TCC_HIT[11]                 TCC_MISS[11] TCC_CYCLE[12]                  TCC_HIT[12]                 TCC_MISS[12] TCC_CYCLE[13]                  TCC_HIT[13]                 TCC_MISS[13] TCC_CYCLE[14]                  TCC_HIT[14]                 TCC_MISS[14] TCC_CYCLE[15]                  TCC_HIT[15]                 TCC_MISS[15] 
+
+
+
+pmc: TCC_REQ[0]                     TCC_READ[0]                 TCC_WRITE[0]                TCC_ATOMIC[0]   TCC_REQ[1]                     TCC_READ[1]                 TCC_WRITE[1]                TCC_ATOMIC[1]   TCC_REQ[2]                     TCC_READ[2]                 TCC_WRITE[2]                TCC_ATOMIC[2]   TCC_REQ[3]                     TCC_READ[3]                 TCC_WRITE[3]                TCC_ATOMIC[3]   TCC_REQ[4]                     TCC_READ[4]                 TCC_WRITE[4]                TCC_ATOMIC[4]   TCC_REQ[5]                     TCC_READ[5]                 TCC_WRITE[5]                TCC_ATOMIC[5]   TCC_REQ[6]                     TCC_READ[6]                 TCC_WRITE[6]                TCC_ATOMIC[6]   TCC_REQ[7]                     TCC_READ[7]                 TCC_WRITE[7]                TCC_ATOMIC[7]   TCC_REQ[8]                     TCC_READ[8]                 TCC_WRITE[8]                TCC_ATOMIC[8]   TCC_REQ[9]                     TCC_READ[9]                 TCC_WRITE[9]                TCC_ATOMIC[9]   TCC_REQ[10]                    TCC_READ[10]                TCC_WRITE[10]               TCC_ATOMIC[10]  TCC_REQ[11]                    TCC_READ[11]                TCC_WRITE[11]               TCC_ATOMIC[11]  TCC_REQ[12]                    TCC_READ[12]                TCC_WRITE[12]               TCC_ATOMIC[12]  TCC_REQ[13]                    TCC_READ[13]                TCC_WRITE[13]               TCC_ATOMIC[13]  TCC_REQ[14]                    TCC_READ[14]                TCC_WRITE[14]               TCC_ATOMIC[14]  TCC_REQ[15]                    TCC_READ[15]                TCC_WRITE[15]               TCC_ATOMIC[15]  
+
+
+
+pmc: TCC_EA_RDREQ[0]                TCC_EA_RDREQ_32B[0]         TCC_EA_WRREQ[0]             TCC_EA_WRREQ_64B[0]   TCC_EA_RDREQ[1]                TCC_EA_RDREQ_32B[1]         TCC_EA_WRREQ[1]             TCC_EA_WRREQ_64B[1]   TCC_EA_RDREQ[2]                TCC_EA_RDREQ_32B[2]         TCC_EA_WRREQ[2]             TCC_EA_WRREQ_64B[2]   TCC_EA_RDREQ[3]                TCC_EA_RDREQ_32B[3]         TCC_EA_WRREQ[3]             TCC_EA_WRREQ_64B[3]   TCC_EA_RDREQ[4]                TCC_EA_RDREQ_32B[4]         TCC_EA_WRREQ[4]             TCC_EA_WRREQ_64B[4]   TCC_EA_RDREQ[5]                TCC_EA_RDREQ_32B[5]         TCC_EA_WRREQ[5]             TCC_EA_WRREQ_64B[5]   TCC_EA_RDREQ[6]                TCC_EA_RDREQ_32B[6]         TCC_EA_WRREQ[6]             TCC_EA_WRREQ_64B[6]   TCC_EA_RDREQ[7]                TCC_EA_RDREQ_32B[7]         TCC_EA_WRREQ[7]             TCC_EA_WRREQ_64B[7]   TCC_EA_RDREQ[8]                TCC_EA_RDREQ_32B[8]         TCC_EA_WRREQ[8]             TCC_EA_WRREQ_64B[8]   TCC_EA_RDREQ[9]                TCC_EA_RDREQ_32B[9]         TCC_EA_WRREQ[9]             TCC_EA_WRREQ_64B[9]   TCC_EA_RDREQ[10]               TCC_EA_RDREQ_32B[10]        TCC_EA_WRREQ[10]            TCC_EA_WRREQ_64B[10]  TCC_EA_RDREQ[11]               TCC_EA_RDREQ_32B[11]        TCC_EA_WRREQ[11]            TCC_EA_WRREQ_64B[11]  TCC_EA_RDREQ[12]               TCC_EA_RDREQ_32B[12]        TCC_EA_WRREQ[12]            TCC_EA_WRREQ_64B[12]  TCC_EA_RDREQ[13]               TCC_EA_RDREQ_32B[13]        TCC_EA_WRREQ[13]            TCC_EA_WRREQ_64B[13]  TCC_EA_RDREQ[14]               TCC_EA_RDREQ_32B[14]        TCC_EA_WRREQ[14]            TCC_EA_WRREQ_64B[14]  TCC_EA_RDREQ[15]               TCC_EA_RDREQ_32B[15]        TCC_EA_WRREQ[15]            TCC_EA_WRREQ_64B[15]  
+
+
+pmc: TCC_EA_ATOMIC[0]               TCC_EA_RDREQ_LEVEL[0]       TCC_EA_WRREQ_LEVEL[0]       TCC_EA_ATOMIC_LEVEL[0]  TCC_EA_ATOMIC[1]               TCC_EA_RDREQ_LEVEL[1]       TCC_EA_WRREQ_LEVEL[1]       TCC_EA_ATOMIC_LEVEL[1]  TCC_EA_ATOMIC[2]               TCC_EA_RDREQ_LEVEL[2]       TCC_EA_WRREQ_LEVEL[2]       TCC_EA_ATOMIC_LEVEL[2]  TCC_EA_ATOMIC[3]               TCC_EA_RDREQ_LEVEL[3]       TCC_EA_WRREQ_LEVEL[3]       TCC_EA_ATOMIC_LEVEL[3]  TCC_EA_ATOMIC[4]               TCC_EA_RDREQ_LEVEL[4]       TCC_EA_WRREQ_LEVEL[4]       TCC_EA_ATOMIC_LEVEL[4]  TCC_EA_ATOMIC[5]               TCC_EA_RDREQ_LEVEL[5]       TCC_EA_WRREQ_LEVEL[5]       TCC_EA_ATOMIC_LEVEL[5]  TCC_EA_ATOMIC[6]               TCC_EA_RDREQ_LEVEL[6]       TCC_EA_WRREQ_LEVEL[6]       TCC_EA_ATOMIC_LEVEL[6]  TCC_EA_ATOMIC[7]               TCC_EA_RDREQ_LEVEL[7]       TCC_EA_WRREQ_LEVEL[7]       TCC_EA_ATOMIC_LEVEL[7]  TCC_EA_ATOMIC[8]               TCC_EA_RDREQ_LEVEL[8]       TCC_EA_WRREQ_LEVEL[8]       TCC_EA_ATOMIC_LEVEL[8]  TCC_EA_ATOMIC[9]               TCC_EA_RDREQ_LEVEL[9]       TCC_EA_WRREQ_LEVEL[9]       TCC_EA_ATOMIC_LEVEL[9]  TCC_EA_ATOMIC[10]              TCC_EA_RDREQ_LEVEL[10]      TCC_EA_WRREQ_LEVEL[10]      TCC_EA_ATOMIC_LEVEL[10] TCC_EA_ATOMIC[11]              TCC_EA_RDREQ_LEVEL[11]      TCC_EA_WRREQ_LEVEL[11]      TCC_EA_ATOMIC_LEVEL[11] TCC_EA_ATOMIC[12]              TCC_EA_RDREQ_LEVEL[12]      TCC_EA_WRREQ_LEVEL[12]      TCC_EA_ATOMIC_LEVEL[12] TCC_EA_ATOMIC[13]              TCC_EA_RDREQ_LEVEL[13]      TCC_EA_WRREQ_LEVEL[13]      TCC_EA_ATOMIC_LEVEL[13] TCC_EA_ATOMIC[14]              TCC_EA_RDREQ_LEVEL[14]      TCC_EA_WRREQ_LEVEL[14]      TCC_EA_ATOMIC_LEVEL[14] TCC_EA_ATOMIC[15]              TCC_EA_RDREQ_LEVEL[15]      TCC_EA_WRREQ_LEVEL[15]      TCC_EA_ATOMIC_LEVEL[15] 
+
+
+pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0]   TCC_EA_RDREQ_GMI_CREDIT_STALL[0]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]  TCC_EA_RDREQ_IO_CREDIT_STALL[1]   TCC_EA_RDREQ_GMI_CREDIT_STALL[1]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]  TCC_EA_RDREQ_IO_CREDIT_STALL[2]   TCC_EA_RDREQ_GMI_CREDIT_STALL[2]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]  TCC_EA_RDREQ_IO_CREDIT_STALL[3]   TCC_EA_RDREQ_GMI_CREDIT_STALL[3]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]  TCC_EA_RDREQ_IO_CREDIT_STALL[4]   TCC_EA_RDREQ_GMI_CREDIT_STALL[4]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]  TCC_EA_RDREQ_IO_CREDIT_STALL[5]   TCC_EA_RDREQ_GMI_CREDIT_STALL[5]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]  TCC_EA_RDREQ_IO_CREDIT_STALL[6]   TCC_EA_RDREQ_GMI_CREDIT_STALL[6]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]  TCC_EA_RDREQ_IO_CREDIT_STALL[7]   TCC_EA_RDREQ_GMI_CREDIT_STALL[7]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]  TCC_EA_RDREQ_IO_CREDIT_STALL[8]   TCC_EA_RDREQ_GMI_CREDIT_STALL[8]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]  TCC_EA_RDREQ_IO_CREDIT_STALL[9]   TCC_EA_RDREQ_GMI_CREDIT_STALL[9]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]  TCC_EA_RDREQ_IO_CREDIT_STALL[10]  TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11]  TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12]  TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13]  TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14]  TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15]  TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] 
+
+
+pmc: TCC_EA_WRREQ_IO_CREDIT_STALL[0]   TCC_EA_WRREQ_GMI_CREDIT_STALL[0]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]  TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[1]   TCC_EA_WRREQ_GMI_CREDIT_STALL[1]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]  TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[2]   TCC_EA_WRREQ_GMI_CREDIT_STALL[2]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]  TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[3]   TCC_EA_WRREQ_GMI_CREDIT_STALL[3]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]  TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[4]   TCC_EA_WRREQ_GMI_CREDIT_STALL[4]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]  TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[5]   TCC_EA_WRREQ_GMI_CREDIT_STALL[5]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]  TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[6]   TCC_EA_WRREQ_GMI_CREDIT_STALL[6]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]  TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[7]   TCC_EA_WRREQ_GMI_CREDIT_STALL[7]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]  TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[8]   TCC_EA_WRREQ_GMI_CREDIT_STALL[8]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]  TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[9]   TCC_EA_WRREQ_GMI_CREDIT_STALL[9]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]  TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[10]  TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[11]  TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[12]  TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[13]  TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[14]  TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[15]  TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] 
+
+gpu: 
+kernel: 
+range: 
+

src/omniperf_soc/profile_configs/gfx906/pmc_tcc_perf.txt

@@ -0,0 +1,19 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_WAVES 
+
+pmc: TCC_CYCLE_sum                          TCC_BUSY_sum                          TCC_PROBE_sum                          TCC_PROBE_ALL_sum 
+pmc: TCC_NC_REQ_sum                         TCC_UC_REQ_sum                        TCC_CC_REQ_sum                         
+pmc: TCC_REQ_sum                            TCC_STREAMING_REQ_sum                 TCC_HIT_sum                            TCC_MISS_sum
+pmc: TCC_READ_sum                           TCC_WRITE_sum                         TCC_ATOMIC_sum                         TCC_WRITEBACK_sum
+pmc: TCC_EA_WRREQ_sum                       TCC_EA_WRREQ_64B_sum                  TCC_EA_WR_UNCACHED_32B_sum 
+pmc: TCC_EA_WRREQ_STALL_sum                 TCC_EA_WRREQ_IO_CREDIT_STALL_sum      TCC_EA_WRREQ_GMI_CREDIT_STALL_sum      TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
+pmc: TCC_TOO_MANY_EA_WRREQS_STALL_sum       TCC_EA_ATOMIC_sum                     TCC_EA_RDREQ_sum                       TCC_EA_RDREQ_32B_sum
+pmc: TCC_EA_RD_UNCACHED_32B_sum             TCC_EA_RDREQ_IO_CREDIT_STALL_sum      TCC_EA_RDREQ_GMI_CREDIT_STALL_sum      TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum
+pmc:                                        TCC_NORMAL_WRITEBACK_sum              TCC_ALL_TC_OP_WB_WRITEBACK_sum         TCC_NORMAL_EVICT_sum
+pmc: TCC_ALL_TC_OP_INV_EVICT_sum            TCC_EA_RDREQ_DRAM_sum                 TCC_EA_WRREQ_DRAM_sum                    
+pmc: TCC_EA_RDREQ_LEVEL_sum                 TCC_EA_WRREQ_LEVEL_sum                TCC_EA_ATOMIC_LEVEL_sum
+
+gpu: 
+kernel: 
+
+range: 
+

src/omniperf_soc/profile_configs/gfx906/pmc_tcp_perf.txt

@@ -0,0 +1,18 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_BUSY_CU_CYCLES       SQ_WAVES        SQ_WAVE_CYCLES
+
+pmc: TCP_GATE_EN1_sum                        TCP_GATE_EN2_sum                        TCP_TD_TCP_STALL_CYCLES_sum                     TCP_TCR_TCP_STALL_CYCLES_sum
+pmc: TCP_READ_TAGCONFLICT_STALL_CYCLES_sum   TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum  TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum         TCP_TA_TCP_STATE_READ_sum
+pmc: TCP_VOLATILE_sum                        TCP_TOTAL_ACCESSES_sum                  TCP_TOTAL_READ_sum                              TCP_TOTAL_WRITE_sum
+pmc: TCP_TOTAL_ATOMIC_WITH_RET_sum           TCP_TOTAL_ATOMIC_WITHOUT_RET_sum        TCP_TOTAL_WRITEBACK_INVALIDATES_sum             TCP_TOTAL_CACHE_ACCESSES_sum
+pmc: TCP_UTCL1_TRANSLATION_MISS_sum          TCP_UTCL1_TRANSLATION_HIT_sum           TCP_UTCL1_PERMISSION_MISS_sum                   TCP_UTCL1_REQUEST_sum
+pmc: TCP_TCP_LATENCY_sum                     TCP_TCC_READ_REQ_LATENCY_sum            TCP_TCC_WRITE_REQ_LATENCY_sum                   TCP_TCC_READ_REQ_sum
+pmc: TCP_TCC_WRITE_REQ_sum                   TCP_TCC_ATOMIC_WITH_RET_REQ_sum         TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum              TCP_TCC_NC_READ_REQ_sum
+pmc: TCP_TCC_NC_WRITE_REQ_sum                TCP_TCC_NC_ATOMIC_REQ_sum               TCP_TCC_UC_READ_REQ_sum                         TCP_TCC_UC_WRITE_REQ_sum
+pmc: TCP_TCC_UC_ATOMIC_REQ_sum               TCP_TCC_CC_READ_REQ_sum                 TCP_TCC_CC_WRITE_REQ_sum                        TCP_TCC_CC_ATOMIC_REQ_sum
+pmc:       				                								  	     TCP_PENDING_STALL_CYCLES_sum
+
+#pmc: TCA_CYCLE_sum                           TCA_BUSY_sum
+
+gpu: 
+kernel: 
+range: 

src/omniperf_soc/profile_configs/gfx906/pmc_td_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+pmc: TD_TD_BUSY_sum                          TD_TC_STALL_sum
+pmc: TD_COALESCABLE_WAVEFRONT_sum            TD_LOAD_WAVEFRONT_sum
+pmc: TD_ATOMIC_WAVEFRONT_sum                 TD_STORE_WAVEFRONT_sum
+
+
+
+gpu:
+range: 
+kernel: 
+

src/omniperf_soc/profile_configs/gfx908/pmc_cpc_perf.txt

@@ -0,0 +1,15 @@
+pmc: GRBM_COUNT  GRBM_GUI_ACTIVE        SQ_CYCLES       SQ_BUSY_CYCLES      SQ_WAVES     
+
+pmc: CPC_CPC_STAT_BUSY      CPC_CPC_STAT_IDLE
+pmc: CPC_CPC_TCIU_BUSY      CPC_CPC_TCIU_IDLE
+pmc: CPC_CPC_STAT_STALL     CPC_UTCL1_STALL_ON_TRANSLATION                   
+pmc: CPC_CPC_UTCL2IU_BUSY    CPC_CPC_UTCL2IU_IDLE    
+pmc: CPC_CPC_UTCL2IU_STALL   CPC_ME1_BUSY_FOR_PACKET_DECODE  
+pmc: CPC_ME1_DC0_SPI_BUSY
+
+range:
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_cpf_perf.txt

@@ -0,0 +1,13 @@
+pmc: GRBM_COUNT                 GRBM_GUI_ACTIVE                 SQ_CYCLES                       SQ_BUSY_CYCLES                  SQ_WAVES         
+
+pmc: CPF_CPF_STAT_BUSY                          CPF_CPF_STAT_STALL
+pmc: CPF_CPF_TCIU_BUSY                          CPF_CPF_TCIU_STALL
+pmc: CPF_CPF_STAT_IDLE                          CPF_CPF_TCIU_IDLE
+pmc: CPF_CMP_UTCL1_STALL_ON_TRANSLATION          
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_spi_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT             GRBM_GUI_ACTIVE            SQ_CYCLES                   SQ_BUSY_CYCLES            SQ_WAVES                   GRBM_SPI_BUSY
+
+pmc: SPI_CSN_WINDOW_VALID   SPI_CSN_BUSY               SPI_CSN_NUM_THREADGROUPS    SPI_CSN_WAVE              SPI_RA_REQ_NO_ALLOC        SPI_RA_REQ_NO_ALLOC_CSN     
+pmc: SPI_RA_RES_STALL_CSN   SPI_RA_TMP_STALL_CSN       SPI_RA_WAVE_SIMD_FULL_CSN   SPI_RA_VGPR_SIMD_FULL_CSN SPI_RA_SGPR_SIMD_FULL_CSN  SPI_RA_LDS_CU_FULL_CSN 
+pmc: SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN   SPI_RA_WVLIM_STALL_CSN      SPI_SWC_CSC_WR            SPI_VWC_CSC_WR             SPI_RA_BULKY_CU_FULL_CSN
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf1.txt

@@ -0,0 +1,31 @@
+#SQ
+pmc: GRBM_COUNT                    GRBM_GUI_ACTIVE                                     SQ_INSTS_VMEM_WR        SQ_INSTS_VMEM_RD       SQ_INSTS_VMEM            SQ_INSTS_SALU              SQ_INSTS_VSKIPPED         
+pmc: SQ_INSTS_SMEM                 SQ_INSTS_FLAT               SQ_INSTS_LDS            SQ_INSTS_GDS            SQ_INSTS_EXP_GDS       SQ_INSTS_BRANCH          SQ_INSTS_SENDMSG           SQ_INSTS    
+pmc: SQ_WAVE_CYCLES                SQ_WAIT_ANY                 SQ_WAIT_INST_ANY        SQ_ACTIVE_INST_ANY      SQ_CYCLES              SQ_BUSY_CYCLES           SQ_BUSY_CU_CYCLES          SQ_INSTS_VALU
+pmc: SQ_ACTIVE_INST_VMEM           SQ_ACTIVE_INST_LDS          SQ_ACTIVE_INST_VALU     SQ_ACTIVE_INST_SCA      SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC      SQ_ACTIVE_INST_FLAT        SQ_INST_CYCLES_VMEM_WR
+pmc: SQ_INST_CYCLES_VMEM_RD        SQ_INST_CYCLES_SMEM         SQ_INST_CYCLES_SALU     SQ_THREAD_CYCLES_VALU   SQ_IFETCH              SQ_LDS_BANK_CONFLICT     SQ_LDS_ADDR_CONFLICT       SQ_LDS_UNALIGNED_STALL
+pmc: SQ_WAVES                      SQ_WAVES_EQ_64              SQ_WAVES_LT_64          SQ_WAVES_LT_48          SQ_WAVES_LT_32         SQ_WAVES_LT_16           SQ_ITEMS                   SQ_INSTS_VSKIPPED      
+pmc: SQ_LDS_MEM_VIOLATIONS         SQ_LDS_ATOMIC_RETURN        SQ_LDS_IDX_ACTIVE       SQ_WAVES_RESTORED       SQ_WAVES_SAVED         SQ_INSTS_SMEM_NORM                           
+
+
+#SQ:MI200
+#pmc: SQ_INSTS_MFMA              SQ_INSTS_VALU_MFMA_I8         SQ_INSTS_VALU_MFMA_F16      SQ_INSTS_VALU_MFMA_BF16       SQ_INSTS_VALU_MFMA_F32        SQ_INSTS_VALU_MFMA_F64        SQ_VALU_MFMA_BUSY_CYCLES    
+#pmc: SQ_INSTS_FLAT_LDS_ONLY     SQ_INSTS_VALU_MFMA_MOPS_I8    SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16  SQ_INSTS_VALU_MFMA_MOPS_F32   SQ_INSTS_VALU_MFMA_MOPS_F64  
+
+#SQC
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+
+
+########################################
+# Filtering
+########################################
+range: 
+gpu: 
+kernel: 
+
+
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf2.txt

@@ -0,0 +1,12 @@
+#################################################
+# VMEM latency
+#################################################
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf3.txt

@@ -0,0 +1,13 @@
+#################################################
+# SMEM latency
+#################################################
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+
+range: 
+gpu: 
+
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf4.txt

@@ -0,0 +1,11 @@
+#################################################
+# ifetch latency
+#################################################
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+kernel: 
+
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf6.txt

@@ -0,0 +1,15 @@
+#################################################
+# LDS latency
+#################################################
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+range: 
+gpu: 
+
+kernel: 
+
+
+
+
+
+

src/omniperf_soc/profile_configs/gfx908/pmc_sq_perf8.txt

@@ -0,0 +1,7 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES 
+
+gpu: 
+range: 
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx908/pmc_sqc_perf1.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+
+pmc: SQC_TC_INST_REQ               SQC_TC_DATA_READ_REQ        SQC_TC_DATA_WRITE_REQ    SQC_TC_DATA_ATOMIC_REQ       SQC_TC_STALL                    SQC_TC_REQ               SQC_DCACHE_REQ_READ_16 
+pmc: SQC_ICACHE_REQ                SQC_ICACHE_HITS             SQC_ICACHE_MISSES        SQC_ICACHE_MISSES_DUPLICATE  SQC_DCACHE_INPUT_VALID_READYB   SQC_DCACHE_ATOMIC        SQC_DCACHE_REQ_READ_8  
+pmc: SQC_DCACHE_REQ                SQC_DCACHE_HITS             SQC_DCACHE_MISSES        SQC_DCACHE_MISSES_DUPLICATE  SQC_DCACHE_REQ_READ_1           SQC_DCACHE_REQ_READ_2    SQC_DCACHE_REQ_READ_4 
+
+range: 
+gpu:  
+
+kernel: 
+

src/omniperf_soc/profile_configs/gfx908/pmc_ta_perf.txt

@@ -0,0 +1,25 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES 
+
+pmc: TA_TA_BUSY_sum
+
+# buffer access
+pmc: TA_BUFFER_WAVEFRONTS_sum                   TA_BUFFER_READ_WAVEFRONTS_sum
+pmc: TA_BUFFER_WRITE_WAVEFRONTS_sum             TA_BUFFER_ATOMIC_WAVEFRONTS_sum
+pmc: TA_BUFFER_TOTAL_CYCLES_sum                 
+pmc: TA_BUFFER_COALESCED_READ_CYCLES_sum        TA_BUFFER_COALESCED_WRITE_CYCLES_sum
+
+
+# stalls
+pmc: TA_ADDR_STALLED_BY_TC_CYCLES_sum    TA_TOTAL_WAVEFRONTS_sum
+pmc: TA_ADDR_STALLED_BY_TD_CYCLES_sum    TA_DATA_STALLED_BY_TC_CYCLES_sum    
+
+# flat accesses
+pmc: TA_FLAT_WAVEFRONTS_sum              TA_FLAT_READ_WAVEFRONTS_sum         
+pmc: TA_FLAT_WRITE_WAVEFRONTS_sum        TA_FLAT_ATOMIC_WAVEFRONTS_sum
+
+
+range: 
+
+gpu:
+
+kernel: 

src/omniperf_soc/profile_configs/gfx908/pmc_tcc2_perf.txt

@@ -0,0 +1,27 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_WAVES
+
+pmc: TCC_CYCLE[0]                   TCC_RW_REQ[0]               TCC_HIT[0]                  TCC_MISS[0]  TCC_CYCLE[1]                   TCC_RW_REQ[1]               TCC_HIT[1]                  TCC_MISS[1]  TCC_CYCLE[2]                   TCC_RW_REQ[2]               TCC_HIT[2]                  TCC_MISS[2]  TCC_CYCLE[3]                   TCC_RW_REQ[3]               TCC_HIT[3]                  TCC_MISS[3]  TCC_CYCLE[4]                   TCC_RW_REQ[4]               TCC_HIT[4]                  TCC_MISS[4]  TCC_CYCLE[5]                   TCC_RW_REQ[5]               TCC_HIT[5]                  TCC_MISS[5]  TCC_CYCLE[6]                   TCC_RW_REQ[6]               TCC_HIT[6]                  TCC_MISS[6]  TCC_CYCLE[7]                   TCC_RW_REQ[7]               TCC_HIT[7]                  TCC_MISS[7]  TCC_CYCLE[8]                   TCC_RW_REQ[8]               TCC_HIT[8]                  TCC_MISS[8]  TCC_CYCLE[9]                   TCC_RW_REQ[9]               TCC_HIT[9]                  TCC_MISS[9]  TCC_CYCLE[10]                  TCC_RW_REQ[10]              TCC_HIT[10]                 TCC_MISS[10] TCC_CYCLE[11]                  TCC_RW_REQ[11]              TCC_HIT[11]                 TCC_MISS[11] TCC_CYCLE[12]                  TCC_RW_REQ[12]              TCC_HIT[12]                 TCC_MISS[12] TCC_CYCLE[13]                  TCC_RW_REQ[13]              TCC_HIT[13]                 TCC_MISS[13] TCC_CYCLE[14]                  TCC_RW_REQ[14]              TCC_HIT[14]                 TCC_MISS[14] TCC_CYCLE[15]                  TCC_RW_REQ[15]              TCC_HIT[15]                 TCC_MISS[15] TCC_CYCLE[16]                  TCC_RW_REQ[16]              TCC_HIT[16]                 TCC_MISS[16] TCC_CYCLE[17]                  TCC_RW_REQ[17]              TCC_HIT[17]                 TCC_MISS[17] TCC_CYCLE[18]                  TCC_RW_REQ[18]              TCC_HIT[18]                 TCC_MISS[18] TCC_CYCLE[19]                  TCC_RW_REQ[19]              TCC_HIT[19]                 TCC_MISS[19] TCC_CYCLE[20]                  TCC_RW_REQ[20]              TCC_HIT[20]                 TCC_MISS[20] TCC_CYCLE[21]                  TCC_RW_REQ[21]              TCC_HIT[21]                 TCC_MISS[21] TCC_CYCLE[22]                  TCC_RW_REQ[22]              TCC_HIT[22]                 TCC_MISS[22] TCC_CYCLE[23]                  TCC_RW_REQ[23]              TCC_HIT[23]                 TCC_MISS[23] TCC_CYCLE[24]                  TCC_RW_REQ[24]              TCC_HIT[24]                 TCC_MISS[24] TCC_CYCLE[25]                  TCC_RW_REQ[25]              TCC_HIT[25]                 TCC_MISS[25] TCC_CYCLE[26]                  TCC_RW_REQ[26]              TCC_HIT[26]                 TCC_MISS[26] TCC_CYCLE[27]                  TCC_RW_REQ[27]              TCC_HIT[27]                 TCC_MISS[27] TCC_CYCLE[28]                  TCC_RW_REQ[28]              TCC_HIT[28]                 TCC_MISS[28] TCC_CYCLE[29]                  TCC_RW_REQ[29]              TCC_HIT[29]                 TCC_MISS[29] TCC_CYCLE[30]                  TCC_RW_REQ[30]              TCC_HIT[30]                 TCC_MISS[30] TCC_CYCLE[31]                  TCC_RW_REQ[31]              TCC_HIT[31]                 TCC_MISS[31] 
+
+
+
+pmc: TCC_REQ[0]                     TCC_READ[0]                 TCC_WRITE[0]                TCC_ATOMIC[0]   TCC_REQ[1]                     TCC_READ[1]                 TCC_WRITE[1]                TCC_ATOMIC[1]   TCC_REQ[2]                     TCC_READ[2]                 TCC_WRITE[2]                TCC_ATOMIC[2]   TCC_REQ[3]                     TCC_READ[3]                 TCC_WRITE[3]                TCC_ATOMIC[3]   TCC_REQ[4]                     TCC_READ[4]                 TCC_WRITE[4]                TCC_ATOMIC[4]   TCC_REQ[5]                     TCC_READ[5]                 TCC_WRITE[5]                TCC_ATOMIC[5]   TCC_REQ[6]                     TCC_READ[6]                 TCC_WRITE[6]                TCC_ATOMIC[6]   TCC_REQ[7]                     TCC_READ[7]                 TCC_WRITE[7]                TCC_ATOMIC[7]   TCC_REQ[8]                     TCC_READ[8]                 TCC_WRITE[8]                TCC_ATOMIC[8]   TCC_REQ[9]                     TCC_READ[9]                 TCC_WRITE[9]                TCC_ATOMIC[9]   TCC_REQ[10]                    TCC_READ[10]                TCC_WRITE[10]               TCC_ATOMIC[10]  TCC_REQ[11]                    TCC_READ[11]                TCC_WRITE[11]               TCC_ATOMIC[11]  TCC_REQ[12]                    TCC_READ[12]                TCC_WRITE[12]               TCC_ATOMIC[12]  TCC_REQ[13]                    TCC_READ[13]                TCC_WRITE[13]               TCC_ATOMIC[13]  TCC_REQ[14]                    TCC_READ[14]                TCC_WRITE[14]               TCC_ATOMIC[14]  TCC_REQ[15]                    TCC_READ[15]                TCC_WRITE[15]               TCC_ATOMIC[15]  TCC_REQ[16]                    TCC_READ[16]                TCC_WRITE[16]               TCC_ATOMIC[16]  TCC_REQ[17]                    TCC_READ[17]                TCC_WRITE[17]               TCC_ATOMIC[17]  TCC_REQ[18]                    TCC_READ[18]                TCC_WRITE[18]               TCC_ATOMIC[18]  TCC_REQ[19]                    TCC_READ[19]                TCC_WRITE[19]               TCC_ATOMIC[19]  TCC_REQ[20]                    TCC_READ[20]                TCC_WRITE[20]               TCC_ATOMIC[20]  TCC_REQ[21]                    TCC_READ[21]                TCC_WRITE[21]               TCC_ATOMIC[21]  TCC_REQ[22]                    TCC_READ[22]                TCC_WRITE[22]               TCC_ATOMIC[22]  TCC_REQ[23]                    TCC_READ[23]                TCC_WRITE[23]               TCC_ATOMIC[23]  TCC_REQ[24]                    TCC_READ[24]                TCC_WRITE[24]               TCC_ATOMIC[24]  TCC_REQ[25]                    TCC_READ[25]                TCC_WRITE[25]               TCC_ATOMIC[25]  TCC_REQ[26]                    TCC_READ[26]                TCC_WRITE[26]               TCC_ATOMIC[26]  TCC_REQ[27]                    TCC_READ[27]                TCC_WRITE[27]               TCC_ATOMIC[27]  TCC_REQ[28]                    TCC_READ[28]                TCC_WRITE[28]               TCC_ATOMIC[28]  TCC_REQ[29]                    TCC_READ[29]                TCC_WRITE[29]               TCC_ATOMIC[29]  TCC_REQ[30]                    TCC_READ[30]                TCC_WRITE[30]               TCC_ATOMIC[30]  TCC_REQ[31]                    TCC_READ[31]                TCC_WRITE[31]               TCC_ATOMIC[31]  
+
+
+
+pmc: TCC_EA_RDREQ[0]                TCC_EA_RDREQ_32B[0]         TCC_EA_WRREQ[0]             TCC_EA_WRREQ_64B[0]   TCC_EA_RDREQ[1]                TCC_EA_RDREQ_32B[1]         TCC_EA_WRREQ[1]             TCC_EA_WRREQ_64B[1]   TCC_EA_RDREQ[2]                TCC_EA_RDREQ_32B[2]         TCC_EA_WRREQ[2]             TCC_EA_WRREQ_64B[2]   TCC_EA_RDREQ[3]                TCC_EA_RDREQ_32B[3]         TCC_EA_WRREQ[3]             TCC_EA_WRREQ_64B[3]   TCC_EA_RDREQ[4]                TCC_EA_RDREQ_32B[4]         TCC_EA_WRREQ[4]             TCC_EA_WRREQ_64B[4]   TCC_EA_RDREQ[5]                TCC_EA_RDREQ_32B[5]         TCC_EA_WRREQ[5]             TCC_EA_WRREQ_64B[5]   TCC_EA_RDREQ[6]                TCC_EA_RDREQ_32B[6]         TCC_EA_WRREQ[6]             TCC_EA_WRREQ_64B[6]   TCC_EA_RDREQ[7]                TCC_EA_RDREQ_32B[7]         TCC_EA_WRREQ[7]             TCC_EA_WRREQ_64B[7]   TCC_EA_RDREQ[8]                TCC_EA_RDREQ_32B[8]         TCC_EA_WRREQ[8]             TCC_EA_WRREQ_64B[8]   TCC_EA_RDREQ[9]                TCC_EA_RDREQ_32B[9]         TCC_EA_WRREQ[9]             TCC_EA_WRREQ_64B[9]   TCC_EA_RDREQ[10]               TCC_EA_RDREQ_32B[10]        TCC_EA_WRREQ[10]            TCC_EA_WRREQ_64B[10]  TCC_EA_RDREQ[11]               TCC_EA_RDREQ_32B[11]        TCC_EA_WRREQ[11]            TCC_EA_WRREQ_64B[11]  TCC_EA_RDREQ[12]               TCC_EA_RDREQ_32B[12]        TCC_EA_WRREQ[12]            TCC_EA_WRREQ_64B[12]  TCC_EA_RDREQ[13]               TCC_EA_RDREQ_32B[13]        TCC_EA_WRREQ[13]            TCC_EA_WRREQ_64B[13]  TCC_EA_RDREQ[14]               TCC_EA_RDREQ_32B[14]        TCC_EA_WRREQ[14]            TCC_EA_WRREQ_64B[14]  TCC_EA_RDREQ[15]               TCC_EA_RDREQ_32B[15]        TCC_EA_WRREQ[15]            TCC_EA_WRREQ_64B[15]  TCC_EA_RDREQ[16]               TCC_EA_RDREQ_32B[16]        TCC_EA_WRREQ[16]            TCC_EA_WRREQ_64B[16]  TCC_EA_RDREQ[17]               TCC_EA_RDREQ_32B[17]        TCC_EA_WRREQ[17]            TCC_EA_WRREQ_64B[17]  TCC_EA_RDREQ[18]               TCC_EA_RDREQ_32B[18]        TCC_EA_WRREQ[18]            TCC_EA_WRREQ_64B[18]  TCC_EA_RDREQ[19]               TCC_EA_RDREQ_32B[19]        TCC_EA_WRREQ[19]            TCC_EA_WRREQ_64B[19]  TCC_EA_RDREQ[20]               TCC_EA_RDREQ_32B[20]        TCC_EA_WRREQ[20]            TCC_EA_WRREQ_64B[20]  TCC_EA_RDREQ[21]               TCC_EA_RDREQ_32B[21]        TCC_EA_WRREQ[21]            TCC_EA_WRREQ_64B[21]  TCC_EA_RDREQ[22]               TCC_EA_RDREQ_32B[22]        TCC_EA_WRREQ[22]            TCC_EA_WRREQ_64B[22]  TCC_EA_RDREQ[23]               TCC_EA_RDREQ_32B[23]        TCC_EA_WRREQ[23]            TCC_EA_WRREQ_64B[23]  TCC_EA_RDREQ[24]               TCC_EA_RDREQ_32B[24]        TCC_EA_WRREQ[24]            TCC_EA_WRREQ_64B[24]  TCC_EA_RDREQ[25]               TCC_EA_RDREQ_32B[25]        TCC_EA_WRREQ[25]            TCC_EA_WRREQ_64B[25]  TCC_EA_RDREQ[26]               TCC_EA_RDREQ_32B[26]        TCC_EA_WRREQ[26]            TCC_EA_WRREQ_64B[26]  TCC_EA_RDREQ[27]               TCC_EA_RDREQ_32B[27]        TCC_EA_WRREQ[27]            TCC_EA_WRREQ_64B[27]  TCC_EA_RDREQ[28]               TCC_EA_RDREQ_32B[28]        TCC_EA_WRREQ[28]            TCC_EA_WRREQ_64B[28]  TCC_EA_RDREQ[29]               TCC_EA_RDREQ_32B[29]        TCC_EA_WRREQ[29]            TCC_EA_WRREQ_64B[29]  TCC_EA_RDREQ[30]               TCC_EA_RDREQ_32B[30]        TCC_EA_WRREQ[30]            TCC_EA_WRREQ_64B[30]  TCC_EA_RDREQ[31]               TCC_EA_RDREQ_32B[31]        TCC_EA_WRREQ[31]            TCC_EA_WRREQ_64B[31]  
+
+
+pmc: TCC_EA_ATOMIC[0]               TCC_EA_RDREQ_LEVEL[0]       TCC_EA_WRREQ_LEVEL[0]       TCC_EA_ATOMIC_LEVEL[0]  TCC_EA_ATOMIC[1]               TCC_EA_RDREQ_LEVEL[1]       TCC_EA_WRREQ_LEVEL[1]       TCC_EA_ATOMIC_LEVEL[1]  TCC_EA_ATOMIC[2]               TCC_EA_RDREQ_LEVEL[2]       TCC_EA_WRREQ_LEVEL[2]       TCC_EA_ATOMIC_LEVEL[2]  TCC_EA_ATOMIC[3]               TCC_EA_RDREQ_LEVEL[3]       TCC_EA_WRREQ_LEVEL[3]       TCC_EA_ATOMIC_LEVEL[3]  TCC_EA_ATOMIC[4]               TCC_EA_RDREQ_LEVEL[4]       TCC_EA_WRREQ_LEVEL[4]       TCC_EA_ATOMIC_LEVEL[4]  TCC_EA_ATOMIC[5]               TCC_EA_RDREQ_LEVEL[5]       TCC_EA_WRREQ_LEVEL[5]       TCC_EA_ATOMIC_LEVEL[5]  TCC_EA_ATOMIC[6]               TCC_EA_RDREQ_LEVEL[6]       TCC_EA_WRREQ_LEVEL[6]       TCC_EA_ATOMIC_LEVEL[6]  TCC_EA_ATOMIC[7]               TCC_EA_RDREQ_LEVEL[7]       TCC_EA_WRREQ_LEVEL[7]       TCC_EA_ATOMIC_LEVEL[7]  TCC_EA_ATOMIC[8]               TCC_EA_RDREQ_LEVEL[8]       TCC_EA_WRREQ_LEVEL[8]       TCC_EA_ATOMIC_LEVEL[8]  TCC_EA_ATOMIC[9]               TCC_EA_RDREQ_LEVEL[9]       TCC_EA_WRREQ_LEVEL[9]       TCC_EA_ATOMIC_LEVEL[9]  TCC_EA_ATOMIC[10]              TCC_EA_RDREQ_LEVEL[10]      TCC_EA_WRREQ_LEVEL[10]      TCC_EA_ATOMIC_LEVEL[10] TCC_EA_ATOMIC[11]              TCC_EA_RDREQ_LEVEL[11]      TCC_EA_WRREQ_LEVEL[11]      TCC_EA_ATOMIC_LEVEL[11] TCC_EA_ATOMIC[12]              TCC_EA_RDREQ_LEVEL[12]      TCC_EA_WRREQ_LEVEL[12]      TCC_EA_ATOMIC_LEVEL[12] TCC_EA_ATOMIC[13]              TCC_EA_RDREQ_LEVEL[13]      TCC_EA_WRREQ_LEVEL[13]      TCC_EA_ATOMIC_LEVEL[13] TCC_EA_ATOMIC[14]              TCC_EA_RDREQ_LEVEL[14]      TCC_EA_WRREQ_LEVEL[14]      TCC_EA_ATOMIC_LEVEL[14] TCC_EA_ATOMIC[15]              TCC_EA_RDREQ_LEVEL[15]      TCC_EA_WRREQ_LEVEL[15]      TCC_EA_ATOMIC_LEVEL[15] TCC_EA_ATOMIC[16]              TCC_EA_RDREQ_LEVEL[16]      TCC_EA_WRREQ_LEVEL[16]      TCC_EA_ATOMIC_LEVEL[16] TCC_EA_ATOMIC[17]              TCC_EA_RDREQ_LEVEL[17]      TCC_EA_WRREQ_LEVEL[17]      TCC_EA_ATOMIC_LEVEL[17] TCC_EA_ATOMIC[18]              TCC_EA_RDREQ_LEVEL[18]      TCC_EA_WRREQ_LEVEL[18]      TCC_EA_ATOMIC_LEVEL[18] TCC_EA_ATOMIC[19]              TCC_EA_RDREQ_LEVEL[19]      TCC_EA_WRREQ_LEVEL[19]      TCC_EA_ATOMIC_LEVEL[19] TCC_EA_ATOMIC[20]              TCC_EA_RDREQ_LEVEL[20]      TCC_EA_WRREQ_LEVEL[20]      TCC_EA_ATOMIC_LEVEL[20] TCC_EA_ATOMIC[21]              TCC_EA_RDREQ_LEVEL[21]      TCC_EA_WRREQ_LEVEL[21]      TCC_EA_ATOMIC_LEVEL[21] TCC_EA_ATOMIC[22]              TCC_EA_RDREQ_LEVEL[22]      TCC_EA_WRREQ_LEVEL[22]      TCC_EA_ATOMIC_LEVEL[22] TCC_EA_ATOMIC[23]              TCC_EA_RDREQ_LEVEL[23]      TCC_EA_WRREQ_LEVEL[23]      TCC_EA_ATOMIC_LEVEL[23] TCC_EA_ATOMIC[24]              TCC_EA_RDREQ_LEVEL[24]      TCC_EA_WRREQ_LEVEL[24]      TCC_EA_ATOMIC_LEVEL[24] TCC_EA_ATOMIC[25]              TCC_EA_RDREQ_LEVEL[25]      TCC_EA_WRREQ_LEVEL[25]      TCC_EA_ATOMIC_LEVEL[25] TCC_EA_ATOMIC[26]              TCC_EA_RDREQ_LEVEL[26]      TCC_EA_WRREQ_LEVEL[26]      TCC_EA_ATOMIC_LEVEL[26] TCC_EA_ATOMIC[27]              TCC_EA_RDREQ_LEVEL[27]      TCC_EA_WRREQ_LEVEL[27]      TCC_EA_ATOMIC_LEVEL[27] TCC_EA_ATOMIC[28]              TCC_EA_RDREQ_LEVEL[28]      TCC_EA_WRREQ_LEVEL[28]      TCC_EA_ATOMIC_LEVEL[28] TCC_EA_ATOMIC[29]              TCC_EA_RDREQ_LEVEL[29]      TCC_EA_WRREQ_LEVEL[29]      TCC_EA_ATOMIC_LEVEL[29] TCC_EA_ATOMIC[30]              TCC_EA_RDREQ_LEVEL[30]      TCC_EA_WRREQ_LEVEL[30]      TCC_EA_ATOMIC_LEVEL[30] TCC_EA_ATOMIC[31]              TCC_EA_RDREQ_LEVEL[31]      TCC_EA_WRREQ_LEVEL[31]      TCC_EA_ATOMIC_LEVEL[31] 
+
+
+
+
+pmc: TCC_EA_RDREQ_IO_CREDIT_STALL[0]   TCC_EA_RDREQ_GMI_CREDIT_STALL[0]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]  TCC_EA_RDREQ_IO_CREDIT_STALL[1]   TCC_EA_RDREQ_GMI_CREDIT_STALL[1]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]  TCC_EA_RDREQ_IO_CREDIT_STALL[2]   TCC_EA_RDREQ_GMI_CREDIT_STALL[2]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]  TCC_EA_RDREQ_IO_CREDIT_STALL[3]   TCC_EA_RDREQ_GMI_CREDIT_STALL[3]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]  TCC_EA_RDREQ_IO_CREDIT_STALL[4]   TCC_EA_RDREQ_GMI_CREDIT_STALL[4]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]  TCC_EA_RDREQ_IO_CREDIT_STALL[5]   TCC_EA_RDREQ_GMI_CREDIT_STALL[5]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]  TCC_EA_RDREQ_IO_CREDIT_STALL[6]   TCC_EA_RDREQ_GMI_CREDIT_STALL[6]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]  TCC_EA_RDREQ_IO_CREDIT_STALL[7]   TCC_EA_RDREQ_GMI_CREDIT_STALL[7]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]  TCC_EA_RDREQ_IO_CREDIT_STALL[8]   TCC_EA_RDREQ_GMI_CREDIT_STALL[8]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]  TCC_EA_RDREQ_IO_CREDIT_STALL[9]   TCC_EA_RDREQ_GMI_CREDIT_STALL[9]  TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]  TCC_EA_RDREQ_IO_CREDIT_STALL[10]  TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11]  TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12]  TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13]  TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14]  TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15]  TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16]  TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17]  TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18]  TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19]  TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20]  TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21]  TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22]  TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23]  TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24]  TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25]  TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26]  TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27]  TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28]  TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29]  TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30]  TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31]  TCC_EA_RDREQ_GMI_CREDIT_STALL[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] 
+
+
+pmc: TCC_EA_WRREQ_IO_CREDIT_STALL[0]   TCC_EA_WRREQ_GMI_CREDIT_STALL[0]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]  TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[1]   TCC_EA_WRREQ_GMI_CREDIT_STALL[1]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]  TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[2]   TCC_EA_WRREQ_GMI_CREDIT_STALL[2]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]  TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[3]   TCC_EA_WRREQ_GMI_CREDIT_STALL[3]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]  TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[4]   TCC_EA_WRREQ_GMI_CREDIT_STALL[4]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]  TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[5]   TCC_EA_WRREQ_GMI_CREDIT_STALL[5]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]  TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[6]   TCC_EA_WRREQ_GMI_CREDIT_STALL[6]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]  TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[7]   TCC_EA_WRREQ_GMI_CREDIT_STALL[7]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]  TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[8]   TCC_EA_WRREQ_GMI_CREDIT_STALL[8]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]  TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[9]   TCC_EA_WRREQ_GMI_CREDIT_STALL[9]  TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]  TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[10]  TCC_EA_WRREQ_GMI_CREDIT_STALL[10] TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[11]  TCC_EA_WRREQ_GMI_CREDIT_STALL[11] TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[12]  TCC_EA_WRREQ_GMI_CREDIT_STALL[12] TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[13]  TCC_EA_WRREQ_GMI_CREDIT_STALL[13] TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[14]  TCC_EA_WRREQ_GMI_CREDIT_STALL[14] TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[15]  TCC_EA_WRREQ_GMI_CREDIT_STALL[15] TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[16]  TCC_EA_WRREQ_GMI_CREDIT_STALL[16] TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] TCC_TOO_MANY_EA_WRREQS_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[17]  TCC_EA_WRREQ_GMI_CREDIT_STALL[17] TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] TCC_TOO_MANY_EA_WRREQS_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[18]  TCC_EA_WRREQ_GMI_CREDIT_STALL[18] TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] TCC_TOO_MANY_EA_WRREQS_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[19]  TCC_EA_WRREQ_GMI_CREDIT_STALL[19] TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] TCC_TOO_MANY_EA_WRREQS_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[20]  TCC_EA_WRREQ_GMI_CREDIT_STALL[20] TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] TCC_TOO_MANY_EA_WRREQS_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[21]  TCC_EA_WRREQ_GMI_CREDIT_STALL[21] TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] TCC_TOO_MANY_EA_WRREQS_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[22]  TCC_EA_WRREQ_GMI_CREDIT_STALL[22] TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] TCC_TOO_MANY_EA_WRREQS_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[23]  TCC_EA_WRREQ_GMI_CREDIT_STALL[23] TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] TCC_TOO_MANY_EA_WRREQS_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[24]  TCC_EA_WRREQ_GMI_CREDIT_STALL[24] TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] TCC_TOO_MANY_EA_WRREQS_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[25]  TCC_EA_WRREQ_GMI_CREDIT_STALL[25] TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] TCC_TOO_MANY_EA_WRREQS_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[26]  TCC_EA_WRREQ_GMI_CREDIT_STALL[26] TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] TCC_TOO_MANY_EA_WRREQS_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[27]  TCC_EA_WRREQ_GMI_CREDIT_STALL[27] TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] TCC_TOO_MANY_EA_WRREQS_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[28]  TCC_EA_WRREQ_GMI_CREDIT_STALL[28] TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] TCC_TOO_MANY_EA_WRREQS_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[29]  TCC_EA_WRREQ_GMI_CREDIT_STALL[29] TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] TCC_TOO_MANY_EA_WRREQS_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[30]  TCC_EA_WRREQ_GMI_CREDIT_STALL[30] TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] TCC_TOO_MANY_EA_WRREQS_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[31]  TCC_EA_WRREQ_GMI_CREDIT_STALL[31] TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] TCC_TOO_MANY_EA_WRREQS_STALL[31]
+
+gpu: 
+kernel: 
+range: 
+

src/omniperf_soc/profile_configs/gfx908/pmc_tcc_perf.txt

@@ -0,0 +1,19 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_WAVES 
+
+pmc: TCC_CYCLE_sum                          TCC_BUSY_sum                          TCC_PROBE_sum                          TCC_PROBE_ALL_sum 
+pmc: TCC_NC_REQ_sum                         TCC_UC_REQ_sum                        TCC_CC_REQ_sum                         TCC_RW_REQ_sum
+pmc: TCC_REQ_sum                            TCC_STREAMING_REQ_sum                 TCC_HIT_sum                            TCC_MISS_sum
+pmc: TCC_READ_sum                           TCC_WRITE_sum                         TCC_ATOMIC_sum                         TCC_WRITEBACK_sum
+pmc: TCC_EA_WRREQ_sum                       TCC_EA_WRREQ_64B_sum                  TCC_EA_WR_UNCACHED_32B_sum 
+pmc: TCC_EA_WRREQ_STALL_sum                 TCC_EA_WRREQ_IO_CREDIT_STALL_sum      TCC_EA_WRREQ_GMI_CREDIT_STALL_sum      TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum
+pmc: TCC_TOO_MANY_EA_WRREQS_STALL_sum       TCC_EA_ATOMIC_sum                     TCC_EA_RDREQ_sum                       TCC_EA_RDREQ_32B_sum
+pmc: TCC_EA_RD_UNCACHED_32B_sum             TCC_EA_RDREQ_IO_CREDIT_STALL_sum      TCC_EA_RDREQ_GMI_CREDIT_STALL_sum      TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum
+pmc: TCC_TAG_STALL_sum                      TCC_NORMAL_WRITEBACK_sum              TCC_ALL_TC_OP_WB_WRITEBACK_sum         TCC_NORMAL_EVICT_sum
+pmc: TCC_ALL_TC_OP_INV_EVICT_sum            TCC_EA_RDREQ_DRAM_sum                 TCC_EA_WRREQ_DRAM_sum                    
+pmc: TCC_EA_RDREQ_LEVEL_sum                 TCC_EA_WRREQ_LEVEL_sum                TCC_EA_ATOMIC_LEVEL_sum
+
+gpu: 
+kernel: 
+
+range: 
+

src/omniperf_soc/profile_configs/gfx908/pmc_tcp_perf.txt

@@ -0,0 +1,18 @@
+pmc: GRBM_COUNT         GRBM_GUI_ACTIVE         SQ_CYCLES       SQ_BUSY_CYCLES          SQ_BUSY_CU_CYCLES       SQ_WAVES        SQ_WAVE_CYCLES
+
+pmc: TCP_GATE_EN1_sum                        TCP_GATE_EN2_sum                        TCP_TD_TCP_STALL_CYCLES_sum                     TCP_TCR_TCP_STALL_CYCLES_sum
+pmc: TCP_READ_TAGCONFLICT_STALL_CYCLES_sum   TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum  TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum         TCP_TA_TCP_STATE_READ_sum
+pmc: TCP_VOLATILE_sum                        TCP_TOTAL_ACCESSES_sum                  TCP_TOTAL_READ_sum                              TCP_TOTAL_WRITE_sum
+pmc: TCP_TOTAL_ATOMIC_WITH_RET_sum           TCP_TOTAL_ATOMIC_WITHOUT_RET_sum        TCP_TOTAL_WRITEBACK_INVALIDATES_sum             TCP_TOTAL_CACHE_ACCESSES_sum
+pmc: TCP_UTCL1_TRANSLATION_MISS_sum          TCP_UTCL1_TRANSLATION_HIT_sum           TCP_UTCL1_PERMISSION_MISS_sum                   TCP_UTCL1_REQUEST_sum
+pmc: TCP_TCP_LATENCY_sum                     TCP_TCC_READ_REQ_LATENCY_sum            TCP_TCC_WRITE_REQ_LATENCY_sum                   TCP_TCC_READ_REQ_sum
+pmc: TCP_TCC_WRITE_REQ_sum                   TCP_TCC_ATOMIC_WITH_RET_REQ_sum         TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum              TCP_TCC_NC_READ_REQ_sum
+pmc: TCP_TCC_NC_WRITE_REQ_sum                TCP_TCC_NC_ATOMIC_REQ_sum               TCP_TCC_UC_READ_REQ_sum                         TCP_TCC_UC_WRITE_REQ_sum
+pmc: TCP_TCC_UC_ATOMIC_REQ_sum               TCP_TCC_CC_READ_REQ_sum                 TCP_TCC_CC_WRITE_REQ_sum                        TCP_TCC_CC_ATOMIC_REQ_sum
+pmc: TCP_TCC_RW_READ_REQ_sum                 TCP_TCC_RW_WRITE_REQ_sum                TCP_TCC_RW_ATOMIC_REQ_sum                       TCP_PENDING_STALL_CYCLES_sum
+
+#pmc: TCA_CYCLE_sum                           TCA_BUSY_sum
+
+gpu: 
+kernel: 
+range: 

src/omniperf_soc/profile_configs/gfx908/pmc_td_perf.txt

@@ -0,0 +1,12 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES
+
+pmc: TD_TD_BUSY_sum                          TD_TC_STALL_sum
+pmc: TD_COALESCABLE_WAVEFRONT_sum            TD_LOAD_WAVEFRONT_sum
+pmc: TD_ATOMIC_WAVEFRONT_sum                 TD_STORE_WAVEFRONT_sum
+
+
+
+gpu:
+range: 
+kernel: 
+

src/omniperf_soc/profile_configs/gfx908_metrics.xml

@@ -0,0 +1,737 @@
+<gfx908>
+  # CPC counters
+  <metric
+    name="CPC_ME1_BUSY_FOR_PACKET_DECODE" block=CPC event=13 descr="Me1 busy for packet decode."
+  ></metric>
+  <metric
+    name="CPC_UTCL1_STALL_ON_TRANSLATION" block=CPC event=24 descr="One of the UTCL1s is stalled waiting on translation, XNACK or PENDING response."
+  ></metric>
+  <metric
+    name="CPC_CPC_STAT_BUSY" block=CPC event=25 descr="CPC Busy."
+  ></metric>
+  <metric
+    name="CPC_CPC_STAT_IDLE" block=CPC event=26 descr="CPC Idle."
+  ></metric>
+  <metric
+    name="CPC_CPC_STAT_STALL" block=CPC event=27 descr="CPC Stalled."
+  ></metric>
+  <metric
+    name="CPC_CPC_TCIU_BUSY" block=CPC event=28 descr="CPC TCIU interface Busy."
+  ></metric>
+  <metric
+    name="CPC_CPC_TCIU_IDLE" block=CPC event=29 descr="CPC TCIU interface Idle."
+  ></metric>
+  <metric
+    name="CPC_CPC_UTCL2IU_BUSY" block=CPC event=30 descr="CPC UTCL2 interface Busy."
+  ></metric>
+  <metric
+    name="CPC_CPC_UTCL2IU_IDLE" block=CPC event=31 descr="CPC UTCL2 interface Idle."
+  ></metric>
+  <metric
+    name="CPC_CPC_UTCL2IU_STALL" block=CPC event=32 descr="CPC UTCL2 interface Stalled waiting on Free, Tags or Translation."
+  ></metric>
+  <metric
+    name="CPC_ME1_DC0_SPI_BUSY" block=CPC event=33 descr="CPC Me1 Processor Busy."
+  ></metric>
+  <metric
+    name="CPF_CMP_UTCL1_STALL_ON_TRANSLATION" block=CPF event=20 descr="One of the Compute UTCL1s is stalled waiting on translation, XNACK or PENDING response."
+  ></metric>
+  <metric
+    name="CPF_CPF_STAT_BUSY" block=CPF event=23 descr="CPF Busy."
+  ></metric>
+  <metric
+    name="CPF_CPF_STAT_IDLE" block=CPF event=24 descr="CPF Idle."
+  ></metric>
+  <metric
+    name="CPF_CPF_STAT_STALL" block=CPF event=25 descr="CPF Stalled."
+  ></metric>
+  <metric
+    name="CPF_CPF_TCIU_BUSY" block=CPF event=26 descr="CPF TCIU interface Busy."
+  ></metric>
+  <metric
+    name="CPF_CPF_TCIU_IDLE" block=CPF event=27 descr="CPF TCIU interface Idle."
+  ></metric>
+  <metric
+    name="CPF_CPF_TCIU_STALL" block=CPF event=28 descr="CPF TCIU interface Stalled waiting on Free, Tags."
+  ></metric>
+  # GRBM counters
+  <metric
+    name="GRBM_COUNT" block=GRBM event=0 descr="Tie High - Count Number of Clocks"
+  ></metric>
+  <metric
+    name="GRBM_GUI_ACTIVE" block=GRBM event=2 descr="The GUI is Active"
+  ></metric>
+  <metric
+    name="GRBM_CP_BUSY" block=GRBM event=3 descr="Any of the Command Processor (CPG/CPC/CPF) blocks are busy."
+  ></metric>
+  <metric
+    name="GRBM_SPI_BUSY" block=GRBM event=11 descr="Any of the Shader Pipe Interpolators (SPI) are busy in the shader engine(s)."
+  ></metric>
+  <metric
+    name="GRBM_TA_BUSY" block=GRBM event=13 descr="Any of the Texture Pipes (TA) are busy in the shader engine(s)."
+  ></metric>
+  <metric
+    name="GRBM_TC_BUSY" block=GRBM event=28 descr="Any of the Texture Cache Blocks (TCP/TCI/TCA/TCC) are busy."
+  ></metric>
+  <metric
+    name="GRBM_CPC_BUSY" block=GRBM event=30 descr="The Command Processor Compute (CPC) is busy."
+  ></metric>
+  <metric
+    name="GRBM_CPF_BUSY" block=GRBM event=31 descr="The Command Processor Fetchers (CPF) is busy."
+  ></metric>
+  <metric
+    name="GRBM_UTCL2_BUSY" block=GRBM event=34 descr="The Unified Translation Cache Level-2 (UTCL2) block is busy."
+  ></metric>
+  <metric
+    name="GRBM_EA_BUSY" block=GRBM event=35 descr="The Efficiency Arbiter (EA) block is busy."
+  ></metric>
+  # SPI counters
+  <metric
+    name="SPI_CSN_WINDOW_VALID" block=SPI event=47 descr="Clock count enabled by perfcounter_start event. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  <metric
+    name="SPI_CSN_BUSY" block=SPI event=48 descr="Number of clocks with outstanding waves (SPI or SH). Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  <metric
+    name="SPI_CSN_NUM_THREADGROUPS" block=SPI event=49 descr="Number of threadgroups launched. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  <metric
+    name="SPI_CSN_WAVE" block=SPI event=52 descr="Number of waves. Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  <metric
+    name="SPI_RA_REQ_NO_ALLOC" block=SPI event=79 descr="Arb cycles with requests but no allocation. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_REQ_NO_ALLOC_CSN" block=SPI event=85 descr="Arb cycles with CSn req and no CSn alloc. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_RES_STALL_CSN" block=SPI event=91 descr="Arb cycles with CSn req and no CSn fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_TMP_STALL_CSN" block=SPI event=97 descr="Cycles where csn wants to req but does not fit in temp space."
+  ></metric>
+  <metric
+    name="SPI_RA_WAVE_SIMD_FULL_CSN" block=SPI event=103 descr="Sum of SIMD where WAVE can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_VGPR_SIMD_FULL_CSN" block=SPI event=109 descr="Sum of SIMD where VGPR can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_SGPR_SIMD_FULL_CSN" block=SPI event=115 descr="Sum of SIMD where SGPR can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_LDS_CU_FULL_CSN" block=SPI event=120 descr="Sum of CU where LDS can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_BAR_CU_FULL_CSN" block=SPI event=123 descr="Sum of CU where BARRIER can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_BULKY_CU_FULL_CSN" block=SPI event=125 descr="Sum of CU where BULKY can't take csn wave when !fits. Source is RA0"
+  ></metric>
+  <metric
+    name="SPI_RA_TGLIM_CU_FULL_CSN" block=SPI event=127 descr="Cycles where csn wants to req but all CU are at tg_limit"
+  ></metric>
+  <metric
+    name="SPI_RA_WVLIM_STALL_CSN" block=SPI event=133 descr="Number of clocks csn is stalled due to WAVE LIMIT."
+  ></metric>
+  <metric
+    name="SPI_SWC_CSC_WR" block=SPI event=189 descr="Number of clocks to write CSC waves to SGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  <metric
+    name="SPI_VWC_CSC_WR" block=SPI event=195 descr="Number of clocks to write CSC waves to VGPRs (need to multiply this value by 4) Requires SPI_DEBUG_CNTL.DEBUG_PIPE_SEL to select source, DEBUG_PIPE_SEL = 1, source is CS1; DEBUG_PIPE_SEL = 2, source is CS2; DEBUG_PIPE_SEL = 3, source is CS3; default, source is CS0;"
+  ></metric>
+  # SQ counters
+  <metric
+    name="SQ_ACCUM_PREV" block=SQ event=1 descr="For counter N, increment by the value of counter N-1. Only accumulates once every 4 cycles."
+  ></metric>
+  <metric
+    name="SQ_CYCLES" block=SQ event=2 descr="Clock cycles. (nondeterministic, per-simd, global)"
+  ></metric>
+  <metric
+    name="SQ_BUSY_CYCLES" block=SQ event=3 descr="Clock cycles while SQ is reporting that it is busy. (nondeterministic, per-simd, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES" block=SQ event=4 descr="Count number of waves sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_LEVEL_WAVES" block=SQ event=5 descr="Track the number of waves. Set ACCUM_PREV for the next counter to use this. (level, per-simd, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_EQ_64" block=SQ event=6 descr="Count number of waves with exactly 64 active threads sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_LT_64" block=SQ event=7 descr="Count number of waves with <64 active threads sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_LT_48" block=SQ event=8 descr="Count number of waves with <48 active threads sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_LT_32" block=SQ event=9 descr="Count number of waves sent <32 active threads sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_LT_16" block=SQ event=10 descr="Count number of waves sent <16 active threads sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_BUSY_CU_CYCLES" block=SQ event=13 descr="Count quad-cycles each CU is busy. (nondeterministic, per-simd)"
+  ></metric>
+  <metric
+    name="SQ_ITEMS" block=SQ event=14 descr="Number of valid items per wave. (per-simd, global)"
+  ></metric>
+  <metric
+    name="SQ_INSTS" block=SQ event=25 descr="Number of instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_VALU" block=SQ event=26 descr="Number of VALU instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_MFMA" block=SQ event=27 descr="Number of MFMA instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_VMEM_WR" block=SQ event=28 descr="Number of VMEM write instructions issued (including FLAT). (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_VMEM_RD" block=SQ event=29 descr="Number of VMEM read instructions issued (including FLAT). (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_VMEM" block=SQ event=30 descr="Number of VMEM instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_SALU" block=SQ event=31 descr="Number of SALU instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_SMEM" block=SQ event=32 descr="Number of SMEM instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_FLAT" block=SQ event=33 descr="Number of FLAT instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_FLAT_LDS_ONLY" block=SQ event=34 descr="Number of FLAT instructions issued that read/wrote only from/to LDS (only works if EARLY_TA_DONE is enabled). (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_LDS" block=SQ event=35 descr="Number of LDS instructions issued (including FLAT). (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_GDS" block=SQ event=36 descr="Number of GDS instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_EXP_GDS" block=SQ event=38 descr="Number of EXP and GDS instructions issued, excluding skipped export instructions. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_BRANCH" block=SQ event=39 descr="Number of Branch instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_SENDMSG" block=SQ event=40 descr="Number of Sendmsg instructions issued. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_VSKIPPED" block=SQ event=41 descr="Number of vector instructions skipped. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INST_LEVEL_VMEM" block=SQ event=42 descr="Number of in-flight VMEM instructions. Set next counter to ACCUM_PREV and divide by INSTS_VMEM for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_INST_LEVEL_SMEM" block=SQ event=43 descr="Number of in-flight SMEM instructions (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). Set next counter to ACCUM_PREV and divide by INSTS_SMEM for average latency per smem request. Falls slightly short of total request latency because some fetches are divided into two requests that may finish at different times and this counter collects the average latency of the two. (per-simd, level, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_INST_LEVEL_LDS" block=SQ event=44 descr="Number of in-flight LDS instructions. Set next counter to ACCUM_PREV and divide by INSTS_LDS for average latency. Includes FLAT instructions. (per-simd, level, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_WAVE_CYCLES" block=SQ event=47 descr="Number of wave-cycles spent by waves in the CUs (per-simd, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_WAIT_ANY" block=SQ event=58 descr="Number of wave-cycles spent waiting for anything (per-simd, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_WAIT_INST_ANY" block=SQ event=61 descr="Number of wave-cycles spent waiting for any instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_WAIT_INST_LDS" block=SQ event=64 descr="Number of wave-cycles spent waiting for LDS instruction issue. In units of 4 cycles. (per-simd, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_ANY" block=SQ event=69 descr="Number of cycles each wave is working on an instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_VMEM" block=SQ event=70 descr="Number of cycles the SQ instruction arbiter is working on a VMEM instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_LDS" block=SQ event=71 descr="Number of cycles the SQ instruction arbiter is working on a LDS instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_VALU" block=SQ event=72 descr="Number of cycles the SQ instruction arbiter is working on a VALU instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_SCA" block=SQ event=73 descr="Number of cycles the SQ instruction arbiter is working on a SALU or SMEM instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_EXP_GDS" block=SQ event=74 descr="Number of cycles the SQ instruction arbiter is working on an EXPORT or GDS instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_MISC" block=SQ event=75 descr="Number of cycles the SQ instruction aribter is working on a BRANCH or SENDMSG instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACTIVE_INST_FLAT" block=SQ event=76 descr="Number of cycles the SQ instruction arbiter is working on a FLAT instruction. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INST_CYCLES_VMEM_WR" block=SQ event=77 descr="Number of cycles needed to send addr and cmd data for VMEM write instructions. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INST_CYCLES_VMEM_RD" block=SQ event=78 descr="Number of cycles needed to send addr and cmd data for VMEM read instructions. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INST_CYCLES_SMEM" block=SQ event=84 descr="Number of cycles needed to execute scalar memory reads. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_INST_CYCLES_SALU" block=SQ event=85 descr="Number of cycles needed to execute non-memory read scalar operations. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_THREAD_CYCLES_VALU" block=SQ event=86 descr="Number of thread-cycles used to execute VALU operations (similar to INST_CYCLES_VALU but multiplied by # of active threads). (per-simd)"
+  ></metric>
+  <metric
+    name="SQ_IFETCH" block=SQ event=88 descr="Number of instruction fetch requests from cache. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_IFETCH_LEVEL" block=SQ event=89 descr="Number of instruction fetch requests from cache. (per-simd, level)"
+  ></metric>
+  <metric
+    name="SQ_LDS_BANK_CONFLICT" block=SQ event=94 descr="Number of cycles LDS is stalled by bank conflicts. (emulated)"
+  ></metric>
+  <metric
+    name="SQ_LDS_ADDR_CONFLICT" block=SQ event=95 descr="Number of cycles LDS is stalled by address conflicts. (emulated,nondeterministic)"
+  ></metric>
+  <metric
+    name="SQ_LDS_UNALIGNED_STALL" block=SQ event=96 descr="Number of cycles LDS is stalled processing flat unaligned load/store ops. (emulated)"
+  ></metric>
+  <metric
+    name="SQ_LDS_MEM_VIOLATIONS" block=SQ event=97 descr="Number of threads that have a memory violation in the LDS.(emulated)"
+  ></metric>
+  <metric
+    name="SQ_LDS_ATOMIC_RETURN" block=SQ event=98 descr="Number of atomic return cycles in LDS. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_LDS_IDX_ACTIVE" block=SQ event=99 descr="Number of cycles LDS is used for indexed (non-direct,non-interpolation) operations. (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQ_ACCUM_PREV_HIRES" block=SQ event=158 descr="For counter N, increment by the value of counter N-1."
+  ></metric>
+  <metric
+    name="SQ_WAVES_RESTORED" block=SQ event=159 descr="Count number of context-restored waves sent to SQs. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_WAVES_SAVED" block=SQ event=160 descr="Count number of context-saved waves. (per-simd, emulated, global)"
+  ></metric>
+  <metric
+    name="SQ_INSTS_SMEM_NORM" block=SQ event=161 descr="Number of SMEM instructions issued normalized to match smem_level (*2 load/store; *2 atomic; *2 memtime; *4 wb/inv). (per-simd, emulated)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_INPUT_VALID_READYB" block=SQ event=260 descr="Input stalled by SQC (per-SQ, nondeterministic, unwindowed)"
+  ></metric>
+  <metric
+    name="SQC_TC_REQ" block=SQ event=262 descr="Total number of TC requests that were issued by instruction and constant caches. (No-Masking, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_TC_INST_REQ" block=SQ event=263 descr="Number of insruction requests to the TC (No-Masking, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_TC_DATA_READ_REQ" block=SQ event=264 descr="Number of data read requests to the TC (No-Masking, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_TC_DATA_WRITE_REQ" block=SQ event=265 descr="Number of data write requests to the TC (No-Masking, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_TC_DATA_ATOMIC_REQ" block=SQ event=266 descr="Number of data atomic requests to the TC (No-Masking, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_TC_STALL" block=SQ event=267 descr="Valid request stalled TC request interface (no-credits). (No-Masking, nondeterministic, unwindowed)"
+  ></metric>
+  <metric
+    name="SQC_ICACHE_REQ" block=SQ event=270 descr="Number of requests. (per-SQ, per-Bank)"
+  ></metric>
+  <metric
+    name="SQC_ICACHE_HITS" block=SQ event=271 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_ICACHE_MISSES" block=SQ event=272 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_ICACHE_MISSES_DUPLICATE" block=SQ event=273 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ" block=SQ event=290 descr="Number of requests (post-bank-serialization). (per-SQ, per-Bank)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_HITS" block=SQ event=291 descr="Number of cache hits. (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_MISSES" block=SQ event=292 descr="Number of cache misses, includes uncached requests. (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_MISSES_DUPLICATE" block=SQ event=293 descr="Number of misses that were duplicates (access to a non-resident, miss pending CL). (per-SQ, per-Bank, nondeterministic)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_ATOMIC" block=SQ event=298 descr="Number of atomic requests. (per-SQ, per-Bank)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ_READ_1" block=SQ event=323 descr="Number of constant cache 1 dw read requests. (per-SQ)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ_READ_2" block=SQ event=324 descr="Number of constant cache 2 dw read requests. (per-SQ)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ_READ_4" block=SQ event=325 descr="Number of constant cache 4 dw read requests. (per-SQ)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ_READ_8" block=SQ event=326 descr="Number of constant cache 8 dw read requests. (per-SQ)"
+  ></metric>
+  <metric
+    name="SQC_DCACHE_REQ_READ_16" block=SQ event=327 descr="Number of constant cache 16 dw read requests. (per-SQ)"
+  ></metric>
+  # TA counters
+  <metric
+    name="TA_TA_BUSY" block=TA event=15 descr="TA block is busy. Perf_Windowing not supported for this counter."
+  ></metric>
+  <metric
+    name="TA_TOTAL_WAVEFRONTS" block=TA event=32 descr="Total number of wavefronts processed by TA."
+  ></metric>
+  <metric
+    name="TA_BUFFER_WAVEFRONTS" block=TA event=44 descr="Number of buffer wavefronts processed by TA."
+  ></metric>
+  <metric
+    name="TA_BUFFER_READ_WAVEFRONTS" block=TA event=45 descr="Number of buffer read wavefronts processed by TA."
+  ></metric>
+  <metric
+    name="TA_BUFFER_WRITE_WAVEFRONTS" block=TA event=46 descr="Number of buffer write wavefronts processed by TA."
+  ></metric>
+  <metric
+    name="TA_BUFFER_ATOMIC_WAVEFRONTS" block=TA event=47 descr="Number of buffer atomic wavefronts processed by TA."
+  ></metric>
+  <metric
+    name="TA_BUFFER_TOTAL_CYCLES" block=TA event=49 descr="Number of buffer cycles issued to TC."
+  ></metric>
+  <metric
+    name="TA_BUFFER_COALESCED_READ_CYCLES" block=TA event=52 descr="Number of buffer coalesced read cycles issued to TC."
+  ></metric>
+  <metric
+    name="TA_BUFFER_COALESCED_WRITE_CYCLES" block=TA event=53 descr="Number of buffer coalesced write cycles issued to TC."
+  ></metric>
+  <metric
+    name="TA_ADDR_STALLED_BY_TC_CYCLES" block=TA event=54 descr="Number of cycles addr path stalled by TC. Perf_Windowing not supported for this counter."
+  ></metric>
+  <metric
+    name="TA_ADDR_STALLED_BY_TD_CYCLES" block=TA event=55 descr="Number of cycles addr path stalled by TD. Perf_Windowing not supported for this counter."
+  ></metric>
+  <metric
+    name="TA_DATA_STALLED_BY_TC_CYCLES" block=TA event=56 descr="Number of cycles data path stalled by TC. Perf_Windowing not supported for this counter."
+  ></metric>
+  <metric
+    name="TA_FLAT_WAVEFRONTS" block=TA event=100 descr="Number of flat opcode wavfronts processed by the TA."
+  ></metric>
+  <metric
+    name="TA_FLAT_READ_WAVEFRONTS" block=TA event=101 descr="Number of flat opcode reads processed by the TA."
+  ></metric>
+  <metric
+    name="TA_FLAT_WRITE_WAVEFRONTS" block=TA event=102 descr="Number of flat opcode writes processed by the TA."
+  ></metric>
+  <metric
+    name="TA_FLAT_ATOMIC_WAVEFRONTS" block=TA event=103 descr="Number of flat opcode atomics processed by the TA."
+  ></metric>
+  # TCA counters
+  <metric
+    name="TCA_CYCLE" block=TCA event=1 descr="Number of cycles. Not windowable."
+  ></metric>
+  <metric
+    name="TCA_BUSY" block=TCA event=2 descr="Number of cycles we have a request pending. Not windowable."
+  ></metric>
+  # TCC counters
+  <metric
+    name="TCC_CYCLE" block=TCC event=1 descr="Number of cycles. Not windowable."
+  ></metric>
+  <metric
+    name="TCC_BUSY" block=TCC event=2 descr="Number of cycles we have a request pending. Not windowable."
+  ></metric>
+  <metric
+    name="TCC_REQ" block=TCC event=3 descr="Number of requests of all types. This is measured at the tag block. This may be more than the number of requests arriving at the TCC, but it is a good indication of the total amount of work that needs to be performed."
+  ></metric>
+  <metric
+    name="TCC_STREAMING_REQ" block=TCC event=4 descr="Number of streaming requests. This is measured at the tag block."
+  ></metric>
+  <metric
+    name="TCC_NC_REQ" block=TCC event=5 descr="The number of noncoherently cached requests. This is measured at the tag block."
+  ></metric>
+  <metric
+    name="TCC_UC_REQ" block=TCC event=6 descr="The number of uncached requests. This is measured at the tag block."
+  ></metric>
+  <metric
+    name="TCC_CC_REQ" block=TCC event=7 descr="The number of coherently cached requests. This is measured at the tag block."
+  ></metric>
+  <metric
+    name="TCC_RW_REQ" block=TCC event=8 descr="The number of RW requests. This is measured at the tag block."
+  ></metric>
+  <metric
+    name="TCC_PROBE" block=TCC event=9 descr="Number of probe requests. Not windowable."
+  ></metric>
+  <metric
+    name="TCC_PROBE_ALL" block=TCC event=10 descr="Number of external probe requests with with EA_TCC_preq_all== 1. Not windowable."
+  ></metric>
+  <metric
+    name="TCC_READ" block=TCC event=12 descr="Number of read requests. Compressed reads are included in this, but metadata reads are not included."
+  ></metric>
+  <metric
+    name="TCC_WRITE" block=TCC event=13 descr="Number of write requests."
+  ></metric>
+  <metric
+    name="TCC_ATOMIC" block=TCC event=14 descr="Number of atomic requests of all types."
+  ></metric>
+  <metric
+    name="TCC_HIT" block=TCC event=17 descr="Number of cache hits."
+  ></metric>
+  <metric
+    name="TCC_MISS" block=TCC event=19 descr="Number of cache misses. UC reads count as misses."
+  ></metric>
+  <metric
+    name="TCC_WRITEBACK" block=TCC event=22 descr="Number of lines written back to main memory. This includes writebacks of dirty lines and uncached write/atomic requests."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ" block=TCC event=26 descr="Number of transactions (either 32-byte or 64-byte) going over the TC_EA_wrreq interface. Atomics may travel over the same interface and are generally classified as write requests. This does not include probe commands."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_64B" block=TCC event=27 descr="Number of 64-byte transactions going (64-byte write or CMPSWAP) over the TC_EA_wrreq interface."
+  ></metric>
+  <metric
+    name="TCC_EA_WR_UNCACHED_32B" block=TCC event=29 descr="Number of 32-byte write/atomic going over the TC_EA_wrreq interface due to uncached traffic. Note that CC mtypes can produce uncached requests, and those are included in this. A 64-byte request will be counted as 2"
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_STALL" block=TCC event=30 descr="Number of cycles a write request was stalled."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_IO_CREDIT_STALL" block=TCC event=31 descr="Number of cycles a EA write request was stalled because the interface was out of IO credits."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_GMI_CREDIT_STALL" block=TCC event=32 descr="Number of cycles a EA write request was stalled because the interface was out of GMI credits."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_DRAM_CREDIT_STALL" block=TCC event=33 descr="Number of cycles a EA write request was stalled because the interface was out of DRAM credits."
+  ></metric>
+  <metric
+    name="TCC_TOO_MANY_EA_WRREQS_STALL" block=TCC event=34 descr="Number of cycles the TCC could not send a EA write request because it already reached its maximum number of pending EA write requests."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_LEVEL" block=TCC event=35 descr="The sum of the number of EA write requests in flight. This is primarily meant for measure average EA write latency. Average write latency = TCC_PERF_SEL_EA_WRREQ_LEVEL/TCC_PERF_SEL_EA_WRREQ."
+  ></metric>
+  <metric
+    name="TCC_EA_ATOMIC" block=TCC event=36 descr="Number of transactions going over the TC_EA_wrreq interface that are actually atomic requests."
+  ></metric>
+  <metric
+    name="TCC_EA_ATOMIC_LEVEL" block=TCC event=37 descr="The sum of the number of EA atomics in flight. This is primarily meant for measure average EA atomic latency. Average atomic latency = TCC_PERF_SEL_EA_WRREQ_ATOMIC_LEVEL/TCC_PERF_SEL_EA_WRREQ_ATOMIC."
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ" block=TCC event=38 descr="Number of TCC/EA read requests (either 32-byte or 64-byte)"
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_32B" block=TCC event=39 descr="Number of 32-byte TCC/EA read requests"
+  ></metric>
+  <metric
+    name="TCC_EA_RD_UNCACHED_32B" block=TCC event=40 descr="Number of 32-byte TCC/EA read due to uncached traffic. A 64-byte request will be counted as 2"
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_IO_CREDIT_STALL" block=TCC event=41 descr="Number of cycles there was a stall because the read request interface was out of IO credits. Stalls occur regardless of whether a read needed to be performed or not."
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_GMI_CREDIT_STALL" block=TCC event=42 descr="Number of cycles there was a stall because the read request interface was out of GMI credits. Stalls occur regardless of whether a read needed to be performed or not."
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_DRAM_CREDIT_STALL" block=TCC event=43 descr="Number of cycles there was a stall because the read request interface was out of DRAM credits. Stalls occur regardless of whether a read needed to be performed or not."
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_LEVEL" block=TCC event=44 descr="The sum of the number of TCC/EA read requests in flight. This is primarily meant for measure average EA read latency. Average read latency = TCC_PERF_SEL_EA_RDREQ_LEVEL/TCC_PERF_SEL_EA_RDREQ."
+  ></metric>
+  <metric
+    name="TCC_TAG_STALL" block=TCC event=45 descr="Number of cycles the normal request pipeline in the tag was stalled for any reason. Normally, stalls of this nature are measured exactly from one point the pipeline, but that is not the case for this counter. Probes can stall the pipeline at a variety of places, and there is no single point that can reasonably measure the total stalls accurately."
+  ></metric>
+  <metric
+    name="TCC_NORMAL_WRITEBACK" block=TCC event=68 descr="Number of writebacks due to requests that are not writeback requests."
+  ></metric>
+  <metric
+    name="TCC_ALL_TC_OP_WB_WRITEBACK" block=TCC event=73 descr="Number of writebacks due to all TC_OP writeback requests."
+  ></metric>
+  <metric
+    name="TCC_NORMAL_EVICT" block=TCC event=74 descr="Number of evictions due to requests that are not invalidate or probe requests."
+  ></metric>
+  <metric
+    name="TCC_ALL_TC_OP_INV_EVICT" block=TCC event=80 descr="Number of evictions due to all TC_OP invalidate requests."
+  ></metric>
+  <metric
+    name="TCC_EA_RDREQ_DRAM" block=TCC event=102 descr="Number of TCC/EA read requests (either 32-byte or 64-byte) destined for DRAM (MC)."
+  ></metric>
+  <metric
+    name="TCC_EA_WRREQ_DRAM" block=TCC event=103 descr="Number of TCC/EA write requests (either 32-byte of 64-byte) destined for DRAM (MC)."
+  ></metric>
+  <metric
+    name="TCC_CLIENT184_REQ" block=TCC event=312 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT185_REQ" block=TCC event=313 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT186_REQ" block=TCC event=314 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT187_REQ" block=TCC event=315 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT188_REQ" block=TCC event=316 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT189_REQ" block=TCC event=317 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT190_REQ" block=TCC event=318 descr=""
+  ></metric>
+  <metric
+    name="TCC_CLIENT191_REQ" block=TCC event=319 descr=""
+  ></metric>
+  # TCP counters
+  <metric
+    name="TCP_GATE_EN1" block=TCP event=0 descr="TCP interface clocks are turned on. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_GATE_EN2" block=TCP event=1 descr="TCP core clocks are turned on. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_TCP_TA_DATA_STALL_CYCLES" block=TCP event=6 descr="TCP stalls TA data interface. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_TD_TCP_STALL_CYCLES" block=TCP event=7 descr="TD stalls TCP"
+  ></metric>
+  <metric
+    name="TCP_TCR_TCP_STALL_CYCLES" block=TCP event=8 descr="TCR stalls TCP_TCR_req interface"
+  ></metric>
+  <metric
+    name="TCP_READ_TAGCONFLICT_STALL_CYCLES" block=TCP event=11 descr="Tagram conflict stall on a read"
+  ></metric>
+  <metric
+    name="TCP_WRITE_TAGCONFLICT_STALL_CYCLES" block=TCP event=12 descr="Tagram conflict stall on a write"
+  ></metric>
+  <metric
+    name="TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES" block=TCP event=13 descr="Tagram conflict stall on an atomic"
+  ></metric>
+  <metric
+    name="TCP_PENDING_STALL_CYCLES" block=TCP event=22 descr="Stall due to data pending from L2"
+  ></metric>
+  <metric
+    name="TCP_TA_TCP_STATE_READ" block=TCP event=27 descr="Number of state reads"
+  ></metric>
+  <metric
+    name="TCP_VOLATILE" block=TCP event=28 descr="Total number of L1 volatile pixels/buffers from TA"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_ACCESSES" block=TCP event=29 descr="Total number of pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_READ+TCP_PERF_SEL_TOTAL_NONREAD"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_READ" block=TCP event=30 descr="Total number of read pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_HIT_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_LRU_READ + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_WRITE" block=TCP event=32 descr="Total number of local write pixels/buffers from TA. Equals TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE+ TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_ATOMIC_WITH_RET" block=TCP event=38 descr="Total number of atomic with return pixels/buffers from TA"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_ATOMIC_WITHOUT_RET" block=TCP event=39 descr="Total number of atomic without return pixels/buffers from TA"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_WRITEBACK_INVALIDATES" block=TCP event=45 descr="Total number of cache invalidates. Equals TCP_PERF_SEL_TOTAL_WBINVL1+ TCP_PERF_SEL_TOTAL_WBINVL1_VOL+ TCP_PERF_SEL_CP_TCP_INVALIDATE+ TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_UTCL1_REQUEST" block=TCP event=47 descr="Total CLIENT_UTCL1 NORMAL requests"
+  ></metric>
+  <metric
+    name="TCP_UTCL1_TRANSLATION_MISS" block=TCP event=48 descr="Total utcl1 translation misses"
+  ></metric>
+  <metric
+    name="TCP_UTCL1_TRANSLATION_HIT" block=TCP event=49 descr="Total utcl1 translation hits"
+  ></metric>
+  <metric
+    name="TCP_UTCL1_PERMISSION_MISS" block=TCP event=50 descr="Total utcl1 permission misses"
+  ></metric>
+  <metric
+    name="TCP_TOTAL_CACHE_ACCESSES" block=TCP event=60 descr="Count of total cache line (tag) accesses (includes hits and misses)."
+  ></metric>
+  <metric
+    name="TCP_TCP_LATENCY" block=TCP event=65 descr="Total TCP wave latency (from first clock of wave entering to first clock of wave leaving), divide by TA_TCP_STATE_READ to avg wave latency"
+  ></metric>
+  <metric
+    name="TCP_TCC_READ_REQ_LATENCY" block=TCP event=66 descr="Total TCP->TCC request latency for reads and atomics with return. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_TCC_WRITE_REQ_LATENCY" block=TCP event=67 descr="Total TCP->TCC request latency for writes and atomics without return. Not Windowed."
+  ></metric>
+  <metric
+    name="TCP_TCC_READ_REQ" block=TCP event=69 descr="Total read requests from TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_WRITE_REQ" block=TCP event=70 descr="Total write requests from TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_ATOMIC_WITH_RET_REQ" block=TCP event=71 descr="Total atomic with return requests from TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_ATOMIC_WITHOUT_RET_REQ" block=TCP event=72 descr="Total atomic without return requests from TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_NC_READ_REQ" block=TCP event=75 descr="Total read requests with NC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_NC_WRITE_REQ" block=TCP event=76 descr="Total write requests with NC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_NC_ATOMIC_REQ" block=TCP event=77 descr="Total atomic requests with NC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_UC_READ_REQ" block=TCP event=78 descr="Total read requests with UC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_UC_WRITE_REQ" block=TCP event=79 descr="Total write requests with UC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_UC_ATOMIC_REQ" block=TCP event=80 descr="Total atomic requests with UC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_CC_READ_REQ" block=TCP event=81 descr="Total write requests with CC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_CC_WRITE_REQ" block=TCP event=82 descr="Total write requests with CC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_CC_ATOMIC_REQ" block=TCP event=83 descr="Total atomic requests with CC mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_RW_READ_REQ" block=TCP event=85 descr="Total write requests with RW mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_RW_WRITE_REQ" block=TCP event=86 descr="Total write requests with RW mtype from this TCP to all TCCs"
+  ></metric>
+  <metric
+    name="TCP_TCC_RW_ATOMIC_REQ" block=TCP event=87 descr="Total atomic requests with RW mtype from this TCP to all TCCs"
+  ></metric>
+  # TD counters
+  <metric
+    name="TD_TD_BUSY" block=TD event=1 descr="TD is processing or waiting for data. Perf_Windowing not supported for this counter."
+  ></metric>
+  <metric
+    name="TD_TC_STALL" block=TD event=15 descr="TD is stalled waiting for TC data."
+  ></metric>
+  <metric
+    name="TD_RESERVED_18" block=TD event=18 descr="RESERVED_18"
+  ></metric>
+  <metric
+    name="TD_LOAD_WAVEFRONT" block=TD event=25 descr="Count the wavefronts with opcode = load, include atomics and store."
+  ></metric>
+  <metric
+    name="TD_ATOMIC_WAVEFRONT" block=TD event=26 descr="Count the wavefronts with opcode = atomic."
+  ></metric>
+  <metric
+    name="TD_STORE_WAVEFRONT" block=TD event=27 descr="Count the wavefronts with opcode = store."
+  ></metric>
+  <metric
+    name="TD_COALESCABLE_WAVEFRONT" block=TD event=32 descr="Count wavefronts that TA finds coalescable."
+  ></metric>
+</gfx908>

src/omniperf_soc/profile_configs/gfx90a/pmc_cpc_perf.txt

@@ -0,0 +1,15 @@
+pmc: GRBM_COUNT  GRBM_GUI_ACTIVE        SQ_CYCLES       SQ_BUSY_CYCLES      SQ_WAVES     
+
+pmc: CPC_CPC_STAT_BUSY      CPC_CPC_STAT_IDLE
+pmc: CPC_CPC_TCIU_BUSY      CPC_CPC_TCIU_IDLE
+pmc: CPC_CPC_STAT_STALL     CPC_UTCL1_STALL_ON_TRANSLATION                   
+pmc: CPC_CPC_UTCL2IU_BUSY    CPC_CPC_UTCL2IU_IDLE    
+pmc: CPC_CPC_UTCL2IU_STALL   CPC_ME1_BUSY_FOR_PACKET_DECODE  
+pmc: CPC_ME1_DC0_SPI_BUSY
+
+range:
+gpu: 
+
+kernel: 
+
+

src/omniperf_soc/profile_configs/gfx90a/pmc_cpf_perf.txt

@@ -0,0 +1,13 @@
+pmc: GRBM_COUNT                 GRBM_GUI_ACTIVE                 SQ_CYCLES                       SQ_BUSY_CYCLES                  SQ_WAVES         
+
+pmc: CPF_CPF_STAT_BUSY                          CPF_CPF_STAT_STALL
+pmc: CPF_CPF_TCIU_BUSY                          CPF_CPF_TCIU_STALL
+pmc: CPF_CPF_STAT_IDLE                          CPF_CPF_TCIU_IDLE
+pmc: CPF_CMP_UTCL1_STALL_ON_TRANSLATION          
+
+range: 
+gpu: 
+
+kernel: 
+
+