diff --git a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp index bcaf4a0738..dff9bee690 100644 --- a/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp +++ b/projects/clr/rocclr/compiler/lib/utils/v0_8/libUtils.cpp @@ -18,6 +18,8 @@ static const std::string sgfx700 = "AMD:AMDGPU:7:0:0"; static const std::string sgfx701 = "AMD:AMDGPU:7:0:1"; static const std::string sgfx800 = "AMD:AMDGPU:8:0:0"; static const std::string sgfx801 = "AMD:AMDGPU:8:0:1"; +static const std::string sgfx802 = "AMD:AMDGPU:8:0:2"; +static const std::string sgfx803 = "AMD:AMDGPU:8:0:3"; static const std::string sgfx804 = "AMD:AMDGPU:8:0:4"; static const std::string sgfx810 = "AMD:AMDGPU:8:1:0"; static const std::string sgfx900 = "AMD:AMDGPU:9:0:0"; @@ -518,6 +520,8 @@ const std::string &getIsaTypeName(const aclTargetInfo *target) case 701: return sgfx701; case 800: return sgfx800; case 801: return sgfx801; + case 802: return sgfx802; + case 803: return sgfx803; case 804: return sgfx804; case 810: return sgfx810; case 900: return sgfx900; @@ -553,11 +557,19 @@ int getIsaType(const aclTargetInfo *target) case FAMILY_VI: switch (Mapping.chip_enum) { default: return 800; - case VI_ICELAND_M_A0: - case VI_TONGA_P_A0: return 800; + case VI_TONGA_P_A0: +#if defined(BUILD_HSA_TARGET) + return 802; // Special case - Boltzmann Tonga + // Otherwise fall through +#endif + case VI_ICELAND_M_A0: return 800; + case VI_FIJI_P_A0: +#if defined(BUILD_HSA_TARGET) + return 803; // Special case - Boltzmann Fiji + // Otherwise fall through +#endif case VI_ELLESMERE_P_A0: case VI_BAFFIN_M_A0: - case VI_FIJI_P_A0: case VI_LEXA_V_A0: return 804; } case FAMILY_CZ: diff --git a/projects/clr/rocclr/runtime/device/rocm/rocprogram.cpp b/projects/clr/rocclr/runtime/device/rocm/rocprogram.cpp index f82c5be363..e5d04c08fe 100644 --- a/projects/clr/rocclr/runtime/device/rocm/rocprogram.cpp +++ b/projects/clr/rocclr/runtime/device/rocm/rocprogram.cpp @@ -1216,6 +1216,7 @@ HSAILProgram::linkImpl(amd::option::Options *options) buildLog_ += "Failed to create Brig Container"; return false; } +#if defined(USE_HSART_FINALIZER) // Create a program. hsa_status_t status = hsa_ext_program_create( HSA_MACHINE_MODEL_LARGE, @@ -1274,6 +1275,36 @@ HSAILProgram::linkImpl(amd::option::Options *options) return false; } +#else // ! USE_HSART_FINALIZER + std::string fin_options(options->origOptionStr); + // Append an option so that we can selectively enable a SCOption on CZ + // whenever IOMMUv2 is enabled. + if (dev().isFineGrainedSystem(true)) { + fin_options.append(" -sc-xnack-iommu"); + } + errorCode = aclCompile(dev().compiler(), binaryElf_, + fin_options.c_str(), ACL_TYPE_CG, ACL_TYPE_ISA, logFunction); + buildLog_ += aclGetCompilerLog(dev().compiler()); + if (errorCode != ACL_SUCCESS) { + buildLog_ += "Error: BRIG finalization to ISA failed.\n"; + return false; + } + size_t secSize; + void *data = (void*)aclExtractSection(device().compiler(), + binaryElf_, &secSize, aclTEXT, &errorCode); + if (errorCode != ACL_SUCCESS) { + buildLog_ += "Error: cannot extract ISA from compiled binary.\n"; + return false; + } + hsa_status_t status = hsa_code_object_deserialize(data, secSize, + NULL, &hsaProgramCodeObject_ ); + if (status != HSA_STATUS_SUCCESS) { + buildLog_ += "Error: failed to load finalized code object.\n"; + return false; + } + +#endif // USE_HSART_FINALIZER + // HLC always generates full profile hsa_profile_t profile = HSA_PROFILE_FULL; @@ -1431,6 +1462,7 @@ HSAILProgram::linkImpl(amd::option::Options *options) saveBinaryAndSetType(TYPE_EXECUTABLE); buildLog_ += g_complibApi._aclGetCompilerLog(device().compiler()); +#if defined(USE_HSART_FINALIZER) if (options->isDumpFlagSet(amd::option::DUMP_O) || options->isDumpFlagSet(amd::option::DUMP_ISA)) { amd::hsa::code::AmdHsaCode code; if (!code.InitAsHandle(hsaProgramCodeObject_)) { @@ -1446,7 +1478,7 @@ HSAILProgram::linkImpl(amd::option::Options *options) } } } - +#endif // defined(USE_HSART_FINALIZER) #endif // !defined(WITH_LIGHTNING_COMPILER) return true; }