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Add CU Utilization and deprecate Active CUs (#1822)

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* ChangeLog

* Deprecation notice in old arch

* Deprecation notice current arch

* New config hash

* Added Config deltas

* Added metric description
This commit is contained in:
abchoudh-amd
2025-11-28 22:02:25 +05:30
committed by GitHub
parent 3f2fbc18e9
commit fd61b0f507
20 changed files with 2522 additions and 1557 deletions
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projects/rocprofiler-compute/CHANGELOG.md
+6
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@@ -53,6 +53,8 @@ Full documentation for ROCm Compute Profiler is available at [https://rocm.docs.
* Adds support for dispatch timeline analysis.
* Shows duration as median in addition to mean in kernel view.
* Added `CU Utilization` metric to display the percentage of CUs utilized during kernel execution.
### Changed
* `-b/--block` accepts block alias(es). See block aliases using command-line option `--list-blocks <arch>`.
@@ -64,6 +66,10 @@ Full documentation for ROCm Compute Profiler is available at [https://rocm.docs.
* Empty cells replaced with `N/A` for unavailable metrics in analysis.
### Deprecated
* `Active CUs` metric has been deprecated and replaced by `CU Utilization`.
### Removed
* Removed `database` mode from ROCm Compute Profiler in favor of other visualization methods, rather than Grafana and MongoDB integration, such as the upcoming Analysis DB-based Visualizer.
projects/rocprofiler-compute/docs/data/metrics_description.yaml
+8 -2
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@@ -1423,9 +1423,9 @@ Command processor packet processor (CPC):
manager <desc-spi>`.
unit: Percent
System Speed-of-Light:
Active CUs:
Active CUs (deprecated):
rst: Total number of active compute units (CUs) on the accelerator during the
kernel execution.
kernel execution. (Deprecated - See CU Utilization instead)
unit: Number
Branch Utilization:
rst: Indicates what percent of the kernel's duration the :ref:`branch <desc-branch>`
@@ -1618,3 +1618,9 @@ System Speed-of-Light:
rst: The ratio of the number of vL1D cache line requests that hit in vL1D cache
over the total number of cache line requests to the :ref:`vL1D cache RAM <desc-tc>`.
unit: Percent
CU Utilization:
rst: The percent of :ref:`total SIMD cycles <total-simd-cycles>` in the kernel
where any :ref:`SIMD <desc-valu>` on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
unit: Percent
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0200_system_speed_of_light.yaml
+12 -3
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@@ -48,7 +48,7 @@ Panel Config:
unit: GIOP/s
peak: ((($max_sclk * $cu_per_gpu) * 1024) / 1000)
pop: None
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -199,6 +199,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -235,8 +240,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -321,3 +326,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/0300_memory_chart.yaml
+3 -3
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@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -167,8 +167,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx908/config_delta/gfx950_diff.yaml
+735 -386
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File diff suppressed because it is too large Load Diff
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0200_system_speed_of_light.yaml
+12 -3
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@@ -64,7 +64,7 @@ Panel Config:
peak: ((($max_sclk * $cu_per_gpu) * 1024) / 1000)
pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp -
Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 1024) / 1000))
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -217,6 +217,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -253,8 +258,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -339,3 +344,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/0300_memory_chart.yaml
+3 -3
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@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -167,8 +167,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx90a/config_delta/gfx950_diff.yaml
+503 -373
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File diff suppressed because it is too large Load Diff
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0200_system_speed_of_light.yaml
+12 -3
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@@ -70,7 +70,7 @@ Panel Config:
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp -
Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -226,6 +226,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -267,8 +272,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -353,3 +358,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/0300_memory_chart.yaml
+3 -3
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@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -159,8 +159,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx940/config_delta/gfx950_diff.yaml
+387 -247
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@@ -22,12 +22,23 @@ Addition:
id: 301
title: Memory Chart
metrics:
- L2 Wr Lat:
value: |
ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else None)), 0)
- L2 Rd Lat:
value: |
ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), 0)
- L2 Wr Lat:
value: |
ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else None)), 0)
metric_descriptions:
L2 Rd Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L2 Wr Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 400
title: Roofline
@@ -41,6 +52,12 @@ Addition:
AVG((((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512)) / ((End_Timestamp - Start_Timestamp) / 1e9)) / 1e9)
unit: GFLOP/s
peak: $MFMA_FLOPs_F6F4_empirical_peak
metric_descriptions:
MFMA FLOPs (F6F4):
plain: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
rst: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
- Panel Config:
id: 500
title: Command Processor (CPC/CPF)
@@ -49,6 +66,16 @@ Addition:
id: 502
title: Command processor packet processor (CPC)
metrics:
- CPC ADC Utilization:
avg: AVG((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
min: MIN((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
max: MAX((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
unit: pct
- CPC CANE Stall Rate:
avg: AVG((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
unit: pct
- CPC SYNC FIFO Full Rate:
avg: |
AVG((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
@@ -57,16 +84,6 @@ Addition:
max: |
MAX((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
unit: pct
- CPC CANE Stall Rate:
avg: AVG((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
unit: pct
- CPC ADC Utilization:
avg: AVG((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
min: MIN((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
max: MAX((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
unit: pct
- Panel Config:
id: 600
title: Workgroup Manager (SPI)
@@ -75,14 +92,6 @@ Addition:
id: 601
title: Workgroup manager utilizations
metrics:
- Scheduler-Pipe Wave Utilization:
avg: |
AVG(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
unit: Pct
- Schedule-Pipe Wave Occupancy:
avg: |
AVG(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY)
@@ -91,6 +100,14 @@ Addition:
max: |
MAX(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY)
unit: Wave
- Scheduler-Pipe Wave Utilization:
avg: |
AVG(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
unit: Pct
- metric_table:
id: 602
title: Workgroup Manager - Resource Allocation
@@ -165,50 +182,64 @@ Addition:
id: 1202
title: LDS Statistics
metrics:
- LDS STORE:
avg: AVG((SQ_INSTS_LDS_STORE / $denom))
min: MIN((SQ_INSTS_LDS_STORE / $denom))
max: MAX((SQ_INSTS_LDS_STORE / $denom))
unit: (instr + $normUnit)
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS ATOMIC:
avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom))
min: MIN((SQ_INSTS_LDS_ATOMIC / $denom))
max: MAX((SQ_INSTS_LDS_ATOMIC / $denom))
unit: (instr + $normUnit)
- LDS STORE Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS LOAD:
avg: AVG((SQ_INSTS_LDS_LOAD / $denom))
min: MIN((SQ_INSTS_LDS_LOAD / $denom))
max: MAX((SQ_INSTS_LDS_LOAD / $denom))
unit: (instr + $normUnit)
- LDS ATOMIC Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS Data FIFO Full Rate:
avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom))
min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom))
max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS LOAD:
avg: AVG((SQ_INSTS_LDS_LOAD / $denom))
min: MIN((SQ_INSTS_LDS_LOAD / $denom))
max: MAX((SQ_INSTS_LDS_LOAD / $denom))
unit: (instr + $normUnit)
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS STORE:
avg: AVG((SQ_INSTS_LDS_STORE / $denom))
min: MIN((SQ_INSTS_LDS_STORE / $denom))
max: MAX((SQ_INSTS_LDS_STORE / $denom))
unit: (instr + $normUnit)
- LDS STORE Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- Panel Config:
id: 1500
title: Address Processing Unit and Data Return Path (TA/TD)
metric_tables:
- metric_table:
id: 1502
title: Instruction counts
metrics:
- Global/Generic Read Instructions for LDS:
avg: AVG((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- Spill/Stack Read Instructions for LDS:
avg: AVG((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1504
title: Vector L1 data-return path or Texture Data (TD)
@@ -218,20 +249,12 @@ Addition:
min: MIN((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
max: MAX((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1502
title: Instruction counts
metrics:
- Spill/Stack Read Instructions for LDS:
avg: AVG((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- Global/Generic Read Instructions for LDS:
avg: AVG((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
metric_descriptions:
Write Ack Instructions:
plain: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
rst: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
- Panel Config:
id: 1600
title: Vector L1 Data Cache
@@ -243,110 +266,126 @@ Addition:
- Stalled on Address:
expr: |
(((100 * TCP_TCP_TA_ADDR_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Data:
expr: |
(((100 * TCP_TCP_TA_DATA_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Latency FIFO:
expr: |
(((100 * TCP_LFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- metric_table:
id: 1603
title: vL1D cache access metrics
metrics:
- Tag RAM 3 Req:
avg: AVG((TCP_TAGRAM3_REQ_sum / $denom))
min: MIN((TCP_TAGRAM3_REQ_sum / $denom))
max: MAX((TCP_TAGRAM3_REQ_sum / $denom))
unit: (Req + $normUnit)
- L1-L2 Read Latency:
avg: AVG((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 2 Req:
avg: AVG((TCP_TAGRAM2_REQ_sum / $denom))
min: MIN((TCP_TAGRAM2_REQ_sum / $denom))
max: MAX((TCP_TAGRAM2_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 0 Req:
avg: AVG((TCP_TAGRAM0_REQ_sum / $denom))
min: MIN((TCP_TAGRAM0_REQ_sum / $denom))
max: MAX((TCP_TAGRAM0_REQ_sum / $denom))
unit: (Req + $normUnit)
- L1-L2 Write Latency:
avg: AVG((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- L1 Access Latency:
avg: AVG((TCP_TCP_LATENCY_sum / $denom))
min: MIN((TCP_TCP_LATENCY_sum / $denom))
max: MAX((TCP_TCP_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- L1-L2 Read Latency:
avg: AVG((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- L1-L2 Write Latency:
avg: AVG((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 0 Req:
avg: AVG((TCP_TAGRAM0_REQ_sum / $denom))
min: MIN((TCP_TAGRAM0_REQ_sum / $denom))
max: MAX((TCP_TAGRAM0_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 1 Req:
avg: AVG((TCP_TAGRAM1_REQ_sum / $denom))
min: MIN((TCP_TAGRAM1_REQ_sum / $denom))
max: MAX((TCP_TAGRAM1_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 2 Req:
avg: AVG((TCP_TAGRAM2_REQ_sum / $denom))
min: MIN((TCP_TAGRAM2_REQ_sum / $denom))
max: MAX((TCP_TAGRAM2_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 3 Req:
avg: AVG((TCP_TAGRAM3_REQ_sum / $denom))
min: MIN((TCP_TAGRAM3_REQ_sum / $denom))
max: MAX((TCP_TAGRAM3_REQ_sum / $denom))
unit: (Req + $normUnit)
- metric_table:
id: 1605
title: L1 Unified Translation Cache (UTCL1)
metrics:
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- Inflight Req:
avg: AVG((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
min: MIN((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
max: MAX((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
units: (Req + $normUnit)
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- metric_table:
id: 1606
title: L1D Addr Translation Stalls
metrics:
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
units: (Cycles + $normUnit)
- Serialization Stall:
avg: AVG((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
min: MIN((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
max: MAX((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Cache Full Stall:
avg: AVG((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
min: MIN((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
max: MAX((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
units: (Cycles + $normUnit)
- UTCL2 Stall:
avg: AVG((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
units: (Cycles + $normUnit)
- Cache Miss Stall:
avg: AVG((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
units: (Cycles + $normUnit)
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
units: (Cycles + $normUnit)
- Resident Page Full Stall:
avg: AVG((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
min: MIN((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
max: MAX((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
units: (Cycles + $normUnit)
- Serialization Stall:
avg: AVG((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
min: MIN((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
max: MAX((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Thrashing Stall:
avg: AVG((TCP_UTCL1_THRASHING_STALL_sum / $denom))
min: MIN((TCP_UTCL1_THRASHING_STALL_sum / $denom))
max: MAX((TCP_UTCL1_THRASHING_STALL_sum / $denom))
units: (Cycles + $normUnit)
- UTCL2 Stall:
avg: AVG((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
units: (Cycles + $normUnit)
metric_descriptions:
L1 Access Latency:
plain: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
rst: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
L1-L2 Read Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L1-L2 Write Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 1700
title: L2 Cache
@@ -355,14 +394,6 @@ Addition:
id: 1702
title: L2-Fabric interface metrics
metrics:
- Write Stall:
avg: |
AVG(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read Stall:
avg: |
AVG((((100 * ((TCC_EA0_RDREQ_IO_CREDIT_STALL_sum + TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum) + TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
@@ -371,35 +402,43 @@ Addition:
max: |
MAX((((100 * ((TCC_EA0_RDREQ_IO_CREDIT_STALL_sum + TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum) + TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write Stall:
avg: |
AVG(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- metric_table:
id: 1703
title: L2 Cache Accesses
metrics:
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Bypasss Req:
avg: AVG((TCC_BYPASS_REQ_sum / $denom))
min: MIN((TCC_BYPASS_REQ_sum / $denom))
max: MAX((TCC_BYPASS_REQ_sum / $denom))
unit: (Req + $normUnit)
- Atomic Bandwidth:
avg: AVG(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Bypasss Req:
avg: AVG((TCC_BYPASS_REQ_sum / $denom))
min: MIN((TCC_BYPASS_REQ_sum / $denom))
max: MAX((TCC_BYPASS_REQ_sum / $denom))
unit: (Req + $normUnit)
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth:
avg: AVG(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- metric_table:
id: 1704
title: L2 Cache Stalls
@@ -423,16 +462,6 @@ Addition:
id: 1705
title: L2 - Fabric Interface stalls
metrics:
- Write - HBM Stall:
type: HBM Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read - HBM Stall:
type: HBM Stall
transaction: Read
@@ -443,26 +472,6 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
type: PCIe Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Read
@@ -483,45 +492,55 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - HBM Stall:
type: HBM Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
type: PCIe Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic - HBM:
avg: AVG((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth - HBM:
avg: AVG(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
- Atomic Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
@@ -532,16 +551,137 @@ Addition:
min: MIN((TCC_EA0_RDREQ_128B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_128B_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth - HBM:
avg: AVG(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
metric_descriptions:
Atomic Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
Atomic Bandwidth - HBM:
plain: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
Atomic Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
Atomic Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
Read - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
Read - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Read - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Read Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
Read Bandwidth - HBM:
plain: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
Read Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
Read Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
Read Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Write - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
Write - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Write - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Write Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
Write Bandwidth - HBM:
plain: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
Write Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
Write Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
Write Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Deletion:
[]
@@ -555,26 +695,26 @@ Modification:
id: 201
title: System Speed-of-Light
metrics:
- MFMA FLOPs (F8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA FLOPs (F64):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
- MFMA IOPs (Int8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA FLOPs (F16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA FLOPs (BF16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA FLOPs (F16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA FLOPs (F64):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
- MFMA FLOPs (F8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA IOPs (Int8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- Panel Config:
id: 300
title: Memory Chart
@@ -596,18 +736,18 @@ Modification:
id: 402
title: Roofline Plot Points
metrics:
- Performance (GFLOPs):
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / (SUM(End_Timestamp - Start_Timestamp) / 1e9) ) / 1e9
- AI L2:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum + TCP_TCC_READ_REQ_sum) * 64 ) )
- AI L1:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM(TCP_TOTAL_CACHE_ACCESSES_sum * 64) )
- AI HBM:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCC_BUBBLE_sum * 128) + (TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32) + (TCC_EA0_WRREQ_64B_sum * 64) ) )
- AI L1:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM(TCP_TOTAL_CACHE_ACCESSES_sum * 64) )
- AI L2:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum + TCP_TCC_READ_REQ_sum) * 64 ) )
- Performance (GFLOPs):
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / (SUM(End_Timestamp - Start_Timestamp) / 1e9) ) / 1e9
- Panel Config:
id: 600
title: Workgroup Manager (SPI)
@@ -616,38 +756,38 @@ Modification:
id: 601
title: Workgroup manager utilizations
metrics:
- SGPR Writes:
max: |
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Dispatched Wavefronts:
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Dispatched Workgroups:
max: |
MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
min: |
MIN(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
avg: |
AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
min: |
MIN(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
- SGPR Writes:
max: |
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Scheduler-Pipe Utilization:
max: |
MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
avg: |
AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
- VGPR Writes:
max: |
MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Panel Config:
id: 700
title: Wavefront
@@ -658,8 +798,8 @@ Modification:
metrics:
- Total Wavefronts:
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Panel Config:
id: 1100
title: Compute Units - Compute Pipeline
@@ -668,6 +808,10 @@ Modification:
id: 1101
title: Compute Speed-of-Light
metrics:
- MFMA FLOPs (BF16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA FLOPs (F16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
@@ -676,18 +820,14 @@ Modification:
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
- MFMA IOPs (INT8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA FLOPs (BF16):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA FLOPs (F8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA IOPs (INT8):
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- metric_table:
id: 1103
title: Arithmetic Operations
@@ -695,10 +835,10 @@ Modification:
- FLOPs (Total):
max: |
MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
min: |
MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
avg: |
AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
min: |
MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
- Panel Config:
id: 1700
title: L2 Cache
@@ -717,22 +857,22 @@ Modification:
- Read BW:
max: |
MAX((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
min: |
MIN((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
avg: |
AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
min: |
MIN((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- Read (64B):
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_64B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
- HBM Write and Atomic:
max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
- Read (64B):
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_64B_sum / $denom))
- Panel Config:
id: 1800
title: L2 Cache (per Channel)
@@ -750,6 +890,6 @@ Modification:
title: L2-Fabric Write and Atomic Stall (Cycles per normUnit)
metrics:
- ::_1:
ea write stall - hbm: AVG((TO_INT(TCC_EA0_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
ea write stall - pcie: AVG((TO_INT(TCC_EA0_WRREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea write stall - if: AVG((TO_INT(TCC_EA0_WRREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea write stall - pcie: AVG((TO_INT(TCC_EA0_WRREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea write stall - hbm: AVG((TO_INT(TCC_EA0_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0200_system_speed_of_light.yaml
+12 -3
View File
@@ -70,7 +70,7 @@ Panel Config:
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp -
Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -226,6 +226,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -267,8 +272,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -353,3 +358,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/0300_memory_chart.yaml
+3 -3
View File
@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -159,8 +159,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx941/config_delta/gfx950_diff.yaml
+384 -244
View File
@@ -28,6 +28,17 @@ Addition:
- L2 Wr Lat:
value: |
ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else None)), 0)
metric_descriptions:
L2 Rd Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L2 Wr Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 400
title: Roofline
@@ -41,6 +52,12 @@ Addition:
AVG((((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512)) / ((End_Timestamp - Start_Timestamp) / 1e9)) / 1e9)
unit: GFLOP/s
peak: $MFMA_FLOPs_F6F4_empirical_peak
metric_descriptions:
MFMA FLOPs (F6F4):
plain: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
rst: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
- Panel Config:
id: 500
title: Command Processor (CPC/CPF)
@@ -49,14 +66,6 @@ Addition:
id: 502
title: Command processor packet processor (CPC)
metrics:
- CPC SYNC FIFO Full Rate:
avg: |
AVG((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
min: |
MIN((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
max: |
MAX((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
unit: pct
- CPC ADC Utilization:
avg: AVG((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
min: MIN((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
@@ -67,6 +76,14 @@ Addition:
min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
unit: pct
- CPC SYNC FIFO Full Rate:
avg: |
AVG((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
min: |
MIN((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
max: |
MAX((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
unit: pct
- Panel Config:
id: 600
title: Workgroup Manager (SPI)
@@ -165,16 +182,36 @@ Addition:
id: 1202
title: LDS Statistics
metrics:
- LDS ATOMIC:
avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom))
min: MIN((SQ_INSTS_LDS_ATOMIC / $denom))
max: MAX((SQ_INSTS_LDS_ATOMIC / $denom))
unit: (instr + $normUnit)
- LDS ATOMIC Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS Data FIFO Full Rate:
avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom))
min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom))
max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS LOAD:
avg: AVG((SQ_INSTS_LDS_LOAD / $denom))
min: MIN((SQ_INSTS_LDS_LOAD / $denom))
max: MAX((SQ_INSTS_LDS_LOAD / $denom))
unit: (instr + $normUnit)
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS STORE:
avg: AVG((SQ_INSTS_LDS_STORE / $denom))
min: MIN((SQ_INSTS_LDS_STORE / $denom))
@@ -185,39 +222,10 @@ Addition:
min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS ATOMIC:
avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom))
min: MIN((SQ_INSTS_LDS_ATOMIC / $denom))
max: MAX((SQ_INSTS_LDS_ATOMIC / $denom))
unit: (instr + $normUnit)
- LDS Data FIFO Full Rate:
avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom))
min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom))
max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- Panel Config:
id: 1500
title: Address Processing Unit and Data Return Path (TA/TD)
metric_tables:
- metric_table:
id: 1504
title: Vector L1 data-return path or Texture Data (TD)
metrics:
- Write Ack Instructions:
avg: AVG((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
min: MIN((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
max: MAX((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1502
title: Instruction counts
@@ -232,6 +240,21 @@ Addition:
min: MIN((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1504
title: Vector L1 data-return path or Texture Data (TD)
metrics:
- Write Ack Instructions:
avg: AVG((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
min: MIN((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
max: MAX((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
unit: (Instructions + $normUnit)
metric_descriptions:
Write Ack Instructions:
plain: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
rst: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
- Panel Config:
id: 1600
title: Vector L1 Data Cache
@@ -240,45 +263,25 @@ Addition:
id: 1602
title: vL1D cache stall metrics
metrics:
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Latency FIFO:
expr: |
(((100 * TCP_LFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Address:
expr: |
(((100 * TCP_TCP_TA_ADDR_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Data:
expr: |
(((100 * TCP_TCP_TA_DATA_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Latency FIFO:
expr: |
(((100 * TCP_LFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- metric_table:
id: 1603
title: vL1D cache access metrics
metrics:
- Tag RAM 2 Req:
avg: AVG((TCP_TAGRAM2_REQ_sum / $denom))
min: MIN((TCP_TAGRAM2_REQ_sum / $denom))
max: MAX((TCP_TAGRAM2_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 0 Req:
avg: AVG((TCP_TAGRAM0_REQ_sum / $denom))
min: MIN((TCP_TAGRAM0_REQ_sum / $denom))
max: MAX((TCP_TAGRAM0_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 3 Req:
avg: AVG((TCP_TAGRAM3_REQ_sum / $denom))
min: MIN((TCP_TAGRAM3_REQ_sum / $denom))
max: MAX((TCP_TAGRAM3_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 1 Req:
avg: AVG((TCP_TAGRAM1_REQ_sum / $denom))
min: MIN((TCP_TAGRAM1_REQ_sum / $denom))
max: MAX((TCP_TAGRAM1_REQ_sum / $denom))
unit: (Req + $normUnit)
- L1 Access Latency:
avg: AVG((TCP_TCP_LATENCY_sum / $denom))
min: MIN((TCP_TCP_LATENCY_sum / $denom))
@@ -294,59 +297,95 @@ Addition:
min: MIN((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 0 Req:
avg: AVG((TCP_TAGRAM0_REQ_sum / $denom))
min: MIN((TCP_TAGRAM0_REQ_sum / $denom))
max: MAX((TCP_TAGRAM0_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 1 Req:
avg: AVG((TCP_TAGRAM1_REQ_sum / $denom))
min: MIN((TCP_TAGRAM1_REQ_sum / $denom))
max: MAX((TCP_TAGRAM1_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 2 Req:
avg: AVG((TCP_TAGRAM2_REQ_sum / $denom))
min: MIN((TCP_TAGRAM2_REQ_sum / $denom))
max: MAX((TCP_TAGRAM2_REQ_sum / $denom))
unit: (Req + $normUnit)
- Tag RAM 3 Req:
avg: AVG((TCP_TAGRAM3_REQ_sum / $denom))
min: MIN((TCP_TAGRAM3_REQ_sum / $denom))
max: MAX((TCP_TAGRAM3_REQ_sum / $denom))
unit: (Req + $normUnit)
- metric_table:
id: 1605
title: L1 Unified Translation Cache (UTCL1)
metrics:
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- Inflight Req:
avg: AVG((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
min: MIN((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
max: MAX((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
units: (Req + $normUnit)
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- metric_table:
id: 1606
title: L1D Addr Translation Stalls
metrics:
- Serialization Stall:
avg: AVG((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
min: MIN((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
max: MAX((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Cache Full Stall:
avg: AVG((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
min: MIN((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
max: MAX((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
units: (Cycles + $normUnit)
- Resident Page Full Stall:
avg: AVG((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
min: MIN((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
max: MAX((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
units: (Cycles + $normUnit)
- UTCL2 Stall:
avg: AVG((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
units: (Cycles + $normUnit)
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
units: (Cycles + $normUnit)
- Thrashing Stall:
avg: AVG((TCP_UTCL1_THRASHING_STALL_sum / $denom))
min: MIN((TCP_UTCL1_THRASHING_STALL_sum / $denom))
max: MAX((TCP_UTCL1_THRASHING_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Cache Miss Stall:
avg: AVG((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
units: (Cycles + $normUnit)
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
units: (Cycles + $normUnit)
- Resident Page Full Stall:
avg: AVG((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
min: MIN((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
max: MAX((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
units: (Cycles + $normUnit)
- Serialization Stall:
avg: AVG((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
min: MIN((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
max: MAX((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Thrashing Stall:
avg: AVG((TCP_UTCL1_THRASHING_STALL_sum / $denom))
min: MIN((TCP_UTCL1_THRASHING_STALL_sum / $denom))
max: MAX((TCP_UTCL1_THRASHING_STALL_sum / $denom))
units: (Cycles + $normUnit)
- UTCL2 Stall:
avg: AVG((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
units: (Cycles + $normUnit)
metric_descriptions:
L1 Access Latency:
plain: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
rst: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
L1-L2 Read Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L1-L2 Write Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 1700
title: L2 Cache
@@ -380,26 +419,26 @@ Addition:
min: MIN(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth:
avg: AVG(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Bypasss Req:
avg: AVG((TCC_BYPASS_REQ_sum / $denom))
min: MIN((TCC_BYPASS_REQ_sum / $denom))
max: MAX((TCC_BYPASS_REQ_sum / $denom))
unit: (Req + $normUnit)
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth:
avg: AVG(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- metric_table:
id: 1704
title: L2 Cache Stalls
@@ -443,16 +482,6 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
type: PCIe Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read - PCIe Stall:
type: PCIe Stall
transaction: Read
@@ -463,16 +492,6 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - HBM Stall:
type: HBM Stall
transaction: Write
@@ -483,65 +502,186 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
type: PCIe Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read (128B):
avg: AVG((TCC_EA0_RDREQ_128B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_128B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_128B_sum / $denom))
unit: (Req + $normUnit)
- Atomic - HBM:
avg: AVG((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read (128B):
avg: AVG((TCC_EA0_RDREQ_128B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_128B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_128B_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth - HBM:
avg: AVG(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
metric_descriptions:
Atomic Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
Atomic Bandwidth - HBM:
plain: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
Atomic Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
Atomic Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
Read - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
Read - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Read - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Read Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
Read Bandwidth - HBM:
plain: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
Read Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
Read Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
Read Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Write - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
Write - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Write - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Write Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
Write Bandwidth - HBM:
plain: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
Write Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
Write Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
Write Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Deletion:
[]
@@ -555,27 +695,27 @@ Modification:
id: 201
title: System Speed-of-Light
metrics:
- MFMA IOPs (Int8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
unit: GFLOP/s
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
- MFMA FLOPs (BF16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
- MFMA FLOPs (F8):
unit: GFLOP/s
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA IOPs (Int8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- Panel Config:
id: 300
title: Memory Chart
@@ -584,11 +724,11 @@ Modification:
id: 301
title: Memory Chart
metrics:
- Wavefronts:
value: ROUND(AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE), 0)
- Workgroups:
value: |
ROUND(AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS), 0)
- Wavefronts:
value: ROUND(AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE), 0)
- Panel Config:
id: 400
title: Roofline
@@ -597,15 +737,15 @@ Modification:
id: 402
title: Roofline Plot Points
metrics:
- AI L2:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum + TCP_TCC_READ_REQ_sum) * 64 ) )
- AI HBM:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCC_BUBBLE_sum * 128) + (TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32) + (TCC_EA0_WRREQ_64B_sum * 64) ) )
- AI L1:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM(TCP_TOTAL_CACHE_ACCESSES_sum * 64) )
- AI L2:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum + TCP_TCC_READ_REQ_sum) * 64 ) )
- Performance (GFLOPs):
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / (SUM(End_Timestamp - Start_Timestamp) / 1e9) ) / 1e9
@@ -617,38 +757,38 @@ Modification:
id: 601
title: Workgroup manager utilizations
metrics:
- Dispatched Wavefronts:
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Dispatched Workgroups:
max: |
MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
avg: |
AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
min: |
MIN(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
- VGPR Writes:
max: |
MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Scheduler-Pipe Utilization:
AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
max: |
MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
avg: |
AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
- SGPR Writes:
max: |
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
min: |
MIN((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Dispatched Wavefronts:
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
max: |
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Scheduler-Pipe Utilization:
min: |
MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
avg: |
AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
- VGPR Writes:
min: |
MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
max: |
MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Panel Config:
id: 700
title: Wavefront
@@ -658,9 +798,9 @@ Modification:
title: Wavefront Launch Stats
metrics:
- Total Wavefronts:
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Panel Config:
id: 1100
title: Compute Units - Compute Pipeline
@@ -669,37 +809,37 @@ Modification:
id: 1101
title: Compute Speed-of-Light
metrics:
- MFMA FLOPs (F8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
- MFMA FLOPs (BF16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA IOPs (INT8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 128) / 1000))
- MFMA FLOPs (F8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA IOPs (INT8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- metric_table:
id: 1103
title: Arithmetic Operations
metrics:
- FLOPs (Total):
max: |
MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
avg: |
AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
min: |
MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
avg: |
AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
max: |
MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
- Panel Config:
id: 1700
title: L2 Cache
@@ -716,31 +856,31 @@ Modification:
title: L2-Fabric interface metrics
metrics:
- Read BW:
max: |
MAX((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
avg: |
AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
min: |
MIN((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
- Remote Read Traffic:
max: |
MAX((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
avg: |
AVG((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
max: |
MAX((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
- Remote Read Traffic:
min: |
MIN((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
avg: |
AVG((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
max: |
MAX((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- HBM Write and Atomic:
max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
- Read (64B):
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_64B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
- Panel Config:
id: 1800
title: L2 Cache (per Channel)
@@ -750,14 +890,14 @@ Modification:
title: L2-Fabric Read Stall (Cycles per normUnit)
metrics:
- ::_1:
ea read stall - pcie: AVG((TO_INT(TCC_EA0_RDREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea read stall - hbm: AVG((TO_INT(TCC_EA0_RDREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
ea read stall - if: AVG((TO_INT(TCC_EA0_RDREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea read stall - pcie: AVG((TO_INT(TCC_EA0_RDREQ_IO_CREDIT_STALL[::_1]) / $denom))
- metric_table:
id: 1810
title: L2-Fabric Write and Atomic Stall (Cycles per normUnit)
metrics:
- ::_1:
ea write stall - pcie: AVG((TO_INT(TCC_EA0_WRREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea write stall - if: AVG((TO_INT(TCC_EA0_WRREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea write stall - hbm: AVG((TO_INT(TCC_EA0_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
ea write stall - pcie: AVG((TO_INT(TCC_EA0_WRREQ_IO_CREDIT_STALL[::_1]) / $denom))
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0200_system_speed_of_light.yaml
+12 -3
View File
@@ -70,7 +70,7 @@ Panel Config:
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp -
Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -226,6 +226,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -267,8 +272,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -353,3 +358,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/0300_memory_chart.yaml
+3 -3
View File
@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -159,8 +159,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx942/config_delta/gfx950_diff.yaml
+391 -251
View File
@@ -22,12 +22,23 @@ Addition:
id: 301
title: Memory Chart
metrics:
- L2 Wr Lat:
value: |
ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else None)), 0)
- L2 Rd Lat:
value: |
ROUND(AVG(((TCP_TCC_READ_REQ_LATENCY_sum / (TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum)) if ((TCP_TCC_READ_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum) != 0) else None)), 0)
- L2 Wr Lat:
value: |
ROUND(AVG(((TCP_TCC_WRITE_REQ_LATENCY_sum / (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum)) if ((TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum) != 0) else None)), 0)
metric_descriptions:
L2 Rd Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L2 Wr Lat:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 400
title: Roofline
@@ -41,6 +52,12 @@ Addition:
AVG((((SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512)) / ((End_Timestamp - Start_Timestamp) / 1e9)) / 1e9)
unit: GFLOP/s
peak: $MFMA_FLOPs_F6F4_empirical_peak
metric_descriptions:
MFMA FLOPs (F6F4):
plain: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
rst: |
The total number of 4-bit and 6-bit floating point MFMA operations executed per second. Note: this does not include any floating point operations from VALU instructions. The peak empirically measured F6F4 MFMA operations achievable on the specific accelerator is displayed alongside for comparison. It is supported on AMD Instinct MI350 series (gfx950) and later only.
- Panel Config:
id: 500
title: Command Processor (CPC/CPF)
@@ -49,16 +66,16 @@ Addition:
id: 502
title: Command processor packet processor (CPC)
metrics:
- CPC CANE Stall Rate:
avg: AVG((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
unit: pct
- CPC ADC Utilization:
avg: AVG((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
min: MIN((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
max: MAX((100 * CPC_TG_SEND) / CPC_GD_BUSY if (CPC_GD_BUSY != 0) else None)
unit: pct
- CPC CANE Stall Rate:
avg: AVG((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
min: MIN((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
max: MAX((100 * CPC_CANE_STALL) / CPC_CANE_BUSY if (CPC_CANE_BUSY != 0) else None)
unit: pct
- CPC SYNC FIFO Full Rate:
avg: |
AVG((100 * CPC_SYNC_FIFO_FULL) / CPC_SYNC_WRREQ_FIFO_BUSY if (CPC_SYNC_WRREQ_FIFO_BUSY != 0) else None)
@@ -75,14 +92,6 @@ Addition:
id: 601
title: Workgroup manager utilizations
metrics:
- Scheduler-Pipe Wave Utilization:
avg: |
AVG(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
unit: Pct
- Schedule-Pipe Wave Occupancy:
avg: |
AVG(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY)
@@ -91,6 +100,14 @@ Addition:
max: |
MAX(SPI_CSQ_P0_OCCUPANCY + SPI_CSQ_P1_OCCUPANCY + SPI_CSQ_P2_OCCUPANCY + SPI_CSQ_P3_OCCUPANCY)
unit: Wave
- Scheduler-Pipe Wave Utilization:
avg: |
AVG(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
min: |
MIN(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CSC_WAVE_CNT_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
unit: Pct
- metric_table:
id: 602
title: Workgroup Manager - Resource Allocation
@@ -165,50 +182,64 @@ Addition:
id: 1202
title: LDS Statistics
metrics:
- LDS STORE Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
- LDS ATOMIC:
avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom))
min: MIN((SQ_INSTS_LDS_ATOMIC / $denom))
max: MAX((SQ_INSTS_LDS_ATOMIC / $denom))
unit: (instr + $normUnit)
- LDS ATOMIC Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS Data FIFO Full Rate:
avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom))
min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom))
max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS LOAD:
avg: AVG((SQ_INSTS_LDS_LOAD / $denom))
min: MIN((SQ_INSTS_LDS_LOAD / $denom))
max: MAX((SQ_INSTS_LDS_LOAD / $denom))
unit: (instr + $normUnit)
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS STORE:
avg: AVG((SQ_INSTS_LDS_STORE / $denom))
min: MIN((SQ_INSTS_LDS_STORE / $denom))
max: MAX((SQ_INSTS_LDS_STORE / $denom))
unit: (instr + $normUnit)
- LDS Data FIFO Full Rate:
avg: AVG((SQ_LDS_DATA_FIFO_FULL / $denom))
min: MIN((SQ_LDS_DATA_FIFO_FULL / $denom))
max: MAX((SQ_LDS_DATA_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS ATOMIC:
avg: AVG((SQ_INSTS_LDS_ATOMIC / $denom))
min: MIN((SQ_INSTS_LDS_ATOMIC / $denom))
max: MAX((SQ_INSTS_LDS_ATOMIC / $denom))
unit: (instr + $normUnit)
- LDS Command FIFO Full Rate:
avg: AVG((SQ_LDS_CMD_FIFO_FULL / $denom))
min: MIN((SQ_LDS_CMD_FIFO_FULL / $denom))
max: MAX((SQ_LDS_CMD_FIFO_FULL / $denom))
unit: (Cycles + $normUnit)
- LDS ATOMIC Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_ATOMIC_BANDWIDTH / (End_Timestamp - Start_Timestamp))
- LDS STORE Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_STORE_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS LOAD Bandwidth:
avg: AVG(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
min: MIN(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
max: MAX(64 * SQ_INSTS_LDS_LOAD_BANDWIDTH / (End_Timestamp - Start_Timestamp))
units: Gbps
- LDS LOAD:
avg: AVG((SQ_INSTS_LDS_LOAD / $denom))
min: MIN((SQ_INSTS_LDS_LOAD / $denom))
max: MAX((SQ_INSTS_LDS_LOAD / $denom))
unit: (instr + $normUnit)
- Panel Config:
id: 1500
title: Address Processing Unit and Data Return Path (TA/TD)
metric_tables:
- metric_table:
id: 1502
title: Instruction counts
metrics:
- Global/Generic Read Instructions for LDS:
avg: AVG((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- Spill/Stack Read Instructions for LDS:
avg: AVG((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1504
title: Vector L1 data-return path or Texture Data (TD)
@@ -218,20 +249,12 @@ Addition:
min: MIN((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
max: MAX((TD_WRITE_ACKT_WAVEFRONT_sum / $denom))
unit: (Instructions + $normUnit)
- metric_table:
id: 1502
title: Instruction counts
metrics:
- Spill/Stack Read Instructions for LDS:
avg: AVG((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_BUFFER_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
- Global/Generic Read Instructions for LDS:
avg: AVG((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
min: MIN((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
max: MAX((TA_FLAT_READ_LDS_WAVEFRONTS_sum / $denom))
unit: (Instructions + $normUnit)
metric_descriptions:
Write Ack Instructions:
plain: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
rst: |
The total number of write acknowledgements submitted by data-return unit to SQ, summed over all compute units on the accelerator, per normalization unit.
- Panel Config:
id: 1600
title: Vector L1 Data Cache
@@ -240,12 +263,6 @@ Addition:
id: 1602
title: vL1D cache stall metrics
metrics:
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Address:
expr: |
(((100 * TCP_TCP_TA_ADDR_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
@@ -255,6 +272,12 @@ Addition:
- Stalled on Latency FIFO:
expr: |
(((100 * TCP_LFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Read Return:
expr: |
(((100 * TCP_TCR_RDRET_STALL_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- Stalled on Request FIFO:
expr: |
(((100 * TCP_RFIFO_STALL_CYCLES_sum) / TCP_GATE_EN1_sum) if (TCP_GATE_EN1_sum != 0) else None)
- metric_table:
id: 1603
title: vL1D cache access metrics
@@ -264,6 +287,16 @@ Addition:
min: MIN((TCP_TCP_LATENCY_sum / $denom))
max: MAX((TCP_TCP_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- L1-L2 Read Latency:
avg: AVG((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- L1-L2 Write Latency:
avg: AVG((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 0 Req:
avg: AVG((TCP_TAGRAM0_REQ_sum / $denom))
min: MIN((TCP_TAGRAM0_REQ_sum / $denom))
@@ -274,21 +307,11 @@ Addition:
min: MIN((TCP_TAGRAM1_REQ_sum / $denom))
max: MAX((TCP_TAGRAM1_REQ_sum / $denom))
unit: (Req + $normUnit)
- L1-L2 Write Latency:
avg: AVG((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_WRITE_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 2 Req:
avg: AVG((TCP_TAGRAM2_REQ_sum / $denom))
min: MIN((TCP_TAGRAM2_REQ_sum / $denom))
max: MAX((TCP_TAGRAM2_REQ_sum / $denom))
unit: (Req + $normUnit)
- L1-L2 Read Latency:
avg: AVG((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
min: MIN((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
max: MAX((TCP_TCC_READ_REQ_LATENCY_sum / $denom))
unit: (Cycles + $normUnit)
- Tag RAM 3 Req:
avg: AVG((TCP_TAGRAM3_REQ_sum / $denom))
min: MIN((TCP_TAGRAM3_REQ_sum / $denom))
@@ -298,34 +321,34 @@ Addition:
id: 1605
title: L1 Unified Translation Cache (UTCL1)
metrics:
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- Inflight Req:
avg: AVG((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
min: MIN((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
max: MAX((TCP_CLIENT_UTCL1_INFLIGHT_sum / $denom))
units: (Req + $normUnit)
- Misses under Translation Miss:
avg: AVG((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
min: MIN((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
max: MAX((TCP_UTCL1_TRANSLATION_MISS_UNDER_MISS_sum / $denom))
units: (Req + $normUnit)
- metric_table:
id: 1606
title: L1D Addr Translation Stalls
metrics:
- Cache Full Stall:
avg: AVG((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
min: MIN((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
max: MAX((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
units: (Cycles + $normUnit)
- Cache Miss Stall:
avg: AVG((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_MULTI_MISS_sum / $denom))
units: (Cycles + $normUnit)
- Thrashing Stall:
avg: AVG((TCP_UTCL1_THRASHING_STALL_sum / $denom))
min: MIN((TCP_UTCL1_THRASHING_STALL_sum / $denom))
max: MAX((TCP_UTCL1_THRASHING_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Cache Full Stall:
avg: AVG((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
min: MIN((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
max: MAX((TCP_UTCL1_STALL_INFLIGHT_MAX_sum / $denom))
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
units: (Cycles + $normUnit)
- Resident Page Full Stall:
avg: AVG((TCP_UTCL1_STALL_LFIFO_NO_RES_sum / $denom))
@@ -337,16 +360,32 @@ Addition:
min: MIN((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
max: MAX((TCP_UTCL1_SERIALIZATION_STALL_sum / $denom))
units: (Cycles + $normUnit)
- Latency FIFO Stall:
avg: AVG((TCP_UTCL1_LFIFO_FULL_sum / $denom))
min: MIN((TCP_UTCL1_LFIFO_FULL_sum / $denom))
max: MAX((TCP_UTCL1_LFIFO_FULL_sum / $denom))
- Thrashing Stall:
avg: AVG((TCP_UTCL1_THRASHING_STALL_sum / $denom))
min: MIN((TCP_UTCL1_THRASHING_STALL_sum / $denom))
max: MAX((TCP_UTCL1_THRASHING_STALL_sum / $denom))
units: (Cycles + $normUnit)
- UTCL2 Stall:
avg: AVG((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
min: MIN((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
max: MAX((TCP_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS_sum / $denom))
units: (Cycles + $normUnit)
metric_descriptions:
L1 Access Latency:
plain: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
rst: |
Calculated as the average number of cycles that a vL1D cache line request spent in the vL1D cache pipeline.
L1-L2 Read Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive read requests from the L2 Cache. This number also includes requests for atomics with return values.
L1-L2 Write Latency:
plain: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
rst: |
Calculated as the average number of cycles that the vL1D cache took to issue and receive acknowledgement of a write request to the L2 Cache. This number also includes requests for atomics without return values.
- Panel Config:
id: 1700
title: L2 Cache
@@ -355,14 +394,6 @@ Addition:
id: 1702
title: L2-Fabric interface metrics
metrics:
- Write Stall:
avg: |
AVG(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read Stall:
avg: |
AVG((((100 * ((TCC_EA0_RDREQ_IO_CREDIT_STALL_sum + TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum) + TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
@@ -371,44 +402,47 @@ Addition:
max: |
MAX((((100 * ((TCC_EA0_RDREQ_IO_CREDIT_STALL_sum + TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum) + TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum)) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write Stall:
avg: |
AVG(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_STALL_sum) / TCC_BUSY_sum) if (TCC_BUSY_sum != 0) else None))
unit: pct
- metric_table:
id: 1703
title: L2 Cache Accesses
metrics:
- Bypasss Req:
avg: AVG((TCC_BYPASS_REQ_sum / $denom))
min: MIN((TCC_BYPASS_REQ_sum / $denom))
max: MAX((TCC_BYPASS_REQ_sum / $denom))
unit: (Req + $normUnit)
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Atomic Bandwidth:
avg: AVG(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_ATOMIC_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Bypasss Req:
avg: AVG((TCC_BYPASS_REQ_sum / $denom))
min: MIN((TCC_BYPASS_REQ_sum / $denom))
max: MAX((TCC_BYPASS_REQ_sum / $denom))
unit: (Req + $normUnit)
- Input Buffer Req:
avg: AVG((TCC_IB_REQ_sum / $denom))
min: MIN((TCC_IB_REQ_sum / $denom))
max: MAX((TCC_IB_REQ_sum / $denom))
unit: (Req + $normUnit)
- Read Bandwidth:
avg: AVG(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_READ_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth:
avg: AVG(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_WRITE_SECTORS_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- metric_table:
id: 1704
title: L2 Cache Stalls
metrics:
- Stalled on Write Data FIFO:
avg: AVG(TCC_SRC_FIFO_FULL_sum / $denom)
min: MIN(TCC_SRC_FIFO_FULL_sum / $denom)
max: MAX(TCC_SRC_FIFO_FULL_sum / $denom)
unit: (Cycles + $normUnit)
- Input Buffer Stalled on L2:
avg: AVG(TCC_IB_STALL_sum / $denom)
min: MIN(TCC_IB_STALL_sum / $denom)
@@ -419,6 +453,11 @@ Addition:
min: MIN(TCC_LATENCY_FIFO_FULL_sum / $denom)
max: MAX(TCC_LATENCY_FIFO_FULL_sum / $denom)
unit: (Cycles + $normUnit)
- Stalled on Write Data FIFO:
avg: AVG(TCC_SRC_FIFO_FULL_sum / $denom)
min: MIN(TCC_SRC_FIFO_FULL_sum / $denom)
max: MAX(TCC_SRC_FIFO_FULL_sum / $denom)
unit: (Cycles + $normUnit)
- metric_table:
id: 1705
title: L2 - Fabric Interface stalls
@@ -433,16 +472,6 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read - PCIe Stall:
type: PCIe Stall
transaction: Read
avg: |
AVG(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Read - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Read
@@ -453,25 +482,15 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_RDREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
- Read - PCIe Stall:
type: PCIe Stall
transaction: Write
transaction: Read
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
AVG(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
MIN(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
MAX(((100 * (TCC_EA0_RDREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - HBM Stall:
type: HBM Stall
@@ -483,60 +502,181 @@ Addition:
max: |
MAX(((100 * (TCC_EA0_WRREQ_DRAM_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - Infinity Fabric Stall:
type: Infinity Fabric™ Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_GMI_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- Write - PCIe Stall:
type: PCIe Stall
transaction: Write
avg: |
AVG(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
min: |
MIN(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
max: |
MAX(((100 * (TCC_EA0_WRREQ_IO_CREDIT_STALL_sum / TCC_BUSY_sum)) if (TCC_BUSY_sum != 0) else None))
unit: pct
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - HBM:
avg: AVG(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic - HBM:
avg: AVG((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_ATOMIC_DRAM_sum / $denom))
unit: (Req + $normUnit)
- Write Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Atomic Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_ATOMIC_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - HBM:
avg: AVG(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Read Bandwidth - PCIe:
avg: AVG(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_RDREQ_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - HBM:
avg: AVG(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_DRAM_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - Infinity Fabric™:
avg: AVG(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_GMI_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
- Write Bandwidth - PCIe:
avg: AVG(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
min: MIN(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
max: MAX(TCC_EA0_WRREQ_WRITE_IO_32B_sum * 32/ (End_Timestamp - Start_Timestamp))
unit: Gbps
metric_descriptions:
Atomic Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for atomic requests, divided by total duration.
Atomic Bandwidth - HBM:
plain: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to HBM traffic, divided by total duration.
Atomic Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to Infinity Fabric traffic, divided by total duration.
Atomic Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 atomic requests due to PCIe traffic, divided by total duration.
Read - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to the accelerator's local HBM as a percent of the total active L2 cycles.
Read - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Read - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on read requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Read Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for read requests, divided by total duration.
Read Bandwidth - HBM:
plain: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to HBM traffic, divided by total duration.
Read Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to Infinity Fabric traffic, divided by total duration.
Read Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 read requests due to PCIe traffic, divided by total duration.
Read Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a read request to any destination (local HBM, remote PCIe\xAE connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Write - HBM Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to accelerator's local HBM as a percent of the total active L2 cycles.
Write - Infinity Fabric Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote Infinity Fabric connected accelerators or CPUs as a percent of the total active L2 cycles.
Write - PCIe Stall:
plain: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
rst: |
The number of cycles the L2-Fabric interface was stalled on write or atomic requests to remote PCIe connected accelerators or CPUs as a percent of the total active L2 cycles.
Write Bandwidth:
plain: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
rst: |
Total number of bytes looked up in the L2 cache for write requests, divided by total duration.
Write Bandwidth - HBM:
plain: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to HBM traffic, divided by total duration.
Write Bandwidth - Infinity Fabric™:
plain: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to Infinity Fabric traffic, divided by total duration.
Write Bandwidth - PCIe:
plain: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
rst: |
Total number of bytes due to L2 write requests due to PCIe traffic, divided by total duration.
Write Stall:
plain: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
rst: |
The ratio of the total number of cycles the L2-Fabric interface was stalled on a write or atomic request to any destination (local HBM, remote accelerator or CPU, PCIe connected accelerator or CPU, or remote Infinity Fabric connected accelerator or CPU) over the total active L2 cycles.
Deletion:
[]
@@ -550,14 +690,14 @@ Modification:
id: 201
title: System Speed-of-Light
metrics:
- MFMA IOPs (Int8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (BF16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
@@ -566,10 +706,10 @@ Modification:
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA IOPs (Int8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- Panel Config:
id: 300
title: Memory Chart
@@ -578,11 +718,11 @@ Modification:
id: 301
title: Memory Chart
metrics:
- Wavefronts:
value: ROUND(AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE), 0)
- Workgroups:
value: |
ROUND(AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS), 0)
- Wavefronts:
value: ROUND(AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE), 0)
- Panel Config:
id: 400
title: Roofline
@@ -591,12 +731,12 @@ Modification:
id: 402
title: Roofline Plot Points
metrics:
- AI L1:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM(TCP_TOTAL_CACHE_ACCESSES_sum * 64) )
- AI HBM:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCC_BUBBLE_sum * 128) + (TCC_EA0_RDREQ_32B_sum * 32) + ((TCC_EA0_RDREQ_sum - TCC_BUBBLE_sum - TCC_EA0_RDREQ_32B_sum) * 64) + ((TCC_EA0_WRREQ_sum - TCC_EA0_WRREQ_64B_sum) * 32) + (TCC_EA0_WRREQ_64B_sum * 64) ) )
- AI L1:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM(TCP_TOTAL_CACHE_ACCESSES_sum * 64) )
- AI L2:
value: |
( SUM( ($wave_size * ( (SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16 + (2 * SQ_INSTS_VALU_FMA_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32 + (2 * SQ_INSTS_VALU_FMA_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64 + (2 * SQ_INSTS_VALU_FMA_F64) + SQ_INSTS_VALU_TRANS_F64) )) + (SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F32 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F64 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) + (SQ_INSTS_VALU_MFMA_MOPS_F6F4 * 512) ) / SUM( (TCP_TCC_WRITE_REQ_sum + TCP_TCC_ATOMIC_WITH_RET_REQ_sum + TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum + TCP_TCC_READ_REQ_sum) * 64 ) )
@@ -612,37 +752,37 @@ Modification:
title: Workgroup manager utilizations
metrics:
- Dispatched Wavefronts:
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Dispatched Workgroups:
avg: |
AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
max: |
MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
min: |
MIN(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
- SGPR Writes:
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
max: |
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
MAX(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
avg: |
AVG(SPI_CS0_NUM_THREADGROUPS + SPI_CS1_NUM_THREADGROUPS + SPI_CS2_NUM_THREADGROUPS + SPI_CS3_NUM_THREADGROUPS)
- SGPR Writes:
min: |
MIN((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Scheduler-Pipe Utilization:
avg: |
AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
max: |
MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
MAX((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((1 * SPI_SWC_CSC_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Scheduler-Pipe Utilization:
min: |
MIN(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
- VGPR Writes:
avg: |
AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
max: |
MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
MAX(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
avg: |
AVG(100 * (SPI_CS0_BUSY + SPI_CS1_BUSY + SPI_CS2_BUSY + SPI_CS3_BUSY) / ($GRBM_GUI_ACTIVE_PER_XCD * $pipes_per_gpu * $se_per_gpu))
- VGPR Writes:
min: |
MIN((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
max: |
MAX((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
avg: |
AVG((((SPI_VWC0_VDATA_VALID_WR + SPI_VWC1_VDATA_VALID_WR) / (SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)) if ((SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE) != 0) else None))
- Panel Config:
id: 700
title: Wavefront
@@ -652,9 +792,9 @@ Modification:
title: Wavefront Launch Stats
metrics:
- Total Wavefronts:
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
min: MIN(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
max: MAX(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
avg: AVG(SPI_CS0_WAVE + SPI_CS1_WAVE + SPI_CS2_WAVE + SPI_CS3_WAVE)
- Panel Config:
id: 1100
title: Compute Units - Compute Pipeline
@@ -667,10 +807,10 @@ Modification:
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_BF16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA IOPs (INT8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
- MFMA FLOPs (F64):
peak: ((($max_sclk * $cu_per_gpu) * 128) / 1000)
pop: |
@@ -679,21 +819,21 @@ Modification:
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- MFMA FLOPs (F16):
peak: ((($max_sclk * $cu_per_gpu) * 4096) / 1000)
- MFMA IOPs (INT8):
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: |
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_F16 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 4096) / 1000))
((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp - Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
- metric_table:
id: 1103
title: Arithmetic Operations
metrics:
- FLOPs (Total):
avg: |
AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
max: |
MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
min: |
MIN((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
max: |
MAX((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
avg: |
AVG((((((((64 * (((SQ_INSTS_VALU_ADD_F16 + SQ_INSTS_VALU_MUL_F16) + SQ_INSTS_VALU_TRANS_F16) + (SQ_INSTS_VALU_FMA_F16 * 2))) + ((512 * SQ_INSTS_VALU_MFMA_MOPS_F8) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F16) + (512 * SQ_INSTS_VALU_MFMA_MOPS_BF16))) + (64 * (((SQ_INSTS_VALU_ADD_F32 + SQ_INSTS_VALU_MUL_F32) + SQ_INSTS_VALU_TRANS_F32) + (SQ_INSTS_VALU_FMA_F32 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F32)) + (64 * (((SQ_INSTS_VALU_ADD_F64 + SQ_INSTS_VALU_MUL_F64) + SQ_INSTS_VALU_TRANS_F64) + (SQ_INSTS_VALU_FMA_F64 * 2)))) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F64) + (512 * SQ_INSTS_VALU_MFMA_MOPS_F6F4)) / $denom))
- Panel Config:
id: 1700
title: L2 Cache
@@ -709,36 +849,36 @@ Modification:
id: 1702
title: L2-Fabric interface metrics
metrics:
- Remote Read Traffic:
avg: |
AVG((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
max: |
MAX((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
min: |
MIN((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
- Read BW:
avg: |
AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
max: |
MAX((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
min: |
MIN((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
max: |
MAX((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
avg: |
AVG((((TCC_EA0_RDREQ_32B_sum * 32) + (TCC_EA0_RDREQ_64B_sum * 64) + (TCC_EA0_RDREQ_128B_sum * 128)) / (End_Timestamp - Start_Timestamp)))
- Remote Read Traffic:
min: |
MIN((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
max: |
MAX((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
avg: |
AVG((100 * (MAX((TCC_EA0_RDREQ_sum - TCC_EA0_RDREQ_DRAM_sum), 0) / TCC_EA0_RDREQ_sum) if (TCC_EA0_RDREQ_sum != 0) else None))
- metric_table:
id: 1706
title: L2 - Fabric interface detailed metrics
metrics:
- Read (64B):
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_64B_sum / $denom))
- Read (128B):
avg: AVG((TCC_EA0_RDREQ_128B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_128B_sum / $denom))
min: MIN((TCC_EA0_RDREQ_128B_sum / $denom))
- HBM Write and Atomic:
avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
min: MIN((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
max: MAX((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
avg: AVG((TCC_EA0_WRREQ_WRITE_DRAM_sum / $denom))
- Read (128B):
min: MIN((TCC_EA0_RDREQ_128B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_128B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_128B_sum / $denom))
- Read (64B):
min: MIN((TCC_EA0_RDREQ_64B_sum / $denom))
max: MAX((TCC_EA0_RDREQ_64B_sum / $denom))
avg: AVG((TCC_EA0_RDREQ_64B_sum / $denom))
- Panel Config:
id: 1800
title: L2 Cache (per Channel)
@@ -748,14 +888,14 @@ Modification:
title: L2-Fabric Read Stall (Cycles per normUnit)
metrics:
- ::_1:
ea read stall - pcie: AVG((TO_INT(TCC_EA0_RDREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea read stall - if: AVG((TO_INT(TCC_EA0_RDREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea read stall - hbm: AVG((TO_INT(TCC_EA0_RDREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
ea read stall - if: AVG((TO_INT(TCC_EA0_RDREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea read stall - pcie: AVG((TO_INT(TCC_EA0_RDREQ_IO_CREDIT_STALL[::_1]) / $denom))
- metric_table:
id: 1810
title: L2-Fabric Write and Atomic Stall (Cycles per normUnit)
metrics:
- ::_1:
ea write stall - hbm: AVG((TO_INT(TCC_EA0_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
ea write stall - if: AVG((TO_INT(TCC_EA0_WRREQ_GMI_CREDIT_STALL[::_1]) / $denom))
ea write stall - pcie: AVG((TO_INT(TCC_EA0_WRREQ_IO_CREDIT_STALL[::_1]) / $denom))
ea write stall - hbm: AVG((TO_INT(TCC_EA0_WRREQ_DRAM_CREDIT_STALL[::_1]) / $denom))
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0200_system_speed_of_light.yaml
+12 -3
View File
@@ -76,7 +76,7 @@ Panel Config:
peak: ((($max_sclk * $cu_per_gpu) * 8192) / 1000)
pop: ((100 * AVG(((SQ_INSTS_VALU_MFMA_MOPS_I8 * 512) / (End_Timestamp -
Start_Timestamp)))) / ((($max_sclk * $cu_per_gpu) * 8192) / 1000))
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
unit: CUs
peak: $cu_per_gpu
@@ -232,6 +232,11 @@ Panel Config:
peak: None
pop: None
coll_level: SQ_IFETCH_LEVEL
CU Utilization:
value: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
unit: Pct
peak: 100
pop: AVG(100 * SQ_BUSY_CU_CYCLES / ($GRBM_GUI_ACTIVE_PER_XCD * $cu_per_gpu))
metrics_description:
VALU FLOPs: >-
The total floating-point operations executed per second on the VALU.
@@ -273,8 +278,8 @@ Panel Config:
Note: this does not include any 8-bit integer operations from VALU instructions.
This is also presented as a percent of the peak theoretical INT8 MFMA operations
achievable on the specific accelerator.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
SALU Utilization: Indicates what percent of the kernel's duration the SALU was
busy executing instructions. Computed as the ratio of the total number of cycles
spent by the scheduler issuing SALU or SMEM instructions over the total CU cycles.
@@ -359,3 +364,7 @@ Panel Config:
of all L1I requests.
L1I Fetch Latency: The average number of cycles spent to fetch instructions to
a CU.
CU Utilization: The percent of total SIMD cycles in the kernel
where any SIMD on a CU was actively doing any work, summed
over all CUs. Low values (less than 100%) indicate that the accelerator was
not fully saturated by the kernel, or a potential load-imbalance issue.
projects/rocprofiler-compute/src/rocprof_compute_soc/analysis_configs/gfx950/0300_memory_chart.yaml
+3 -3
View File
@@ -33,7 +33,7 @@ Panel Config:
value: ROUND(AVG((SQ_INSTS_GDS / $denom)), 0)
BR:
value: ROUND(AVG((SQ_INSTS_BRANCH / $denom)), 0)
Active CUs:
Active CUs (deprecated):
value: $numActiveCUs
Num CUs:
value: $cu_per_gpu
@@ -169,8 +169,8 @@ Panel Config:
GWS: Total number of GDS (global data sync) instructions issued per normalization
unit.
BR: Total number of BRANCH instructions issued per normalization unit.
Active CUs: Total number of active compute units (CUs) on the accelerator during
the kernel execution.
Active CUs (deprecated): Total number of active compute units (CUs) on the accelerator during
the kernel execution. (Deprecated - See CU Utilization instead)
Num CUs: Total number of compute units (CUs) on the accelerator.
VGPR: >-
The number of architected vector general-purpose registers allocated
projects/rocprofiler-compute/tools/config_management/.config_hashes.json
+18 -18
View File
@@ -1,12 +1,12 @@
{
"archs": {
"gfx908": {
"delta_hash": "a2d9bef7e5d8b056605f9b1fa6569678",
"delta_hash": "ea37a8ffe846ecab3bd5833be174b1d1",
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "c4878ac57b7b7b4b5711672cb2f6dffc",
"0300_memory_chart.yaml": "221c6d2bb50a4f4177585b9988f88c7b",
"0200_system_speed_of_light.yaml": "9ddb50865f89c836306ac651605f702c",
"0300_memory_chart.yaml": "51bf953860670ffb6de4b598228fb101",
"0400_roofline.yaml": "bad8d851694ff9a140e29a148a35fa50",
"0500_command_processor_cpc_cpf.yaml": "d8f424ec3fcfa4b2fcee2ad5e6456531",
"0600_workgroup_manager_spi.yaml": "8b6a89de516bed5821a9849627ad634a",
@@ -24,12 +24,12 @@
}
},
"gfx90a": {
"delta_hash": "55e28dda19e9ae640ba436be1a42fe97",
"delta_hash": "0c232e10c260a381e44b5c074463387b",
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "dc6a6e1a8513e2d32aecc055a958c639",
"0300_memory_chart.yaml": "a61f219fe063c4c4b0b9cbaf96389a8b",
"0200_system_speed_of_light.yaml": "11ff9f634400a71b95a7a23b6e426077",
"0300_memory_chart.yaml": "d4eca43aa3bc8f07a3c2d9fbbc87839f",
"0400_roofline.yaml": "da1d514ed19ca2466c167e983bdb4f13",
"0500_command_processor_cpc_cpf.yaml": "d8f424ec3fcfa4b2fcee2ad5e6456531",
"0600_workgroup_manager_spi.yaml": "8b6a89de516bed5821a9849627ad634a",
@@ -47,12 +47,12 @@
}
},
"gfx940": {
"delta_hash": "531bb865bffcb2fc5658c2e613b341d2",
"delta_hash": "d7d4c9ae9917d68def0e868e925477a6",
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "8b413c47f06f2e94b3faa723daac8edd",
"0300_memory_chart.yaml": "3d6c88ab2704dc4bd72a63e99fd68cf7",
"0200_system_speed_of_light.yaml": "d5df0a2b701972fa08ba0a44e72aa752",
"0300_memory_chart.yaml": "40dc04c73c3cec3d0a93e26d2db8c6f3",
"0400_roofline.yaml": "d4650e008f2e3a7d28871e8518153575",
"0500_command_processor_cpc_cpf.yaml": "d8f424ec3fcfa4b2fcee2ad5e6456531",
"0600_workgroup_manager_spi.yaml": "8b6a89de516bed5821a9849627ad634a",
@@ -70,12 +70,12 @@
}
},
"gfx941": {
"delta_hash": "9b30264f36ff99f54941346a18af016a",
"delta_hash": "723ad8f0a57153314eac933ddb184ee3",
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "0ddeaefd245291c7f88674431efd74f6",
"0300_memory_chart.yaml": "3d6c88ab2704dc4bd72a63e99fd68cf7",
"0200_system_speed_of_light.yaml": "0ccc1a63ebe11079832741c6d86ec3aa",
"0300_memory_chart.yaml": "40dc04c73c3cec3d0a93e26d2db8c6f3",
"0400_roofline.yaml": "c066a19bc0e00e692c34998e44c62387",
"0500_command_processor_cpc_cpf.yaml": "d8f424ec3fcfa4b2fcee2ad5e6456531",
"0600_workgroup_manager_spi.yaml": "8b6a89de516bed5821a9849627ad634a",
@@ -93,12 +93,12 @@
}
},
"gfx942": {
"delta_hash": "66cf66455fafa2b6b5936d31fecf3e85",
"delta_hash": "69acdfb29af82ce78f1b7051d57ae5b1",
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "8b413c47f06f2e94b3faa723daac8edd",
"0300_memory_chart.yaml": "3d6c88ab2704dc4bd72a63e99fd68cf7",
"0200_system_speed_of_light.yaml": "d5df0a2b701972fa08ba0a44e72aa752",
"0300_memory_chart.yaml": "40dc04c73c3cec3d0a93e26d2db8c6f3",
"0400_roofline.yaml": "318c3e774d41a639628a7f72c2462375",
"0500_command_processor_cpc_cpf.yaml": "d8f424ec3fcfa4b2fcee2ad5e6456531",
"0600_workgroup_manager_spi.yaml": "8b6a89de516bed5821a9849627ad634a",
@@ -120,8 +120,8 @@
"files": {
"0000_top_stats.yaml": "2819d96f5b1c3704f2ac50868a246a7f",
"0100_system_info.yaml": "cefae2b10db8cf4b0d3a971cff5e82c8",
"0200_system_speed_of_light.yaml": "a5ee49ce96bfab87128c856c827db870",
"0300_memory_chart.yaml": "e2401641a8f280fda308f87e5ad243df",
"0200_system_speed_of_light.yaml": "bf2ca00d4b255dbbe191a7641b81dc4c",
"0300_memory_chart.yaml": "2c82fa6f81a0dda679706d36b99e7913",
"0400_roofline.yaml": "2bd3b630b72d6d165c0d30cf481136a9",
"0500_command_processor_cpc_cpf.yaml": "3f7dab1663ad7a6fae3801aec2b1e8d0",
"0600_workgroup_manager_spi.yaml": "e6546a92d283fed5a5dc6df203efb670",
@@ -139,4 +139,4 @@
}
}
}
}
}