From fe9b01e9165e05075d86c0cf7836e414d80d403e Mon Sep 17 00:00:00 2001 From: Mike Li Date: Tue, 8 Jun 2021 11:48:11 -0400 Subject: [PATCH] Added gfx940 ISA Signed-off-by: Mike Li Change-Id: Icb1830fe186abc69fe7ee709b7f12b882cab9e87 [ROCm/ROCR-Runtime commit: bd98a1e5bf611c1813be7799954387fcab0b318d] --- .../rocrtst/suites/test_common/CMakeLists.txt | 2 +- .../runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp | 8 +++++--- .../runtime/hsa-runtime/core/runtime/hsa.cpp | 4 ++++ .../runtime/hsa-runtime/core/runtime/isa.cpp | 9 +++++++++ .../runtime/hsa-runtime/image/blit_kernel.cpp | 3 +++ .../runtime/hsa-runtime/image/blit_src/CMakeLists.txt | 2 +- .../rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h | 2 +- .../runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp | 2 ++ 8 files changed, 26 insertions(+), 6 deletions(-) diff --git a/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt b/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt index 7a01f76b71..51842eeecd 100755 --- a/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt +++ b/projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt @@ -82,7 +82,7 @@ if ( PROC_RESULT EQUAL "0" AND NOT EVAL_RESULT STREQUAL "" ) endif() set (CPACK_RPM_PACKAGE_REQUIRES "rocm-core") -set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") +set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") # # Currently support for Windows platform is not present diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp index 6d8efe0618..6664d60ce9 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp @@ -314,7 +314,8 @@ void GpuAgent::AssembleShader(const char* func_name, AssembleTarget assemble_tar asic_shader = &compiled_shader_it->second.compute_8; break; case 9: - if((isa_->GetMinorVersion() == 0) && (isa_->GetStepping() == 10)) + if(((isa_->GetMinorVersion() == 0) && (isa_->GetStepping() == 10)) || + ((isa_->GetMinorVersion() == 4) && (isa_->GetStepping() == 0))) asic_shader = &compiled_shader_it->second.compute_90a; else asic_shader = &compiled_shader_it->second.compute_9; @@ -368,8 +369,9 @@ void GpuAgent::AssembleShader(const char* func_name, AssembleTarget assemble_tar AMD_HSA_BITS_SET(header->compute_pgm_rsrc2, AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X, 1); - if ((isa_->GetMajorVersion() == 9) && (isa_->GetMinorVersion() == 0) && - (isa_->GetStepping() == 10)) { + if ((isa_->GetMajorVersion() == 9) && + (((isa_->GetMinorVersion() == 0) && (isa_->GetStepping() == 10)) || + ((isa_->GetMinorVersion() == 4) && (isa_->GetStepping() == 0)))) { // Program COMPUTE_PGM_RSRC3.ACCUM_OFFSET for 0 ACC VGPRs on gfx90a. // FIXME: Assemble code objects from source at build time int gran_accvgprs = ((gran_vgprs + 1) * 8) / 4 - 1; diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp index bcc1414573..d8604f710b 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp @@ -1906,6 +1906,10 @@ static std::string ConvertOldTargetNameToNew( NewName = "amdgcn-amd-amdhsa--gfx90c"; xnack_supported = true; } + else if (OldName == "AMD:AMDGPU:9:4:0") { + NewName = "amdgcn-amd-amdhsa--gfx940"; + xnack_supported = true; + } else { // Code object v2 only supports asics up to gfx906 plus gfx90c. Do NOT add // handling of new asics into this if-else-if* block. diff --git a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp index 7d3cf906e0..0a2fa5742a 100755 --- a/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp @@ -297,6 +297,15 @@ constexpr size_t hsa_name_size = 63; ISAREG_ENTRY_GEN("gfx90c", 9, 0, 12, unsupported, any, 64) ISAREG_ENTRY_GEN("gfx90c:xnack-", 9, 0, 12, unsupported, disabled, 64) ISAREG_ENTRY_GEN("gfx90c:xnack+", 9, 0, 12, unsupported, enabled, 64) + ISAREG_ENTRY_GEN("gfx940", 9, 4, 0, any, any, 64) + ISAREG_ENTRY_GEN("gfx940:xnack-", 9, 4, 0, any, disabled, 64) + ISAREG_ENTRY_GEN("gfx940:xnack+", 9, 4, 0, any, enabled, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc-", 9, 4, 0, disabled, any, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc+", 9, 4, 0, enabled, any, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc-:xnack-", 9, 4, 0, disabled, disabled, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc-:xnack+", 9, 4, 0, disabled, enabled, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc+:xnack-", 9, 4, 0, enabled, disabled, 64) + ISAREG_ENTRY_GEN("gfx940:sramecc+:xnack+", 9, 4, 0, enabled, enabled, 64) ISAREG_ENTRY_GEN("gfx1010", 10, 1, 0, unsupported, any, 32) ISAREG_ENTRY_GEN("gfx1010:xnack-", 10, 1, 0, unsupported, disabled, 32) ISAREG_ENTRY_GEN("gfx1010:xnack+", 10, 1, 0, unsupported, enabled, 32) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp index 3eea38d6e3..6b4bd53e64 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp @@ -85,6 +85,7 @@ extern uint8_t ocl_blit_object_gfx908[]; extern uint8_t ocl_blit_object_gfx909[]; extern uint8_t ocl_blit_object_gfx90a[]; extern uint8_t ocl_blit_object_gfx90c[]; +extern uint8_t ocl_blit_object_gfx940[]; extern uint8_t ocl_blit_object_gfx1010[]; extern uint8_t ocl_blit_object_gfx1011[]; extern uint8_t ocl_blit_object_gfx1012[]; @@ -1007,6 +1008,8 @@ hsa_status_t BlitKernel::GetPatchedBlitObject(const char* agent_name, *blit_code_object = ocl_blit_object_gfx90a; } else if (sname == "gfx90c") { *blit_code_object = ocl_blit_object_gfx90c; + } else if (sname == "gfx940") { + *blit_code_object = ocl_blit_object_gfx940; } else if (sname == "gfx1010") { *blit_code_object = ocl_blit_object_gfx1010; } else if (sname == "gfx1011") { diff --git a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt index 21f998bf72..d8d39605d5 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt +++ b/projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt @@ -47,7 +47,7 @@ find_package(Clang REQUIRED HINTS ${CMAKE_PREFIX_PATH}/llvm PATHS /opt/rocm/llvm # Determine the target devices if not specified if (NOT DEFINED TARGET_DEVICES) - set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") + set(TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx940;gfx1010;gfx1011;gfx1012;gfx1013;gfx1030;gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036;gfx1100;gfx1101;gfx1102;gfx1103") endif() set( TARGET_DEVICES ${TARGET_DEVICES} CACHE STRING "Build targets" FORCE ) diff --git a/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h b/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h index b2de2a20a3..283d48d754 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h +++ b/projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h @@ -119,7 +119,7 @@ enum : unsigned { EF_AMDGPU_MACH_AMDGCN_GFX1035 = 0x03d, EF_AMDGPU_MACH_AMDGCN_GFX1034 = 0x03e, EF_AMDGPU_MACH_AMDGCN_GFX90A = 0x03f, - EF_AMDGPU_MACH_AMDGCN_RESERVED_0X40 = 0x040, + EF_AMDGPU_MACH_AMDGCN_GFX940 = 0x040, EF_AMDGPU_MACH_AMDGCN_GFX1100 = 0x041, EF_AMDGPU_MACH_AMDGCN_GFX1013 = 0x042, EF_AMDGPU_MACH_AMDGCN_GFX1103 = 0x044, diff --git a/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp b/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp index 64eac2e65c..48169e33a5 100644 --- a/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp +++ b/projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp @@ -643,6 +643,8 @@ namespace code { mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX906; else if (old_name == "AMD:AMDGPU:9:0:12") mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C; + else if (old_name == "AMD:AMDGPU:9:4:0") + mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX940; else if (old_name == "AMD:AMDGPU:11:0:0") mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100; else if (old_name == "AMD:AMDGPU:11:0:1")