P4 to Git Change 1275749 by wchau@wchau_WIN_OCL_HSA on 2016/06/02 13:38:16
SWDEV-89502 - [OCL] Support AMD DVR Core functionalities. Add OCL support for DOPP for desktop and present texture (OCL RT changes)
Affected files ...
... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_gl.cpp#50 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/amdocl/cl_svm.cpp#17 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/khronos/headers/opencl1.2/CL/cl_ext.h#11 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/khronos/headers/opencl2.0/CL/cl_ext.h#25 edit
... //depot/stg/opencl/drivers/opencl/api/opencl/khronos/headers/opencl2.1/CL/cl_ext.h#4 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.cpp#316 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpukernel.hpp#124 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#403 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDeviceGL.cpp#26 edit
... //depot/stg/opencl/drivers/opencl/runtime/platform/kernel.hpp#16 edit
[ROCm/clr commit: 7acdb2390f]
This commit is contained in:
@@ -472,7 +472,7 @@ VirtualGPU::create(bool profiling, uint rtCUs, uint deviceQueueSize,
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}
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//!@todo This is not a generic solution and
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// may have issues with > 8 queues
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idx = index() % (dev().engines().numComputeRings() +
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idx = index() % (dev().engines().numComputeRings() +
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dev().engines().numComputeRingsRT());
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}
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// hwRing_ should be set 0 if forced to have single scratch buffer
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@@ -1839,11 +1839,23 @@ VirtualGPU::submitKernelInternalHSA(
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pKernelInfo = &kernelInfo;
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}
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// Set up the dispatch information
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KernelDispatchInfo dispatchInfo;
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dispatchInfo.aqlPacket = aqlPkt;
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dispatchInfo.mems = vmMems();
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dispatchInfo.numMems = cal_.memCount_;
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dispatchInfo.scratch = scratch;
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dispatchInfo.scratchOffset = scratchOffset;
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dispatchInfo.cpuAqlCode = hsaKernel.cpuAqlCode();
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dispatchInfo.hsaQueueVA = hsaQueueMem_->vmAddress();
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dispatchInfo.kernelInfo = pKernelInfo;
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dispatchInfo.wavesPerSH = hsaKernel.getWavesPerSH(this);
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dispatchInfo.lastDoppSubmission = kernel.parameters().getExecNewVcop();
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GpuEvent gpuEvent;
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// Run AQL dispatch in HW
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eventBegin(MainEngine);
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cs()->AqlDispatch(aqlPkt, vmMems(), cal_.memCount_, scratch, scratchOffset,
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hsaKernel.cpuAqlCode(), hsaQueueMem_->vmAddress(), pKernelInfo, hsaKernel.getWavesPerSH(this));
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cs()->AqlDispatch(&dispatchInfo);
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eventEnd(MainEngine, gpuEvent);
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if (dbgManager && (NULL != dbgManager->postDispatchCallBackFunc())) {
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@@ -2143,7 +2155,7 @@ VirtualGPU::submitKernelInternal(
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}
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// Execute the kernel
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if (gpuKernel.run(*this, &gpuEvent, lastRun)) {
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if (gpuKernel.run(*this, &gpuEvent, lastRun, kernel.parameters().getExecNewVcop())) {
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//! @todo A flush is necessary to make sure
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// that 2 consecutive runs won't access to the same
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// private/local memory. CAL has to generate cache flush
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