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Author SHA1 Message Date
Gerardo Hernandez d96c631de0 SWDEV-496392 - Remove references to ASIC Polaris22 in pal::Settings and pal::Device (it is being retired) 
Change-Id: I6318abf3e46ed250d087a3d2266d2ae3d4c8c000


[ROCm/clr commit: 03e4057fce]
 2024-12-10 06:01:32 -05:00
Gerardo Hernandez 03e4057fce SWDEV-496392 - Remove references to ASIC Polaris22 in pal::Settings and pal::Device (it is being retired) 
Change-Id: I6318abf3e46ed250d087a3d2266d2ae3d4c8c000
 2024-12-10 06:01:32 -05:00
Jatin Chaudhary d9482cf69c SWDEV-486137 - Add tests for *hadd* 
Change-Id: I60839bce25ac57947bda1eab9c49941c53ace7cd


[ROCm/hip-tests commit: 7bb49582db]
 2024-12-10 04:32:45 -05:00
Jatin Chaudhary 7bb49582db SWDEV-486137 - Add tests for *hadd* 
Change-Id: I60839bce25ac57947bda1eab9c49941c53ace7cd
 2024-12-10 04:32:45 -05:00
Branislav Brzak be67fb0fdf SWDEV-441986 - Create tests for divergent execution of warp_sync builtins 
Change-Id: If9ce0bdb0974732b692c779c7cae5527cec2fc83


[ROCm/hip-tests commit: 3a20cff19b]
 2024-12-10 04:15:11 -05:00
Branislav Brzak 3a20cff19b SWDEV-441986 - Create tests for divergent execution of warp_sync builtins 
Change-Id: If9ce0bdb0974732b692c779c7cae5527cec2fc83
 2024-12-10 04:15:11 -05:00
Marko Arandjelovic 625c30fdf7 SWDEV-477070 - Add unit test for hipTexRefGetArray 
Change-Id: Ifa4c62d926dd15ce8379b9899ca81d3a39595c8e


[ROCm/hip-tests commit: 533db3b042]
 2024-12-10 04:00:33 -05:00
Marko Arandjelovic 533db3b042 SWDEV-477070 - Add unit test for hipTexRefGetArray 
Change-Id: Ifa4c62d926dd15ce8379b9899ca81d3a39595c8e
 2024-12-10 04:00:33 -05:00
Bhardwaj, Gopesh 681740b52b gobhardw/docs logging (#10) 
* reducing docs logging

* Addressing review comments

* exclude dirs

* maximize NUM_PROC_THREADS

* parallel build

[ROCm/rocprofiler-sdk commit: 3ee06ed747]
 2024-12-10 14:15:59 +05:30
Bhardwaj, Gopesh 3ee06ed747 gobhardw/docs logging (#10) 
* reducing docs logging

* Addressing review comments

* exclude dirs

* maximize NUM_PROC_THREADS

* parallel build
 2024-12-10 14:15:59 +05:30
Aryan Salmanpour 67ab645a6d Enable the CMake ROCDECODE_ROCPROFILER_REGISTER option by default (#469) 
[ROCm/rocdecode commit: c02fbcf658]
 2024-12-09 18:24:30 -05:00
Aryan Salmanpour c02fbcf658 Enable the CMake ROCDECODE_ROCPROFILER_REGISTER option by default (#469) 2024-12-09 18:24:30 -05:00
Jimbo Xie ff5e5c5e98 SWDEV-477219 - hipEventRecordwithFlags hipother 
Change-Id: I17313697f24ab095f134da0873148962114df5fc


[ROCm/hipother commit: 0b82c50300]
 2024-12-09 16:41:55 -05:00
Jimbo Xie 0b82c50300 SWDEV-477219 - hipEventRecordwithFlags hipother 
Change-Id: I17313697f24ab095f134da0873148962114df5fc
 2024-12-09 16:41:55 -05:00
Ranjith Ramakrishnan 87b59eade6 SWDEV-498728 - Add backward compatibility for deprecated package rocm-opencl-icd-loader 
Change-Id: Ic659639e3bb55bd90bd50acf28d8079ff7b084bc


[ROCm/clr commit: 7c9c7a6332]
 2024-12-09 16:27:43 -05:00
Ranjith Ramakrishnan 7c9c7a6332 SWDEV-498728 - Add backward compatibility for deprecated package rocm-opencl-icd-loader 
Change-Id: Ic659639e3bb55bd90bd50acf28d8079ff7b084bc
 2024-12-09 16:27:43 -05:00
David Rosca 41da20ae17 Create surfaces with linear modifier (#88) 
Mesa will be enabling tiling for all VA surfaces by default,
but HIP doesn't support modifiers for dmabuf import.

[ROCm/rocjpeg commit: d9b89264d5]
 2024-12-09 16:27:40 -05:00
David Rosca d9b89264d5 Create surfaces with linear modifier (#88) 
Mesa will be enabling tiling for all VA surfaces by default,
but HIP doesn't support modifiers for dmabuf import.
 2024-12-09 16:27:40 -05:00
Maisam Arif ddcfe28520 [SWDEV-503491] Updated Market Names 
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: Ib56c4c96190e18708ef4d0d6358dd8d5b1ee9e6a
 2024-12-09 15:40:06 -05:00
Maisam Arif 0db64ff2b3 [SWDEV-503491] Updated Market Names 
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: Ib56c4c96190e18708ef4d0d6358dd8d5b1ee9e6a


[ROCm/amdsmi commit: ddcfe28520]
 2024-12-09 15:40:06 -05:00
German Andryeyev 6604accdb3 SWDEV-501757 - Use signals without interrupts 
In active wait mode use signals without interrupts by default and switch
to the interrupts only if a callback is required.

Change-Id: Ibcde8f7d44c70f8fb8fa5e0a7fdd8b08a2982a8e


[ROCm/clr commit: f4b9d3b7bd]
 2024-12-09 15:16:15 -05:00
German Andryeyev f4b9d3b7bd SWDEV-501757 - Use signals without interrupts 
In active wait mode use signals without interrupts by default and switch
to the interrupts only if a callback is required.

Change-Id: Ibcde8f7d44c70f8fb8fa5e0a7fdd8b08a2982a8e
 2024-12-09 15:16:15 -05:00
David Rosca 2a4a772f41 Create surfaces with linear modifier (#465) 
Mesa will be enabling tiling for all VA surfaces by default,
but HIP doesn't support modifiers for dmabuf import.

[ROCm/rocdecode commit: 80e08f47c2]
 2024-12-09 14:46:57 -05:00
David Rosca 80e08f47c2 Create surfaces with linear modifier (#465) 
Mesa will be enabling tiling for all VA surfaces by default,
but HIP doesn't support modifiers for dmabuf import.
 2024-12-09 14:46:57 -05:00
Marko Arandjelovic cee2f8215d SWDEV-477740 - Add unit test for hipTexRefSetArray 
Change-Id: I3bd2f9cd956260110e7e5cd6c982769c5752b7d8


[ROCm/hip-tests commit: b346582bff]
 2024-12-09 13:52:30 -05:00
Marko Arandjelovic b346582bff SWDEV-477740 - Add unit test for hipTexRefSetArray 
Change-Id: I3bd2f9cd956260110e7e5cd6c982769c5752b7d8
 2024-12-09 13:52:30 -05:00
SrinivasaRao 5ba5ca2934 SWDEV-490555-[catch2][dtest] Functional tests for the API hipMemcpyHtoAAsync 
Change-Id: I927e0907e2e2fb8316151da5b3a5ba23835412e8


[ROCm/hip-tests commit: 16c33198ba]
 2024-12-09 13:49:05 -05:00
SrinivasaRao 16c33198ba SWDEV-490555-[catch2][dtest] Functional tests for the API hipMemcpyHtoAAsync 
Change-Id: I927e0907e2e2fb8316151da5b3a5ba23835412e8
 2024-12-09 13:49:05 -05:00
Bindhiya Kanangot Balakrishnan 288b11df37 [SWDEV-496639] Align amd-smi xgmi statistics 
The xgmi read and write values were displayed in KB. The numbers became
unreadable due to misalignment. So, converted read and write values to
readable units using helper function. Updated Changelog.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
Change-Id: I4c90a1de8a58c29cbdf43fe3480a1546f3946673
 2024-12-09 12:57:45 -05:00
Bindhiya Kanangot Balakrishnan efa7286410 [SWDEV-496639] Align amd-smi xgmi statistics 
The xgmi read and write values were displayed in KB. The numbers became
unreadable due to misalignment. So, converted read and write values to
readable units using helper function. Updated Changelog.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
Change-Id: I4c90a1de8a58c29cbdf43fe3480a1546f3946673


[ROCm/amdsmi commit: 288b11df37]
 2024-12-09 12:57:45 -05:00
Rahul Manocha 05e52df05c SWDEV-483107,SWDEV-492076,SWDEV-491371,SWDEV-484940 - hipStreamBeginCaptureToGraph catch exception fix 
1) Catch Section should not be used inside host thread call.

Change-Id: I52c1bb80d6f92034dfbe2484d928e66eacf67d4c


[ROCm/hip-tests commit: decf563391]
 2024-12-09 12:07:26 -05:00
Rahul Manocha decf563391 SWDEV-483107,SWDEV-492076,SWDEV-491371,SWDEV-484940 - hipStreamBeginCaptureToGraph catch exception fix 
1) Catch Section should not be used inside host thread call.

Change-Id: I52c1bb80d6f92034dfbe2484d928e66eacf67d4c
 2024-12-09 12:07:26 -05:00
Ajay 7346f3bd29 SWDEV-498474 - APU: when total allocated is greater than 75% of invisible 
Only when memory type is Local and the invisible memory is +ve
Should also fix SWDEV-490991

Change-Id: I78a4925a234ba90c63909bde5b7dc217568b4de3


[ROCm/clr commit: 7d763fb803]
 2024-12-09 12:06:57 -05:00
Ajay 7d763fb803 SWDEV-498474 - APU: when total allocated is greater than 75% of invisible 
Only when memory type is Local and the invisible memory is +ve
Should also fix SWDEV-490991

Change-Id: I78a4925a234ba90c63909bde5b7dc217568b4de3
 2024-12-09 12:06:57 -05:00
Rahul Manocha 4dcee8e1e9 SWDEV-467733 - Enable SetCacheConfig Negative Param test 
Change-Id: I8be8783dea6728a94580f2489251c7f1d60db7b2


[ROCm/hip-tests commit: 803097426e]
 2024-12-09 11:22:25 -05:00
Rahul Manocha 803097426e SWDEV-467733 - Enable SetCacheConfig Negative Param test 
Change-Id: I8be8783dea6728a94580f2489251c7f1d60db7b2
 2024-12-09 11:22:25 -05:00
Satyanvesh Dittakavi 9cad0a4d59 SWDEV-485372 - Fix texture catch tests to run on appropriate ASICs 
Change-Id: I9ef93e37eb29c3d09c6448fe95dba39fa7060464


[ROCm/hip-tests commit: d5028f0c2a]
 2024-12-09 10:35:43 -05:00
Satyanvesh Dittakavi d5028f0c2a SWDEV-485372 - Fix texture catch tests to run on appropriate ASICs 
Change-Id: I9ef93e37eb29c3d09c6448fe95dba39fa7060464
 2024-12-09 10:35:43 -05:00
Ioannis Assiouras ca754b4a3e SWDEV-475482 - Disable Texture Object Tests for all asics to merge clr change 
Change-Id: I1dea13d938fd1c62a3a2ce8eb97fbff338a9e0bb


[ROCm/hip-tests commit: 8a3c3b65a7]
 2024-12-09 06:59:20 -05:00
Ioannis Assiouras 8a3c3b65a7 SWDEV-475482 - Disable Texture Object Tests for all asics to merge clr change 
Change-Id: I1dea13d938fd1c62a3a2ce8eb97fbff338a9e0bb
 2024-12-09 06:59:20 -05:00
Vladana Stojiljkovic d6b1d6a264 SWDEV-489376 - Fix Unit_hipLaunchHostFunc_Graph memory leaks 
Change-Id: I209f686cb13f05d6b0b790aaa7ab8b93555df3b1


[ROCm/hip-tests commit: bf9f14d2ee]
 2024-12-09 04:01:22 -05:00
Vladana Stojiljkovic bf9f14d2ee SWDEV-489376 - Fix Unit_hipLaunchHostFunc_Graph memory leaks 
Change-Id: I209f686cb13f05d6b0b790aaa7ab8b93555df3b1
 2024-12-09 04:01:22 -05:00
Branislav Brzak 92b1136755 SWDEV-490860 - Do signal_is_required detection post graph schedule 
Change-Id: Iaf1067a811aeac3d16c08de954036e219b545e07


[ROCm/clr commit: 89dfdc4dbe]
 2024-12-09 03:57:44 -05:00
Branislav Brzak 89dfdc4dbe SWDEV-490860 - Do signal_is_required detection post graph schedule 
Change-Id: Iaf1067a811aeac3d16c08de954036e219b545e07
 2024-12-09 03:57:44 -05:00
Anusha GodavarthySurya 4957a7b5cd SWDEV-485904 - Fix mem leak with Unit_hipMemSetAccess_negative 
Change-Id: I6339ec290d901a6fc5cf33e33a71bf1b86f635ae


[ROCm/hip-tests commit: 984731b3ec]
 2024-12-09 03:51:09 -05:00
Anusha GodavarthySurya 984731b3ec SWDEV-485904 - Fix mem leak with Unit_hipMemSetAccess_negative 
Change-Id: I6339ec290d901a6fc5cf33e33a71bf1b86f635ae
 2024-12-09 03:51:09 -05:00
Charis Poag 5d7555e586 [SWDEV-475712] Fix MI2x target_graphics_version 
Removed correcting target_graphics_version by
product name. Instead detected target_graphics_version which
needs to be corrected -> populate accordingly.

Change-Id: I90765c87e0629daea5c732dace8acfd17e8c62c7
Signed-off-by: Charis Poag <Charis.Poag@amd.com>


[ROCm/rocm_smi_lib commit: 8488518b1c]
 2024-12-08 22:01:43 -06:00
Charis Poag 8488518b1c [SWDEV-475712] Fix MI2x target_graphics_version 
Removed correcting target_graphics_version by
product name. Instead detected target_graphics_version which
needs to be corrected -> populate accordingly.

Change-Id: I90765c87e0629daea5c732dace8acfd17e8c62c7
Signed-off-by: Charis Poag <Charis.Poag@amd.com>
 2024-12-08 22:01:43 -06:00
Jaydeep Patel a7406bbd5d SWDEV-502532 - Exit graph launch in case of empty graph. 
Change-Id: Ifb6ab14ca6810cbc1c9e38c59d1d9e7d367358d9


[ROCm/clr commit: 0d4823ff88]
 2024-12-07 12:27:53 -05:00
Jaydeep Patel 0d4823ff88 SWDEV-502532 - Exit graph launch in case of empty graph. 
Change-Id: Ifb6ab14ca6810cbc1c9e38c59d1d9e7d367358d9
 2024-12-07 12:27:53 -05:00