76333 Commits

Autor SHA1 Mensaje Fecha
Nilesh M Negi 7ca67f1cb9 [BUILD] Update install.sh for RCCL build (#1191)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>

[ROCm/rccl commit: 5aaf7121d9]
2024-05-31 17:58:34 -05:00
Nilesh M Negi 5aaf7121d9 [BUILD] Update install.sh for RCCL build (#1191)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>
2024-05-31 17:58:34 -05:00
Nilesh M Negi 8518ef4afb [MSCCL]: Move scratch buffer debug msgs to TRACE (#1189)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>

[ROCm/rccl commit: 1249a6c3fd]
2024-05-31 17:54:23 -05:00
Nilesh M Negi 1249a6c3fd [MSCCL]: Move scratch buffer debug msgs to TRACE (#1189)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>
2024-05-31 17:54:23 -05:00
coleramos425 351d8d2141 Missing test case
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 7c06b4d2ae]
2024-05-31 22:02:18 +00:00
coleramos425 7c06b4d2ae Missing test case
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 22:02:18 +00:00
coleramos425 4ce7be32fb Fixing some typos from debug
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 55a31ef880]
2024-05-31 21:46:18 +00:00
coleramos425 55a31ef880 Fixing some typos from debug
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 21:46:18 +00:00
Roopa Malavally 5ba90607ee ROCm SMI Documentation Reorg
Change-Id: I3e4db2c50a43a51eeea4d3e06ba4811ad1859368
Signed-off-by: Charis Poag <Charis.Poag@amd.com>


[ROCm/rocm_smi_lib commit: 2fd36e33ad]
2024-05-31 16:25:35 -05:00
Roopa Malavally 2fd36e33ad ROCm SMI Documentation Reorg
Change-Id: I3e4db2c50a43a51eeea4d3e06ba4811ad1859368
Signed-off-by: Charis Poag <Charis.Poag@amd.com>
2024-05-31 16:25:35 -05:00
Lakshmi Kumar d334d7367b AV1 - VA-API structure for rocdecode (#359)
* vaapi sturctures for rocdecode

* vaapi sturctures for rocdecode

* adjust spacing - review comment

* merge conflicts

* name change for some struct

* removing empty lines

* removing empty lines

[ROCm/rocdecode commit: 751d0ccac7]
2024-05-31 17:17:52 -04:00
Lakshmi Kumar 751d0ccac7 AV1 - VA-API structure for rocdecode (#359)
* vaapi sturctures for rocdecode

* vaapi sturctures for rocdecode

* adjust spacing - review comment

* merge conflicts

* name change for some struct

* removing empty lines

* removing empty lines
2024-05-31 17:17:52 -04:00
coleramos425 38ddf94211 Comply to Python formatting
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 9ff90edc10]
2024-05-31 16:09:58 -05:00
coleramos425 9ff90edc10 Comply to Python formatting
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 1dab1f6062 Remove outdated CTest case from CMakeLists
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: fef13818f9]
2024-05-31 16:09:58 -05:00
coleramos425 fef13818f9 Remove outdated CTest case from CMakeLists
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 d02806639a Update gpu-id on MI300 CI workloads and update test case
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 0315ed4458]
2024-05-31 16:09:58 -05:00
coleramos425 0315ed4458 Update gpu-id on MI300 CI workloads and update test case
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 b046f69ce4 Remove old workloads
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 73f18d20f5]
2024-05-31 16:09:58 -05:00
coleramos425 73f18d20f5 Remove old workloads
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
JoseSantosAMD ebad309264 Updated test_analyze_commands to include mi300 directories
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>


[ROCm/rocprofiler-compute commit: 91f635e3e6]
2024-05-31 16:09:58 -05:00
JoseSantosAMD 91f635e3e6 Updated test_analyze_commands to include mi300 directories
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 2bc71cc0d8 Add vcopy workloads for MI300A and MI300X
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: c079f1330b]
2024-05-31 16:09:58 -05:00
coleramos425 c079f1330b Add vcopy workloads for MI300A and MI300X
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
JoseSantosAMD 34b289e66d updating expected exit codes for pytest
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>


[ROCm/rocprofiler-compute commit: db7d77ca3f]
2024-05-31 16:09:58 -05:00
JoseSantosAMD db7d77ca3f updating expected exit codes for pytest
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-05-31 16:09:58 -05:00
JoseSantosAMD ec09cf2cca update test analyze scripts
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>


[ROCm/rocprofiler-compute commit: 6d98a1eb5e]
2024-05-31 16:09:58 -05:00
JoseSantosAMD 6d98a1eb5e update test analyze scripts
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 4c3c196c61 Remove debug print statements from profile_general
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 618c064571]
2024-05-31 16:09:58 -05:00
coleramos425 618c064571 Remove debug print statements from profile_general
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 9be67d0cb4 Remove invalid test from workload generation script
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: cdccd93afa]
2024-05-31 16:09:58 -05:00
coleramos425 cdccd93afa Remove invalid test from workload generation script
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 89dc3f650f Add CI workloads for MI300A_A1 and MI300X_A1
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: b8af814467]
2024-05-31 16:09:58 -05:00
coleramos425 b8af814467 Add CI workloads for MI300A_A1 and MI300X_A1
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 9edb0fb72d Remove redundant code in PyTest
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 7d79fcc276]
2024-05-31 16:09:58 -05:00
coleramos425 7d79fcc276 Remove redundant code in PyTest
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 0158663680 Support MI300 in PyTest profile tests
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 09264591f3]
2024-05-31 16:09:58 -05:00
coleramos425 09264591f3 Support MI300 in PyTest profile tests
Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
coleramos425 23cbe3f595 Create dedicated subdirectory in perfmon configs for archs supporting roofline
Separate subdirs allows us to target different roofline counters for different archs (i.e. MI300 vs MI200)

Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: 49371cacec]
2024-05-31 16:09:58 -05:00
coleramos425 49371cacec Create dedicated subdirectory in perfmon configs for archs supporting roofline
Separate subdirs allows us to target different roofline counters for different archs (i.e. MI300 vs MI200)

Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
Ajay 3e79adaf37 SWDEV-439581 - fix comments for hipEventSynchronize
Change-Id: I81152ff29b9c59015253b736eea3679f4c750530


[ROCm/hip commit: bbe3cc5e77]
2024-05-31 16:47:16 -04:00
Ajay bbe3cc5e77 SWDEV-439581 - fix comments for hipEventSynchronize
Change-Id: I81152ff29b9c59015253b736eea3679f4c750530
2024-05-31 16:47:16 -04:00
jeffqjiangNew 3230cca447 rocDecode: Added decode buffer pool implementation for AVC and HEVC. (#355)
* * rocDecode: Initial check in for decode buffer pool.

* * rocDecode: All 135 streams pass.

* * rocDecode: Fixed a build error in debug mode.

* * rocDecode/HEVC: Removed two workaround in HEVC DPB management, after decode buffer pool implementa
tion.
 - WR 1: Conditional bumping (when max_num_reorder_pics > 0) to avoid synchronous job submission in
C.5.2.3.
 - WR 2: Add two more buffers in DPB to avoid buffer over-writing.

* * rocDecode/HEVC: Added display delay feature.

* * rocDecode/HEVC: Fixed the -z option issue within the context of the new decode buffer pool implementation.

* * rocDecode/HEVC: Removed redundent code.

* * rocDecode/AVC: Added decode buffer pool implementation for AVC.

* * rocDecode: Added a few changes.
 - Added display delay feature to AVC.
 - Removed a workaround for AVC: AVC_MAX_DPB_FRAMES was increased to 18. Now it is back to 16.
 - Removed a workaround for AVC: increased DPB buffer size by 2. Now it is back to normal.
 - Code format changes for HEVC.

* * rocDecode/AVC: Fixed the -z option issue within the context of the new decode buffer pool implementation.

* * rocDecode: Merged OutputDecodedPictures() method to upper class RocVideoParser.

* * rocDecode: Code cleanup. No functional changes.

* * rocDecode: Made decode buffer pool size adaptive.
 - Removed the hard coded decode buffer pool size set in the decoder.
 - Exposed the display delay parameter from RocVideoDecoder class to the user.
 - Now the decoder buffer pool size is determined from the DPB buffer size and display delay parameter.

* * rocDecode: Several changes based on code review.
 - Merged decode and display use status into one parameter.
 - Removed the surface index from DecodeFrameBuffer, which is now implicitly referred by the array index.
 - Changed a function name for better clarity.

* * rocDecode: Added a comment.

[ROCm/rocdecode commit: 61c8661b9c]
2024-05-31 13:14:02 -04:00
jeffqjiangNew 61c8661b9c rocDecode: Added decode buffer pool implementation for AVC and HEVC. (#355)
* * rocDecode: Initial check in for decode buffer pool.

* * rocDecode: All 135 streams pass.

* * rocDecode: Fixed a build error in debug mode.

* * rocDecode/HEVC: Removed two workaround in HEVC DPB management, after decode buffer pool implementa
tion.
 - WR 1: Conditional bumping (when max_num_reorder_pics > 0) to avoid synchronous job submission in
C.5.2.3.
 - WR 2: Add two more buffers in DPB to avoid buffer over-writing.

* * rocDecode/HEVC: Added display delay feature.

* * rocDecode/HEVC: Fixed the -z option issue within the context of the new decode buffer pool implementation.

* * rocDecode/HEVC: Removed redundent code.

* * rocDecode/AVC: Added decode buffer pool implementation for AVC.

* * rocDecode: Added a few changes.
 - Added display delay feature to AVC.
 - Removed a workaround for AVC: AVC_MAX_DPB_FRAMES was increased to 18. Now it is back to 16.
 - Removed a workaround for AVC: increased DPB buffer size by 2. Now it is back to normal.
 - Code format changes for HEVC.

* * rocDecode/AVC: Fixed the -z option issue within the context of the new decode buffer pool implementation.

* * rocDecode: Merged OutputDecodedPictures() method to upper class RocVideoParser.

* * rocDecode: Code cleanup. No functional changes.

* * rocDecode: Made decode buffer pool size adaptive.
 - Removed the hard coded decode buffer pool size set in the decoder.
 - Exposed the display delay parameter from RocVideoDecoder class to the user.
 - Now the decoder buffer pool size is determined from the DPB buffer size and display delay parameter.

* * rocDecode: Several changes based on code review.
 - Merged decode and display use status into one parameter.
 - Removed the surface index from DecodeFrameBuffer, which is now implicitly referred by the array index.
 - Changed a function name for better clarity.

* * rocDecode: Added a comment.
2024-05-31 13:14:02 -04:00
Aryan Salmanpour 46902dc30d Update docs and README (#29)
[ROCm/rocjpeg commit: 417a5f5c92]
2024-05-31 12:36:12 -04:00
Aryan Salmanpour 417a5f5c92 Update docs and README (#29) 2024-05-31 12:36:12 -04:00
Maisam Arif 7c6bd4dc1c Updated RDC to use AMD-SMI 24.6.0 structs
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I9ef0f3cb786c1238e53cf21df5c6afafac829175
2024-05-31 10:37:39 -05:00
Maisam Arif d9adf280cd Updated RDC to use AMD-SMI 24.6.0 structs
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I9ef0f3cb786c1238e53cf21df5c6afafac829175


[ROCm/rdc commit: 7c6bd4dc1c]
2024-05-31 10:37:39 -05:00
Young Hui - AMD 4a6e9d709b Docs: reordered index grid (#345)
* reordered index to have separate install card, and diataxis grid

* add Tutorials folder

* Explain that tutorials/README.md is just a blank placeholder file.  Can be removed in future.

* Update docs/index.rst

Co-authored-by: Leo Paoletti <164940351+lpaoletti@users.noreply.github.com>

* changed to quick start (no hyphen)

* missed index.rst for quick start edit

* change text to Using rocDecode

---------

Co-authored-by: Leo Paoletti <164940351+lpaoletti@users.noreply.github.com>

[ROCm/rocdecode commit: 7f5cc9c42f]
2024-05-31 10:12:24 -04:00
Young Hui - AMD 7f5cc9c42f Docs: reordered index grid (#345)
* reordered index to have separate install card, and diataxis grid

* add Tutorials folder

* Explain that tutorials/README.md is just a blank placeholder file.  Can be removed in future.

* Update docs/index.rst

Co-authored-by: Leo Paoletti <164940351+lpaoletti@users.noreply.github.com>

* changed to quick start (no hyphen)

* missed index.rst for quick start edit

* change text to Using rocDecode

---------

Co-authored-by: Leo Paoletti <164940351+lpaoletti@users.noreply.github.com>
2024-05-31 10:12:24 -04:00