This reverts commit f94be2078c.
Change-Id: I954326d9a291280de7c9b7ef49a8cce0cd9dd9ad
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: a809a5bf32]
This reverts commit 559bb50c6a.
Change-Id: Ibd32ac36bcb9ee418957d25b240ef9dd9172fbd3
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 91b0fce535]
This reverts commit 14d821391e.
Change-Id: Idf636655ac01f569d8e92e9c0e100e5db7d1cb61
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 445fcd803b]
Map readonly range to GPU, test GPU can read range but write to
range trigger GPU vm fault.
Change-Id: Id2ce106055a353f21f4c34fa7f562d546523bc49
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Map readonly range to GPU, test GPU can read range but write to
range trigger GPU vm fault.
Change-Id: Id2ce106055a353f21f4c34fa7f562d546523bc49
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: f9648c5014]
To test if SVM support address mmap on file backed memory.
Change-Id: I227cc0b44d167c4fa2e63257e13a481aefa4f750
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
To test if SVM support address mmap on file backed memory.
Change-Id: I227cc0b44d167c4fa2e63257e13a481aefa4f750
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: d91f92669b]
1. Fix hipMallocManagedMultiChunkMultiDevice
Add device setting before kernel launching
Add stream sync
2. Fix hipMemcpyAtoH and hipMemcpyHtoA
Fix primary context initialization issue when device
is changed on cuda
Change-Id: I3fe6dbc35b7b24abb21ada297b7885df83d28152
1. Simply enable test on NV
Some need minor fix
performance/compute/hipPerfDotProduct.cpp
performance/dispatch/hipPerfDispatchSpeed.cpp
performance/memory/hipPerfBufferCopyRectSpeed.cpp
performance/memory/hipPerfBufferCopySpeed.cpp
performance/memory/hipPerfDevMemReadSpeed.cpp
performance/memory/hipPerfDevMemWriteSpeed.cpp
performance/memory/hipPerfMemcpy.cpp
performance/memory/hipPerfMemset.cpp
performance/memory/hipPerfSharedMemReadSpeed.cpp
performance/stream/hipPerfDeviceConcurrency.cpp
performance/stream/hipPerfStreamCreateCopyDestroy.cpp
2. Enable and fix on NV
performance/compute/hipPerfMandelbrot.cpp
Root cause: coordIdx is random
Solution: Initialize coordIdx correctly
performance/memory/hipPerfMemFill.cpp
Root cause: Hip ext Apis called.
Solution: Exclude case with Hip ext Apis involved
performance/memory/hipPerfMemMallocCpyFree.cpp
Root cause: Test allocates device memory more than GPU has.
Solution: Allocate device memory in terms of GPU capacity.
tests/performance/memory/hipPerfSampleRate.cpp
Root cause: Cuda has no operators += for float2 and float4.
Solution: Provide the operators.
performance/stream/hipPerfStreamConcurrency.cpp
Root cause:float4 format doesn't match cude.
operators are missing in cuda lib.
Solution: Use (x, y, z, w) format.
Add necessary float4 operatoris for cuda.
Change-Id: I5add29ebabcfb21fb3ef89d09004c5d13423a291
[ROCm/hip-tests commit: bfc2f4516a]
1. Simply enable test on NV
Some need minor fix
performance/compute/hipPerfDotProduct.cpp
performance/dispatch/hipPerfDispatchSpeed.cpp
performance/memory/hipPerfBufferCopyRectSpeed.cpp
performance/memory/hipPerfBufferCopySpeed.cpp
performance/memory/hipPerfDevMemReadSpeed.cpp
performance/memory/hipPerfDevMemWriteSpeed.cpp
performance/memory/hipPerfMemcpy.cpp
performance/memory/hipPerfMemset.cpp
performance/memory/hipPerfSharedMemReadSpeed.cpp
performance/stream/hipPerfDeviceConcurrency.cpp
performance/stream/hipPerfStreamCreateCopyDestroy.cpp
2. Enable and fix on NV
performance/compute/hipPerfMandelbrot.cpp
Root cause: coordIdx is random
Solution: Initialize coordIdx correctly
performance/memory/hipPerfMemFill.cpp
Root cause: Hip ext Apis called.
Solution: Exclude case with Hip ext Apis involved
performance/memory/hipPerfMemMallocCpyFree.cpp
Root cause: Test allocates device memory more than GPU has.
Solution: Allocate device memory in terms of GPU capacity.
tests/performance/memory/hipPerfSampleRate.cpp
Root cause: Cuda has no operators += for float2 and float4.
Solution: Provide the operators.
performance/stream/hipPerfStreamConcurrency.cpp
Root cause:float4 format doesn't match cude.
operators are missing in cuda lib.
Solution: Use (x, y, z, w) format.
Add necessary float4 operatoris for cuda.
Change-Id: I5add29ebabcfb21fb3ef89d09004c5d13423a291
1. Simply enable test on NV
Some need minor fix
performance/compute/hipPerfDotProduct.cpp
performance/dispatch/hipPerfDispatchSpeed.cpp
performance/memory/hipPerfBufferCopyRectSpeed.cpp
performance/memory/hipPerfBufferCopySpeed.cpp
performance/memory/hipPerfDevMemReadSpeed.cpp
performance/memory/hipPerfDevMemWriteSpeed.cpp
performance/memory/hipPerfMemcpy.cpp
performance/memory/hipPerfMemset.cpp
performance/memory/hipPerfSharedMemReadSpeed.cpp
performance/stream/hipPerfDeviceConcurrency.cpp
performance/stream/hipPerfStreamCreateCopyDestroy.cpp
2. Enable and fix on NV
performance/compute/hipPerfMandelbrot.cpp
Root cause: coordIdx is random
Solution: Initialize coordIdx correctly
performance/memory/hipPerfMemFill.cpp
Root cause: Hip ext Apis called.
Solution: Exclude case with Hip ext Apis involved
performance/memory/hipPerfMemMallocCpyFree.cpp
Root cause: Test allocates device memory more than GPU has.
Solution: Allocate device memory in terms of GPU capacity.
tests/performance/memory/hipPerfSampleRate.cpp
Root cause: Cuda has no operators += for float2 and float4.
Solution: Provide the operators.
performance/stream/hipPerfStreamConcurrency.cpp
Root cause:float4 format doesn't match cude.
operators are missing in cuda lib.
Solution: Use (x, y, z, w) format.
Add necessary float4 operatoris for cuda.
Change-Id: I5add29ebabcfb21fb3ef89d09004c5d13423a291
[ROCm/hip commit: 9035ae3154]
1. Simply enable test on NV
Some need minor fix
performance/compute/hipPerfDotProduct.cpp
performance/dispatch/hipPerfDispatchSpeed.cpp
performance/memory/hipPerfBufferCopyRectSpeed.cpp
performance/memory/hipPerfBufferCopySpeed.cpp
performance/memory/hipPerfDevMemReadSpeed.cpp
performance/memory/hipPerfDevMemWriteSpeed.cpp
performance/memory/hipPerfMemcpy.cpp
performance/memory/hipPerfMemset.cpp
performance/memory/hipPerfSharedMemReadSpeed.cpp
performance/stream/hipPerfDeviceConcurrency.cpp
performance/stream/hipPerfStreamCreateCopyDestroy.cpp
2. Enable and fix on NV
performance/compute/hipPerfMandelbrot.cpp
Root cause: coordIdx is random
Solution: Initialize coordIdx correctly
performance/memory/hipPerfMemFill.cpp
Root cause: Hip ext Apis called.
Solution: Exclude case with Hip ext Apis involved
performance/memory/hipPerfMemMallocCpyFree.cpp
Root cause: Test allocates device memory more than GPU has.
Solution: Allocate device memory in terms of GPU capacity.
tests/performance/memory/hipPerfSampleRate.cpp
Root cause: Cuda has no operators += for float2 and float4.
Solution: Provide the operators.
performance/stream/hipPerfStreamConcurrency.cpp
Root cause:float4 format doesn't match cude.
operators are missing in cuda lib.
Solution: Use (x, y, z, w) format.
Add necessary float4 operatoris for cuda.
Change-Id: I5add29ebabcfb21fb3ef89d09004c5d13423a291
* SWDEV-266829 - Enable more tests on AMD and NV devices
1. Enable tests on AMD and NV devices
tests/src/runtimeApi/event/hipEventMultiThreaded.cpp
Loops and threads per core are changed smaller so that test can
finish in a shorter time.
tests/src/runtimeApi/stream/hipStreamCreateWithPriority.cpp
Fix logic error on how to get priority_normal
2. Simply enable test on AMD device
tests/src/runtimeApi/memory/hipManagedKeyword.cpp
tests/src/runtimeApi/module/hipManagedKeyword.cpp
tests/src/runtimeApi/stream/hipStreamACb_MultiThread.cpp
tests/src/runtimeApi/memory/p2p_copy_coherency.cpp
3. Simply enable test on NV device
tests/src/runtimeApi/module/hipModuleLoadDataMultThreaded.cpp
4. Fix typo
tests/src/runtimeApi/stream/hipStreamAddCallbackCatch.cpp
5. Remove useless tests
tests/src/hipC.c
tests/src/hipHcc.cpp
Change-Id: Ia4406353e64d69bd34c58ebb56185701f7ce1caa
* Remove tests/src/runtimeApi/module/hipModuleLoadDataMultThreaded.cpp for cuda test
Co-authored-by: anusha GodavarthySurya <Anusha.GodavarthySurya@amd.com>
Co-authored-by: Jenkins <jenkins-compute@amd.com>
[ROCm/hip commit: 3fd16c0b5b]
* SWDEV-266829 - Enable more tests on AMD and NV devices
1. Enable tests on AMD and NV devices
tests/src/runtimeApi/event/hipEventMultiThreaded.cpp
Loops and threads per core are changed smaller so that test can
finish in a shorter time.
tests/src/runtimeApi/stream/hipStreamCreateWithPriority.cpp
Fix logic error on how to get priority_normal
2. Simply enable test on AMD device
tests/src/runtimeApi/memory/hipManagedKeyword.cpp
tests/src/runtimeApi/module/hipManagedKeyword.cpp
tests/src/runtimeApi/stream/hipStreamACb_MultiThread.cpp
tests/src/runtimeApi/memory/p2p_copy_coherency.cpp
3. Simply enable test on NV device
tests/src/runtimeApi/module/hipModuleLoadDataMultThreaded.cpp
4. Fix typo
tests/src/runtimeApi/stream/hipStreamAddCallbackCatch.cpp
5. Remove useless tests
tests/src/hipC.c
tests/src/hipHcc.cpp
Change-Id: Ia4406353e64d69bd34c58ebb56185701f7ce1caa
* Remove tests/src/runtimeApi/module/hipModuleLoadDataMultThreaded.cpp for cuda test
Co-authored-by: anusha GodavarthySurya <Anusha.GodavarthySurya@amd.com>
Co-authored-by: Jenkins <jenkins-compute@amd.com>
* Use relaxed atomics and add sleep and wakeup in barrier loop
* atomicAdd in ROCm 4.3 only support unsigned long long
* Switch to atomicAdd and atomicExch in more places
* Restore LOAD/STORE define to __ATOMIC_SEQ_CST
* Restore atomic for sizes FIFO
[ROCm/rccl commit: 020484bf40]
* Use relaxed atomics and add sleep and wakeup in barrier loop
* atomicAdd in ROCm 4.3 only support unsigned long long
* Switch to atomicAdd and atomicExch in more places
* Restore LOAD/STORE define to __ATOMIC_SEQ_CST
* Restore atomic for sizes FIFO
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE
Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
[ROCm/clr commit: d8a86e4870]
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE
Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.
Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975
[ROCm/clr commit: 65ddfcc6a8]
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.
Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975
Philip Yang
agunashe
sumanthtg
TomSang
Julia Jiang
Chauncey Hui
Satyanvesh Dittakavi
Wenkai Du
German Andryeyev
Jonathan R. Madsen