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Payam 2e52ceca29 SWDEV-182753 - Throw error if launch params>bounds 
Change-Id: I5f9931efac37e3149894ca116a1b0c2dcc3e5bc5
 2021-03-12 19:17:08 -05:00
Payam d372df5d34 SWDEV-182753 - Throw error if launch params>bounds 
Change-Id: I5f9931efac37e3149894ca116a1b0c2dcc3e5bc5


[ROCm/hip commit: f17adc439c]
 2021-03-12 19:17:08 -05:00
Payam f17adc439c SWDEV-182753 - Throw error if launch params>bounds 
Change-Id: I5f9931efac37e3149894ca116a1b0c2dcc3e5bc5
 2021-03-12 19:17:08 -05:00
German Andryeyev 890afbf666 SWDEV-276631 - return error codes for clCreateEventFromGLsyncKHR() 
Change-Id: I9b93f5bde157d0f746a9d662ef35fbbb20cce6e6


[ROCm/clr commit: 9aebe61637]
 2021-03-12 14:34:59 -05:00
German Andryeyev 9aebe61637 SWDEV-276631 - return error codes for clCreateEventFromGLsyncKHR() 
Change-Id: I9b93f5bde157d0f746a9d662ef35fbbb20cce6e6
 2021-03-12 14:34:59 -05:00
Chauncey Hui b367058ccf SWDEV-2 - Change OpenCL version number from 3274 to 3275 
[ROCm/clr commit: dc58078887]
 2021-03-12 03:00:05 -05:00
Chauncey Hui dc58078887 SWDEV-2 - Change OpenCL version number from 3274 to 3275 2021-03-12 03:00:05 -05:00
Saleel Kudchadker f2a7ea3927 SWDEV-271010 - Increase active wait time 
Increase wait time for active wait to 50us

Change-Id: I8f269ab25ecc6775e655b9eb36fafc5f41a59c95


[ROCm/clr commit: d034c48405]
 2021-03-11 13:16:59 -08:00
Saleel Kudchadker d034c48405 SWDEV-271010 - Increase active wait time 
Increase wait time for active wait to 50us

Change-Id: I8f269ab25ecc6775e655b9eb36fafc5f41a59c95
 2021-03-11 13:16:59 -08:00
Saleel Kudchadker 459ec08f99 SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77


[ROCm/hip-tests commit: 7023d87e72]
 2021-03-11 11:01:54 -08:00
Saleel Kudchadker 7023d87e72 SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77
 2021-03-11 11:01:54 -08:00
Saleel Kudchadker 49d2182dc7 SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77


[ROCm/clr commit: 47e44117cd]
 2021-03-11 11:01:54 -08:00
Saleel Kudchadker 47e44117cd SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77
 2021-03-11 11:01:54 -08:00
Saleel Kudchadker b511383959 SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77


[ROCm/hip commit: d6f331697d]
 2021-03-11 11:01:54 -08:00
Saleel Kudchadker d6f331697d SWDEV-271010 - Add 512KB transfer size for test 
Add a new transfer to hipPerfBufferCopySpeed test

Change-Id: Ia7ec9a89e8789bf16fd5f86b08521287049c1e77
 2021-03-11 11:01:54 -08:00
Felix Kuehling d287c60246 libhsakmt: New SRAM EDC support bit 
The old bit was deprecated, because old buggy user mode depends on it
being always 0. The correct value is now reported in a new bit. New user
mode handles the reported EDC setting correctly, so we can report the
correct value in a new bit.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: Ib5d5ed2519810e650458c6b69c97670dab435ddb
 2021-03-11 13:37:45 -05:00
Felix Kuehling 4493f63d55 libhsakmt: New SRAM EDC support bit 
The old bit was deprecated, because old buggy user mode depends on it
being always 0. The correct value is now reported in a new bit. New user
mode handles the reported EDC setting correctly, so we can report the
correct value in a new bit.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: Ib5d5ed2519810e650458c6b69c97670dab435ddb


[ROCm/ROCR-Runtime commit: d287c60246]
 2021-03-11 13:37:45 -05:00
kjayapra-amd 449cc5096e SWDEV-276169 - Multiprocess IPC tests for Events and Memory. 
Change-Id: I4a7af60e732de234a535574aa8597a7abd0b899b


[ROCm/clr commit: 57615530a7]
 2021-03-11 11:16:23 -05:00
kjayapra-amd 57615530a7 SWDEV-276169 - Multiprocess IPC tests for Events and Memory. 
Change-Id: I4a7af60e732de234a535574aa8597a7abd0b899b
 2021-03-11 11:16:23 -05:00
kjayapra-amd b8e5485f00 SWDEV-276169 - Multiprocess IPC tests for Events and Memory. 
Change-Id: I4a7af60e732de234a535574aa8597a7abd0b899b


[ROCm/hip commit: 0bed2779aa]
 2021-03-11 11:16:23 -05:00
kjayapra-amd 0bed2779aa SWDEV-276169 - Multiprocess IPC tests for Events and Memory. 
Change-Id: I4a7af60e732de234a535574aa8597a7abd0b899b
 2021-03-11 11:16:23 -05:00
Chauncey Hui 9aaec719a3 SWDEV-2 - Change OpenCL version number from 3273 to 3274 
[ROCm/clr commit: 982f6b4159]
 2021-03-11 03:00:06 -05:00
Chauncey Hui 982f6b4159 SWDEV-2 - Change OpenCL version number from 3273 to 3274 2021-03-11 03:00:06 -05:00
Felix Kuehling 41cd7aea2f Revert "libhsakmt: add kfd_ioctl.h svm and xnack support" 
This reverts commit 5ae49f2321.
SVM is not ready yet. This was merged by accident.

Change-Id: I8901594a72e785ba5d25a6448718a570e76fe117
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2021-03-10 22:33:49 -05:00
Felix Kuehling 3be7292742 Revert "libhsakmt: add kfd_ioctl.h svm and xnack support" 
This reverts commit 07b0758bee.
SVM is not ready yet. This was merged by accident.

Change-Id: I8901594a72e785ba5d25a6448718a570e76fe117
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 41cd7aea2f]
 2021-03-10 22:33:49 -05:00
Felix Kuehling 5edd00136d Revert "libhsakmt: add API to support svm and xnack" 
This reverts commit a352639df5.
SVM is not ready yet. This was merged by accident.

Change-Id: I1bee102823e7e612be8e8f2e0f50580e8692cc80
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2021-03-10 22:33:49 -05:00
Felix Kuehling cb956dc239 Revert "libhsakmt: add API to support svm and xnack" 
This reverts commit 08e65a397a.
SVM is not ready yet. This was merged by accident.

Change-Id: I1bee102823e7e612be8e8f2e0f50580e8692cc80
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 5edd00136d]
 2021-03-10 22:33:49 -05:00
Felix Kuehling 4ebda913cd Revert "libhsakmt: add SVM thunk implementation" 
This reverts commit 75e8fe383f.
SVM is not ready yet. This was merged by accident.

Change-Id: I372f7d293fd38429ec570bc0e0add7e612871594
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2021-03-10 22:33:34 -05:00
Felix Kuehling 9216fb99b8 Revert "libhsakmt: add SVM thunk implementation" 
This reverts commit a247255a6a.
SVM is not ready yet. This was merged by accident.

Change-Id: I372f7d293fd38429ec570bc0e0add7e612871594
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 4ebda913cd]
 2021-03-10 22:33:34 -05:00
Felix Kuehling a8f4c43fef Revert "libhsakmt: add XNACK API set/get mode" 
This reverts commit 3f45f602d4.
SVM is not ready yet. This was merged by accident.

Change-Id: I7c0d835a0d3a448f2ac1094f818601e5d6363045
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
 2021-03-10 20:34:43 -05:00
Felix Kuehling 0a400cac45 Revert "libhsakmt: add XNACK API set/get mode" 
This reverts commit 2c1c2cfdf8.
SVM is not ready yet. This was merged by accident.

Change-Id: I7c0d835a0d3a448f2ac1094f818601e5d6363045
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: a8f4c43fef]
 2021-03-10 20:34:43 -05:00
Jason Tang 64f4e4c01c SWDEV-3 - Backport M0 changes 
Change-Id: I36f676713442479ede142b7e887656f0b658bc7b


[ROCm/clr commit: 8d01cbddbe]
 2021-03-10 10:25:42 -05:00
Jason Tang 8d01cbddbe SWDEV-3 - Backport M0 changes 
Change-Id: I36f676713442479ede142b7e887656f0b658bc7b
 2021-03-10 10:25:42 -05:00
Lakhan singh Thakur 3064521743 SWDEV-238517 - Enhancing hip unit tests 
[dtest] Additional tests for Memcpy

APIs tested:
      hipMemcpy, hipMemcpyAsync,
      hipMemcpyHtoD, hipMemcpyHtoDAsync,
      hipMemcpyDtoH, hipMemcpyDtoHAsync,
      hipMemcpyDtoD, hipMemcpyDtoDAsync

1: The aim of this test case is to cover all
   the negative test cases for 8 hipMemcpy apis
2: This test launches NUM_THREADS threads.
   Each thread in turn tests the working of
   8 hipmemcpy apis
3: This test case verifies the working of
   Memcpy apis for range of memory sizes from
   smallest one unit transfer to 1GB.

Change-Id: If5c99527a78e817bafab2e1bd9b686a9ff916184


[ROCm/clr commit: d4041fae4a]
 2021-03-10 10:14:36 -05:00
Lakhan singh Thakur d4041fae4a SWDEV-238517 - Enhancing hip unit tests 
[dtest] Additional tests for Memcpy

APIs tested:
      hipMemcpy, hipMemcpyAsync,
      hipMemcpyHtoD, hipMemcpyHtoDAsync,
      hipMemcpyDtoH, hipMemcpyDtoHAsync,
      hipMemcpyDtoD, hipMemcpyDtoDAsync

1: The aim of this test case is to cover all
   the negative test cases for 8 hipMemcpy apis
2: This test launches NUM_THREADS threads.
   Each thread in turn tests the working of
   8 hipmemcpy apis
3: This test case verifies the working of
   Memcpy apis for range of memory sizes from
   smallest one unit transfer to 1GB.

Change-Id: If5c99527a78e817bafab2e1bd9b686a9ff916184
 2021-03-10 10:14:36 -05:00
Lakhan singh Thakur 640c7cede8 SWDEV-238517 - Enhancing hip unit tests 
[dtest] Additional tests for Memcpy

APIs tested:
      hipMemcpy, hipMemcpyAsync,
      hipMemcpyHtoD, hipMemcpyHtoDAsync,
      hipMemcpyDtoH, hipMemcpyDtoHAsync,
      hipMemcpyDtoD, hipMemcpyDtoDAsync

1: The aim of this test case is to cover all
   the negative test cases for 8 hipMemcpy apis
2: This test launches NUM_THREADS threads.
   Each thread in turn tests the working of
   8 hipmemcpy apis
3: This test case verifies the working of
   Memcpy apis for range of memory sizes from
   smallest one unit transfer to 1GB.

Change-Id: If5c99527a78e817bafab2e1bd9b686a9ff916184


[ROCm/hip commit: da723c8807]
 2021-03-10 10:14:36 -05:00
Lakhan singh Thakur da723c8807 SWDEV-238517 - Enhancing hip unit tests 
[dtest] Additional tests for Memcpy

APIs tested:
      hipMemcpy, hipMemcpyAsync,
      hipMemcpyHtoD, hipMemcpyHtoDAsync,
      hipMemcpyDtoH, hipMemcpyDtoHAsync,
      hipMemcpyDtoD, hipMemcpyDtoDAsync

1: The aim of this test case is to cover all
   the negative test cases for 8 hipMemcpy apis
2: This test launches NUM_THREADS threads.
   Each thread in turn tests the working of
   8 hipmemcpy apis
3: This test case verifies the working of
   Memcpy apis for range of memory sizes from
   smallest one unit transfer to 1GB.

Change-Id: If5c99527a78e817bafab2e1bd9b686a9ff916184
 2021-03-10 10:14:36 -05:00
Chauncey Hui e9edf23f52 SWDEV-2 - Change OpenCL version number from 3272 to 3273 
[ROCm/clr commit: 6cc43d0807]
 2021-03-10 03:00:06 -05:00
Chauncey Hui 6cc43d0807 SWDEV-2 - Change OpenCL version number from 3272 to 3273 2021-03-10 03:00:06 -05:00
Evgeny c46913cdd6 SWDEV-274603 : fix SPM mode enabling 
Change-Id: I67d9ecd8c808989315b2991ec492af2a4dd4ccbf
 2021-03-10 01:27:28 -06:00
Evgeny 02d06d0c19 SWDEV-274603 : fix SPM mode enabling 
Change-Id: I67d9ecd8c808989315b2991ec492af2a4dd4ccbf


[ROCm/rocprofiler commit: c46913cdd6]
 2021-03-10 01:27:28 -06:00
Evgeny 76f7c9a5fd SWDEV-267198 : adding gpu index to hsa_handles file 
Change-Id: I6ddba45ab31fff97a1f85f889c56693accf8f5bc


[ROCm/roctracer commit: 1c77416a6c]
 2021-03-09 15:37:44 -06:00
Evgeny 1c77416a6c SWDEV-267198 : adding gpu index to hsa_handles file 
Change-Id: I6ddba45ab31fff97a1f85f889c56693accf8f5bc
 2021-03-09 15:37:44 -06:00
jujiang 7020872b45 SWDEV-270961 - Add doxygen for Texture APIs 
Change-Id: I4038320a638292440d9ca8c23ffcabffcd9a48c2


[ROCm/clr commit: 3126196cca]
 2021-03-09 16:23:56 -05:00
jujiang 3126196cca SWDEV-270961 - Add doxygen for Texture APIs 
Change-Id: I4038320a638292440d9ca8c23ffcabffcd9a48c2
 2021-03-09 16:23:56 -05:00
jujiang f9b7d37bea SWDEV-270961 - Add doxygen for Texture APIs 
Change-Id: I4038320a638292440d9ca8c23ffcabffcd9a48c2


[ROCm/hip commit: 3498f3600a]
 2021-03-09 16:23:56 -05:00
jujiang 3498f3600a SWDEV-270961 - Add doxygen for Texture APIs 
Change-Id: I4038320a638292440d9ca8c23ffcabffcd9a48c2
 2021-03-09 16:23:56 -05:00
Vladislav Sytchenko 16aedba832 SWDEV-232428 - Fix CI regressions caused by 9eb113d 
Change-Id: I6523a8abc19dc5b01f7eacb3a949da01afae60d5


[ROCm/clr commit: 07702bb28f]
 2021-03-09 13:50:13 -05:00
Vladislav Sytchenko 07702bb28f SWDEV-232428 - Fix CI regressions caused by 99e8ac5 
Change-Id: I6523a8abc19dc5b01f7eacb3a949da01afae60d5
 2021-03-09 13:50:13 -05:00
Rahul Garg 513c951343 SWDEV-270599 - hipExtLaunchKernelGGL Event Timing Incorrect Between Two Launches 
Change-Id: I599a51720f297209072c6be8fffe2aa61e1a071e


[ROCm/clr commit: cc17122987]
 2021-03-09 12:18:39 -05:00