نمودار کامیت

470 کامیت‌ها

مولف SHA1 پیام تاریخ
Ioannis Assiouras 35629e433d SWDEV-546146 - Added support for hipMemLocationTypeHost in hipMemSetAccess (#682) 2025-09-10 23:06:20 +01:00
Ioannis Assiouras 4c6fce8ba0 SWDEV-546223 - Remove comgr query for image support from windows path (#861) 2025-09-09 07:54:48 +05:30
SaleelK e197aa83ba SWDEV-543723 - Execute permission for kernArg buf (#728)
- Refactor deviceLocalAlloc arguments
- Refactor hostAlloc code, have cleaner interface
- Kern args buffer need to have execute flag set as CP enforces this on
  certain newer HW.
2025-09-08 12:21:30 -07:00
Ajay GunaShekar d4435bb74a SWDEV-552573 - restore asm file before clang formatting (#802)
* Restore asm file before clang formatting
* Surround inline assembly in clang-format off
2025-09-03 14:26:49 +05:30
Ioannis Assiouras a1c30318fb SWDEV-546223 - Get image support info from ISA meta (#773) 2025-09-02 15:05:18 +01:00
Danylo Lytovchenko 2ff2316227 Adjust clang format to the new versions, revert broken macro layout (#714) 2025-08-22 17:23:22 +02:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
GunaShekar, Ajay bfcf0ef4e8 SWDEV-543366 - Bump PAL_CLIENT_INTERFACE_MAJOR_VERSION 916 --> 932 (#725)
Co-authored-by: Lin, Qun <Quentin.Lin@amd.com>
Co-authored-by: Lin,Qun <qlin@amd.com>

[ROCm/clr commit: ed903e8889]
2025-08-08 08:45:42 -07:00
Xie, Pengda 9cbbee4d6e SWDEV-520384 - Improve Fat Binary loading latency (#390)
Init and fini kernel needs to be launched when we load and unload code object. Avoid looping through all kernels within a code object just to run the init and fini kernels. Compiler currently only generates 1 init and fini kernel.

[ROCm/clr commit: cd46294b31]
2025-08-05 14:02:05 -07:00
Xie, Jiabao(Jimbo) e5226f2b7e SWDEV-460151 - add gfx1201 to amd-staging clr (#183)
* SWDEV-460151 - add gfx1201 to amd-staging clr

* SWDEV-460151 - removed pal macro

---------

Co-authored-by: Jimbo Xie <jiabaxie@amd.com>

[ROCm/clr commit: a5d932f160]
2025-07-11 08:51:47 -07:00
Sang, Tao 7fd322af90 SWDEV-508776 - support VGPRs validation (#274)
Clarify some VGPRs terms description.
Fix some wrong query logics of availableVGPRs_ and
availableRegistersPerCU_ in device info.
Add hipDeviceAttributeMaxAvailableVgprsPerThread
attribute query.
Remove hardcoding of following
 info_.vgprAllocGranularity_
 info_.vgprsPerSimd_

[ROCm/clr commit: 397f303d97]
2025-07-09 10:46:52 -04:00
Lin, Qun ced47b3588 SWDEV-508869 - Replace asicRevision with gfxip triple in paldevice (#601)
asicRevision is not unique in pal path now, use gfxip triple to match isa is more straight forward in pal path.

[ROCm/clr commit: b584fc8cd1]
2025-06-27 10:09:21 +08:00
Lin, Qun 3b44884a57 SWDEV-508869 - Fix Linux build error for HIP on PAL (#176)
[ROCm/clr commit: 9699cc3864]
2025-06-27 07:51:22 +08:00
Assiouras, Ioannis 71f19d7017 SWDEV-529449 - Bug fix when retrieving a memobj from the IPC mem handle
[ROCm/clr commit: f7482ef0a6]
2025-05-13 19:18:22 +01:00
Andryeyev, German b9669ea266 SWDEV-531678 - Remove split path from the dispatch (#283)
The split path for blit kernels are no longer necessary, since the new blit kernels
don't use the copy size as the global workload

[ROCm/clr commit: da198ac5b2]
2025-05-12 12:50:32 -04:00
Patel, Jaydeepkumar 5bd5f3aa6e SWDEV-521135 - Make common way to set/parse UUID bytes from PAL props. (#63)
[ROCm/clr commit: 6858b0fca1]
2025-05-12 17:00:30 +05:30
Six, Lancelot fe14cc349b SWDEV-517078: Fix gfx11 trap handler (#212)
Fix incorrect edits done when porting the 2nd level trap handler from
the hsa-runtime.

Change-Id: I7bc5160be47b8f669efe05c4d194bc3c47fc0661

[ROCm/clr commit: c35e9643ec]
2025-05-11 01:12:28 +01:00
Xie, AlexBin 142e347aac SWDEV-528860 - reserve some memory in visible frame buffer (#251)
[ROCm/clr commit: faac50c77a]
2025-05-09 20:08:23 -04:00
Assiouras, Ioannis 3d4ff304d7 SWDEV-521011 - Fix alignment in PalResource::CreateSvm
[ROCm/clr commit: 9d6a0d1a4d]
2025-05-01 02:22:49 +01:00
Andryeyev, German 13c7977d50 SWDEV-526836 - add PipelineStageBlt flag (#229)
CP sync requires PipelineStageBlt flag.


[ROCm/clr commit: 84a4f293f4]
2025-04-30 14:27:41 -04:00
Jiang, Julia 6ab34e0924 SWDEV-522634 - Fix device properties in hipInfo (#203)
[ROCm/clr commit: eb62fe9f62]
2025-04-29 11:29:47 -04:00
GunaShekar, Ajay c4567a9188 SWDEV-523028 - print PAL failure return values in logs (#81)
* print PAL failure return values in logs
* dump kernel info incase of PAL failure

[ROCm/clr commit: 99ef573399]
2025-04-29 11:23:43 +05:30
Critchley, Paul 4d3978e094 SWDEV-523611 - [Tools][OCL] OpenCL fails to capture with PalTrace (#198)
Finalize DevDriver initialization after device creation

[ROCm/clr commit: 7e9d5eab7c]
2025-04-28 08:02:34 -07:00
Li, Todd tiantuo 8706df3726 SWDEV-511055 - fix HIP PAL memory allocation workaround for APU (#40)
[ROCm/clr commit: 95cdc83eaf]
2025-04-24 15:07:16 -07:00
Critchley, Paul 4fd8a0164a SWDEV-527731 - [Ubertrace] OpenCL driver reports wrong Instrumentation API Version (#211)
[ROCm/clr commit: 4f2a4b12a9]
2025-04-24 14:06:17 -07:00
Xie, Jiabao(Jimbo) c7737558a4 SWDEV-441487 - add gfx1150/1 support to amd-staging clr (#182)
Co-authored-by: Jimbo Xie <jiabaxie@amd.com>

[ROCm/clr commit: 9a8c9e70b2]
2025-04-23 20:43:03 +05:30
Andryeyev, German a9df586812 SWDEV-459758 - Pass workgroup size explicitly (#185)
It's easier for compiler to move explicit kernel arguments into user SGPRs

[ROCm/clr commit: 3fd7650fe3]
2025-04-15 15:22:15 -04:00
Andryeyev, German db3c5f87ea SWDEV-526836 - Switch PAL backend to CmdReleaseThenAcquire() (#175)
[ROCm/clr commit: f6c804edc0]
2025-04-15 11:49:53 -04:00
Six, Lancelot b389f97d73 SWDEV-517078 - Update 2nd level trap handlers (#148)
* SWDEV-517078 - Maintain the trap handler ABI version in CLR

The trap handler ABI version is communicated to the debugger using
the r_version field in the r_debug structure.  This structure is
an external dependency, which makes it complicated to keep the trap
handler source (in CRL) and the ABI version number (external dependency)
in sync.

This patch proposes to patch the trap handler ABI version number in
_amdgpu_r_debug before communicating it to the debugger.

We can't directly include sc's executable.hpp file in CRL as it relies
on conflicting definition of ELF related types, so instead we need to
rely on a-priori knowledge on the r_debug structure.  Fortunately, this
structure is part of a stable ABI, so its layout is guaranteed to be
kept stable.

Update the 2nd level trap handler to follow updates from the
ROCr-runtime.  The trap handlers are stripped from parts dedicated to
architectures unsupported by CLR.

Bump the r_debug.r_version to track the ABI changes in the trap handler.

[ROCm/clr commit: 7b72c1b786]
2025-04-11 18:59:54 +01:00
Andryeyev, German 90e3d2619a SWDEV-525725 - Enable resource cache for SVM (#156)
- Make sure reserved_va_ updated before svmPtr overwrite

[ROCm/clr commit: 94cd9bc4f7]
2025-04-10 10:54:28 -04:00
Patel, Jaydeepkumar 2f3bc7f01c SWDEV-521011 - Allow max stack size as per ISA. (#73)
[ROCm/clr commit: 9e7248aa36]
2025-04-08 10:15:38 +05:30
Andryeyev, German 4c9cc6ba30 SWDEV-497841 - Add VmHeapArray support (#76)
Add VmHeapArray class to reduce the pressure on VA reservation, since
multiple memory pools can be active at the same time.

[ROCm/clr commit: e974f7fde1]
2025-04-03 21:04:18 +05:30
Patel, Jaydeepkumar b217d3a4e6 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29)
[ROCm/clr commit: b5c9cbc236]
2025-04-02 16:33:29 +05:30
GunaShekar, Ajay aaba454bfc SWDEV-523853 - Use RecordRenderOps instead of RecordRenderOp (#97)
[ROCm/clr commit: 686dd56a4e]
2025-03-26 09:28:40 +05:30
agunashe 4a5c6b8d82 SWDEV-513810 - APU: memory allocations threshold 0.75-->1
Needs further debugging but for now can test the change

Need to verify if this fixes all the below issues-
SWDEV-512754, SWDEV-511675, SWDEV-511055, SWDEV-504085, SWDEV-499503
Also verify original issues
SWDEV-471863, SWDEV-490991

Change-Id: Ic845f851de1b98e8ed9aa0f07afddec3858119e9


[ROCm/clr commit: f1b8ee7b7f]
2025-03-11 05:30:43 -04:00
Pengda Xie 021ca96766 SWDEV-497619 - Ensure suballocSize is integer multiple of 4096
Change-Id: Iefc452d73566f58cfb63391a68c836f30d77dd6c


[ROCm/clr commit: b02b1858c0]
2025-03-07 15:36:57 -05:00
Branislav Brzak c81185cf26 SWDEV-516564 - SWDEV-512817 - Remove mentions of gfx940 and gfx941
Change-Id: Ia069fcb9c6948c3fc9a00961593c9dcc59609375


[ROCm/clr commit: c2d1776ebd]
2025-03-05 04:26:07 -05:00
Julia Jiang 1495cc77eb SWDEV-513294 - fix regression on SVM sub-test failure in Conformance
Change-Id: Ic2449dd34a9cd2b623d5f8fbe89fd042566a56e3


[ROCm/clr commit: b7eaec76fc]
2025-02-20 15:40:23 -05:00
German Andryeyev f9d9b2c441 SWDEV-497841 - Add virtual memory heap
Add initial implementation of virtual memory heap with
dynamic virtual memory mapping support for memory pools.
DEBUG_HIP_MEM_POOL_VMHEAP controls the new method.

Change-Id: I8dc5be2e0f34ab472f1800f43bb6243639a5e500


[ROCm/clr commit: 296dce5570]
2025-02-20 10:55:49 -05:00
German Andryeyev 6f2a603277 SWDEV-497619 - Allocate extra space in CB
Compute doesn't support IB chaining, but RGP may collect
perf counters, which require more space in CB.
Increase CB size if RGP is enabled.

Change-Id: Iaa0a620ead8541a679b0dfe5e5711af5afdba545


[ROCm/clr commit: 63cf3057ba]
2025-02-20 10:40:09 -05:00
agunashe 52a1f5dbf7 SWDEV-507967 - Deprecate gfx9, gfx8, gfx7 on Windows
PAL_CLIENT_INTERFACE_MAJOR_VERSION from 872 --> 910

Change-Id: I03dfa2924ccdae4c2f13f09d5f34ee58298e1343


[ROCm/clr commit: ea804e16f8]
2025-02-17 02:59:41 -05:00
Aidan Belton-Schure 4b4a35b86b SWDEV-508279 - Improve HIP event profiling
There are 2 functional changes to this patch:
* Use GPU timing for internal markers for HIP.
* Measure CPU time closer to GPU timer, to reduce delta between GPU/CPU timestamp measurements.

There are some smaller non-functional updates:
* waifForFence -> waitForFence typo
* Remove unused drmProfiling

Change-Id: I4c5fa600a842ab60e454888779edcac8449a902a


[ROCm/clr commit: 179801a750]
2025-02-13 04:15:40 -05:00
kjayapra-amd 1f648c7d94 SWDEV-511672 - Special case the Remote USWC memory usage for HIP, if the alloc size is large.
Change-Id: I524c1402b249cedfd58b56f494caa2ac057e1623


[ROCm/clr commit: cf6aabb823]
2025-02-11 06:42:18 -05:00
taosang2 40df900647 SWDEV-501963 - Add missing codes for gfx950
Cherry-pick https://gerrit-git.amd.com/c/compute/ec/clr/+/1162997

Change-Id: I6b3c6bf55c61cffd43cd6f17b75998f751b75723


[ROCm/clr commit: 32daa8f384]
2025-01-31 14:34:49 -05:00
Aidan Belton-Schure dc2fa93f37 SWDEV-482851 - Do not release last suballocator chunk
Change-Id: Ib28dc9df68e454ee0c0c699c1ff17588fd55f802


[ROCm/clr commit: 451b0ce768]
2025-01-13 10:14:40 -05:00
Daniel Livingston 50387f6eb5 SWDEV-489003 - [Ubertrace] OCL/HIP profiles are missing event instrumentation
Adds UberTrace support for pre-dispatch markers and barrier begin/end markers.

Moves shared definitions out of palgpuopen.hpp into shared header
palcapturemgr.hpp.

Change-Id: I9f464c689e7ff12c54eca043fc1ad65e1836a64f


[ROCm/clr commit: 541c449ce2]
2025-01-10 11:28:52 -05:00
Jatin Jaikishan Chaudhary 8b1d0cff83 Revert "SWDEV-505971 - change setArgument arg from uint32_t to uint64_t"
This reverts commit 0830d95f6d.

Reason for revert: There needs to be memcpy size change

Change-Id: If4f51769731e54743ac705b19b4f81b2d5925d5a


[ROCm/clr commit: 446ed661a0]
2025-01-06 18:03:23 -05:00
Jatin Chaudhary 0830d95f6d SWDEV-505971 - change setArgument arg from uint32_t to uint64_t
We are passing this arg as an address, and memcpy complains about
overreading (8 bytes instead of 4).

Change-Id: Ica9207f6c5f6056a4bfc968280c76e779ded13ae


[ROCm/clr commit: a6f2a2c2af]
2025-01-06 08:16:59 -05:00
taosang2 da613fbbeb SWDEV-479958 - Support different address mode
Support different address modes in X, Y, Z directions

Change-Id: If1db5a8af33c92dd14b48968c3e8eceb97daea6c


[ROCm/clr commit: d82d6a78cf]
2024-12-23 16:39:54 -05:00
Sourabh Betigeri 7261404002 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8


[ROCm/clr commit: 03dbcd8ca7]
2024-12-12 19:29:24 -05:00