01a8efbb76
[TransferBench] Adding ability to specify source data pattern ( #394 )
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* [TransferBench] Adding ability to specify source data pattern
[ROCm/rccl commit: ff413be933
2021-06-15 08:41:57 -06:00
60c74f63fa
[TransferBench] Restore some previous fixes - memory leak, PCIe address ( #314 )
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[ROCm/rccl commit: 62e0447e9a
2021-02-01 09:48:09 -07:00
c570f09681
[TransferBench] Fixing bug with fine-grained memory allocation ( #311 )
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* Fixing bug with fine-grained memory
[ROCm/rccl commit: 41c35dad48
2020-12-15 17:37:31 -07:00
5155abb250
[TransferBench] Adding ability to perform CPU-executed copies, various upgrades ( #309 )
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* Adding CPU based execution, fixing typos, adding Fine-grained mem
* Exposing sampling factor when generating range of data sizes
* Refactoring how Links are launched, now once per thread
* Documentation updates
[ROCm/rccl commit: ae0c4092c7
2020-12-11 10:21:14 -07:00
9b48f92d72
[TransferBench] Support multiple of 4 byte sizes, changing default GPU timing mechanism ( #307 )
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* Changing default timing mechanism, adjusting CPU bandwidth calc, adding flag to use combined timing
* Adding support for smaller transfers (byte size must be multiple of 4 instead of 128)
[ROCm/rccl commit: b80ae551b1
2020-12-04 14:57:13 -07:00
2931959e6e
Adding output to CSV, removing OpenMP, decreasing default numBytes to 64MB, adding aggregate stats ( #290 )
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[ROCm/rccl commit: bfab1d3592
2020-10-27 09:00:33 -06:00
a062c80298
[TransferBench] Displaying PCIe Bus ID ( #288 )
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* Adding PCIe BusID per GPU in topology display
[ROCm/rccl commit: 61e1a71d14
2020-10-21 16:13:36 -06:00
0282595de5
TransferBench Typo. Pinned host memory uses C not P ( #286 )
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[ROCm/rccl commit: 769418c5c7
2020-10-21 12:05:38 -06:00
5ca117d7cd
New TransferBench features ( #273 )
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* Upgrading TransferBench to support pinned CPU memory, expanding functionality, cleaning up env vars
[ROCm/rccl commit: ee262819a7
2020-09-25 12:20:48 -06:00
3e4ddd065b
Upgrading various TransferBench features ( #257 )
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[ROCm/rccl commit: ec9af40fcd
2020-08-19 09:47:19 -06:00
1a9b00a7fd
Fixes to make TransferBench compile for hipclang ( #254 )
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[ROCm/rccl commit: c985478133
2020-08-13 12:25:28 -06:00
eebc6f2844
Adding option to re-use streams instead of re-creating per topology
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[ROCm/rccl commit: 339bf9ff19
2020-04-23 15:53:40 +00:00
bfbfe370c3
Fix HIP-Clang build with HSA headers
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HIP-Clang does not include these HSA headers, and they need to be explicitly added in RCCL.
[ROCm/rccl commit: a95090d981
2020-04-03 17:58:23 -04:00
e5419407c4
Updating copyright notices for 2020.
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[ROCm/rccl commit: 20fa04d9b6
2020-01-29 15:28:08 -08:00
5783917a75
Changing single sync mode to time all iterations instead of just last
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[ROCm/rccl commit: e5074ce94d
2019-12-20 17:08:39 -08:00
a461b6d139
Adding new sleep after sync capability for data fabric profiling ( #162 )
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Fixing missing header include for ROCM 3.0 changes
[ROCm/rccl commit: 2f4269d06d
2019-12-12 15:20:54 -07:00
22cbbb9004
Adding interactive mode for profiling purposes ( #150 )
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[ROCm/rccl commit: fd94f4fa25
2019-11-05 17:10:16 -07:00
f9ef1553aa
Single Sync Timing mode ( #144 )
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* Adding single sync timing mode to emulate timing reported by rccl-prim-test / rccl-tests
* Adding duration / overhead info
[ROCm/rccl commit: 2f9edd2432
2019-11-01 10:18:25 -06:00
a99accb2cb
Adding ability to switch between fine/coarse grain destination GPU memory
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Adding ability to switch between memset/memcpy
[ROCm/rccl commit: 648c1ee7cc
2019-10-29 12:00:32 -06:00
8645391260
Adding TransferBench tool ( #113 )
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* Adding standalone TransferBench tool
[ROCm/rccl commit: b8cf48fc16
2019-08-07 17:21:41 -06:00
gilbertlee-amd
Gilbert Lee
Aaron Enye Shi
Stanley Tsang