Commit grafiek

4372 Commits

Auteur SHA1 Bericht Datum
anusha GodavarthySurya 02e46ec231 SWDEV-284895 - Adding kind metadata and launch init/fini marked kernels
Change-Id: If2b21c4b98567632c426943e0b69aca8d6f1ec2a


[ROCm/clr commit: 102aa9d6d9]
2021-12-01 08:17:44 -08:00
Chauncey Hui 0ef7ea3ad9 SWDEV-2 - Change OpenCL version number from 3400 to 3401
[ROCm/clr commit: 3d56881a14]
2021-11-30 03:00:03 -05:00
Sarbojit Sarkar c8a6920b91 SWDEV-310181 - Fix for AtoH Memcpy tests failure
Change-Id: Ibf8c8c01257f0516088d50d5c9f82040ed8fa067


[ROCm/clr commit: 02dc6f9f9a]
2021-11-29 22:55:23 -05:00
kjayapra-amd f75cfb049a SWDEV-312822 - Fix the globalWorkSize to number of sizeof(var) instead of bytes.
Change-Id: Ic6b2bbb2e8d4cb6aa8d906d4b93cd06a176160d8


[ROCm/clr commit: d4ad981c0c]
2021-11-29 17:36:11 -05:00
German Andryeyev 861b9fb84c SWDEV-294669 - Avoid stall when the new signal was created
Stall in the host thread could occur earlier than the app expects.
Make sure rutnime can grow the signals to the queue size without
any stall. Also adding a new signal to the end of the pool could
break the dependency chain on signal reuse. The new logic will
insert the new signal after current to keep the chain intact.

Change-Id: I9c90b98515907db8b677528263c3e88cd9581a14


[ROCm/clr commit: 102c19adf3]
2021-11-29 10:08:06 -05:00
Chauncey Hui ed0b9b60ed SWDEV-2 - Change OpenCL version number from 3399 to 3400
[ROCm/clr commit: bfcb47ca72]
2021-11-29 03:00:05 -05:00
kjayapra-amd f74515778c SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns."
This reverts commit 7220267211.

Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39


[ROCm/clr commit: 2e9bc8f793]
2021-11-28 23:39:40 -05:00
Chauncey Hui af0788d2e9 SWDEV-2 - Change OpenCL version number from 3398 to 3399
[ROCm/clr commit: 2c23a1091f]
2021-11-27 03:00:08 -05:00
German Andryeyev b0b0c3049f SWDEV-313126 - Use data() method for the base array address
Reference for the first element can trigger an assert with
_GLIBCXX_ASSERTIONS build

Change-Id: I59c63c052831307edfe5dcc6384798a43e9596dd


[ROCm/clr commit: 6f2e7c3199]
2021-11-26 09:51:57 -05:00
Chauncey Hui 3577900318 SWDEV-2 - Change OpenCL version number from 3397 to 3398
[ROCm/clr commit: e4be77cbef]
2021-11-26 03:00:05 -05:00
Julia Jiang ea2741f631 SWDEV-308644 - merge roc blit kernels
Change-Id: I378e511959fe17c03fa45066022e9670a4d181f0


[ROCm/clr commit: f5c9ad5b1d]
2021-11-25 10:07:51 -05:00
Chauncey Hui 4d011fd9ae SWDEV-2 - Change OpenCL version number from 3396 to 3397
[ROCm/clr commit: 964f5bc502]
2021-11-25 03:00:04 -05:00
Satyanvesh Dittakavi 1caf1e4936 SWDEV-292714 - Add unique id for each allocation to support HIP_POINTER_ATTRIBUTE_BUFFER_ID
Change-Id: Ibb3fcb2d0bbbef03525fc884d5b3e9b5f6c11423


[ROCm/clr commit: c56317b2e0]
2021-11-24 06:10:50 -05:00
Chauncey Hui b3edecda2c SWDEV-2 - Change OpenCL version number from 3395 to 3396
[ROCm/clr commit: 0ab4ad1310]
2021-11-24 03:00:04 -05:00
Saleel Kudchadker dc7a87fad8 SWDEV-299893 - Fix PAL/lnx build
Change-Id: If4408a81d2dc8686c8e805a7697a7d9b2589c864


[ROCm/clr commit: 1e6cc5a2fa]
2021-11-23 08:09:33 -08:00
Chauncey Hui 3af9ff75f6 SWDEV-2 - Change OpenCL version number from 3394 to 3395
[ROCm/clr commit: f526e9ea89]
2021-11-23 03:00:03 -05:00
Sarbojit Sarkar 04745adf7a SWDEV-310181 - Fix for mGPU dtest failure
Change-Id: Id0898bd45e23f2d637bef25a3e69f26d9dc40785


[ROCm/clr commit: 2afeacc858]
2021-11-22 01:01:47 -05:00
Chauncey Hui b9d61c4cd8 SWDEV-2 - Change OpenCL version number from 3393 to 3394
[ROCm/clr commit: 7fdeb37239]
2021-11-20 03:00:06 -05:00
kjayapra-amd 7220267211 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns.
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d


[ROCm/clr commit: 8307886644]
2021-11-19 10:32:40 -05:00
Saleel Kudchadker 04a391004a SWDEV-299893 - Set preferred node affinity
Set affinity to the closest node of the current GPU. This reduces
the latency to fetch kernel args since device would query the CPU cache
of core which did the dispatch. This behavior is controlled with
AMD_CPU_AFFINITY env var(disabled by default)

Change-Id: I65afba62cb818ea25a311b88d1c0dd5c51330292


[ROCm/clr commit: b192beea52]
2021-11-19 04:42:42 -05:00
Chauncey Hui 8ff18d5e6f SWDEV-2 - Change OpenCL version number from 3392 to 3393
[ROCm/clr commit: 6cf5089f37]
2021-11-19 03:00:05 -05:00
anusha GodavarthySurya 2c1173ea32 SWDEV-240806 - hipGraph performance create new graph commands for every launch
Change-Id: Ifd4a373d6a76118ae0946238b29accfacbe32937


[ROCm/clr commit: ef1ec6ffde]
2021-11-19 00:09:47 -05:00
German Andryeyev c116411e00 SWDEV-294669 - Avoid queue drain
Use slot wait logic for direct dispatch

Change-Id: I431ba1418eb4aa066b9881934f4055b3d338ce3a


[ROCm/clr commit: 8e4101b4fd]
2021-11-18 13:06:12 -05:00
Chauncey Hui a3e56d08b7 SWDEV-2 - Change OpenCL version number from 3391 to 3392
[ROCm/clr commit: 874513375f]
2021-11-18 03:00:10 -05:00
pghafari e7df603b2a SWDEV-297142 - HIP-Vulkan - linux interop buffer
Change-Id: I0278e56bba632024c214beb9e1758587ccba0927


[ROCm/clr commit: e38a200bf7]
2021-11-17 06:06:58 -05:00
Chauncey Hui 0e39d6f41a SWDEV-2 - Change OpenCL version number from 3390 to 3391
[ROCm/clr commit: 13ef90af61]
2021-11-17 03:00:15 -05:00
German Andryeyev 95c01935b8 SWDEV-305016 - Correct timeout logic
Timeout logic should be applied always even if the wait is active.

Change-Id: I2e5db7ac8a0f9a0355ad7b40e4227d76fb002aa0


[ROCm/clr commit: 9877fc9dbf]
2021-11-16 23:04:34 -05:00
Julia Jiang e3f6db3d64 SWDEV-308644 - update blit kernel setup in rocm
Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c


[ROCm/clr commit: ef3d6f7b28]
2021-11-15 13:28:07 -05:00
Chauncey Hui a7edd1e407 SWDEV-2 - Change OpenCL version number from 3389 to 3390
[ROCm/clr commit: 02f36b565b]
2021-11-13 03:00:04 -05:00
kjayapra-amd 2fdfb47092 SWDEV-309657 - Align Virtual queue size to sizeof(uint64_t).
Change-Id: Ia55d7316693bd13938875ce53f7849d5eb658e8c


[ROCm/clr commit: 7e32d6d909]
2021-11-12 10:35:36 -05:00
Chauncey Hui c27731f98b SWDEV-2 - Change OpenCL version number from 3388 to 3389
[ROCm/clr commit: 777c91a539]
2021-11-12 03:00:06 -05:00
Julia Jiang db667776fe SWDEV-306204 - update disclaimer in vdi
Change-Id: I69aac8897c43b72a52bee0279d3dbdcf3f1fb484


[ROCm/clr commit: a38f5f8382]
2021-11-11 14:01:56 -05:00
Chauncey Hui eea0019645 SWDEV-2 - Change OpenCL version number from 3387 to 3388
[ROCm/clr commit: 85d34f9277]
2021-11-11 03:00:06 -05:00
German Andryeyev 0b03dde692 SWDEV-286150 - Add detailed thread trace support in RGP
- Create hash values for binaries
- Add the binaries into RGP trace
- Add corresponding hash value for every dispatch

Change-Id: I2c3ce004d69f37d0d46bc4744e12f24273517f5e


[ROCm/clr commit: 2a298f2ec3]
2021-11-10 14:46:02 -05:00
Chauncey Hui 63bbdb2ab5 SWDEV-2 - Change OpenCL version number from 3386 to 3387
[ROCm/clr commit: b2de4f625c]
2021-11-06 03:00:04 -04:00
German Andryeyev 92be4f5781 SWDEV-286150 - Fix a crash when LC is forced
Change-Id: I1127490502012cdbc0391e45b5d9310f04f9482b


[ROCm/clr commit: b0af08ac04]
2021-11-05 12:35:11 -04:00
Chauncey Hui 3e0539fc40 SWDEV-2 - Change OpenCL version number from 3385 to 3386
[ROCm/clr commit: b44dc91f4f]
2021-11-05 03:00:04 -04:00
German Andryeyev 7a9f92d95e SWDEV-305016 - Add a timeout wait into IsHwEventReady()
Just signal check will still submit the marker and then later
runtime will have a timeout, but the barrier packet is still
generated. Hence early timeout will allow to skip the marker.

Change-Id: Ieb7d89becbcff43a4f4c46715354ca65ab4a80b9


[ROCm/clr commit: bbb635bc32]
2021-11-02 11:37:23 -04:00
Chauncey Hui b1eda6f40e SWDEV-2 - Change OpenCL version number from 3384 to 3385
[ROCm/clr commit: 712b65765e]
2021-10-29 03:00:05 -04:00
German Andryeyev 7821cddb3e SWDEV-257789 - Initial change to skip kernel arg copy
The optimization is controlled with ROCR_SKIP_KERNEL_ARG_COPY.
This is initial check-in for experiments. Extra changes are
necessary for full support:
- handle graph capture with the original sysmem alloc
- avoid memobject references, otherwise there is a race condition with
reusage of the arg buffer
- Remove arg setup from hip

Change-Id: Ib0af710f93e79834711fa4049a7c66093711e68b


[ROCm/clr commit: 7e12cf6318]
2021-10-28 20:35:35 -04:00
Chauncey Hui 4f82f985c0 SWDEV-2 - Change OpenCL version number from 3383 to 3384
[ROCm/clr commit: 530283e12a]
2021-10-28 03:00:04 -04:00
German Andryeyev 2d2d33dd9c SWDEV-303567 - reset kernel arg buffer to chunk 0
Change-Id: I2974e31af9700705554b0f274ede6f8b9a9d6e7b


[ROCm/clr commit: 30bba18a06]
2021-10-27 22:15:55 -04:00
Alex Xie da48f060f4 SWDEV-305752 - OCL WIN Conformance select test fail
Change-Id: I73571c262a14d6b27d8cf91b6d1a13e1974ddc96


[ROCm/clr commit: 0e321f45c1]
2021-10-27 19:54:24 -04:00
German Andryeyev 22182e12bd SWDEV-286150 - Switch PAL to 678 interface
Change-Id: I3c130998902654e1dffc954ddf33530ea998ac34


[ROCm/clr commit: 4aea2ad172]
2021-10-27 17:25:02 -04:00
Alex Xie d84cde7888 SWDEV-308726 - OCL WIN - Conformance SVM Test failing
SVM mapping should not use direct mapping in Windows PAL

Change-Id: I005115bdce6ef99f471bb08fa8d042fa644587a6


[ROCm/clr commit: fa73e0cfcc]
2021-10-27 03:20:47 -04:00
Chauncey Hui aeb2e28f75 SWDEV-2 - Change OpenCL version number from 3382 to 3383
[ROCm/clr commit: 5ad666093a]
2021-10-27 03:00:04 -04:00
German Andryeyev d8201bc1ce SWDEV-303567 - Add chunks for the pool of kernel arguments
The kernel arg pool will be divided into 8 chunks to avoid long stalls,
when the pool will be reused.

Change-Id: I228e6ca1c09e428c1775f1e5b685220a9a5d71af


[ROCm/clr commit: f78b3a8919]
2021-10-26 16:31:37 -04:00
Sarbojit Sarkar 2e1ec62950 SWDEV-306773 - Pal fix for 2D/3D memset
Change-Id: Id705e9292e17621ea70e283d7494212809456e27


[ROCm/clr commit: c218022296]
2021-10-25 00:37:18 -04:00
Chauncey Hui 41c6814044 SWDEV-2 - Change OpenCL version number from 3381 to 3382
[ROCm/clr commit: 44c479b65f]
2021-10-23 03:00:05 -04:00
Jason Tang c9fa41e3c6 SWDEV-292525 - Fix -Werror=parentheses build failure
Change-Id: I2650413914914392df68a9fbf669af216a132640


[ROCm/clr commit: f61dc18681]
2021-10-22 09:43:15 -04:00