All conditional logic previously dependent on asic_family now dependent
on gfx version. As such, HSA_FORCE_ASIC_TYPE is now deprecated and
HSA_OVERRIDE_GFX_VERSION should be used instead.
device_info structs containing asic_family, eop_buffer_size, and
doorbell_size removed (alongside dev_lookup_table[]). eop_buffer_size
and doorbell_size now determined via macro, with eop_buffer_size and
full gfx version field being added to queue struct.
Certain funcs previously dependent on DID or GPU ID now dependent on
Node ID (due to use of get_gfxv_by_node_id()).
Fixes sleeper bug where ctl_stack_size and debug_memory_size were being
incorrectly programmed on gfx90a.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: Iaabdc5c73920ad83b4b379cd6086992357b8ff10
[ROCm/ROCR-Runtime commit: 8f883d0830]
Add defines for converting between full gfx version (in decimal) to
major/minor/stepping values, and major/minor/stepping values to full gfx
version (in hex). The first is to be used when grabbing the gfx version
from sysfs, the second when returning the gfx version in
get_gfxv_by_node_id() for comparisions in Thunk.
Add enum for defines of full gfx versions for various cards. These are
to be used in conditionals to replace CHIP_*/asic_family comparisons. On
NPI bringup, addition to this enum will not be required for
functionality unless explicitly needed for a conditional. Most ASICs in
this enum simply for completeness.
Add get_gfxv_by_node_id(): returns full gfx version in hex.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I9d1dba7fdd4a587a000eea2f4141a1d301bf4776
[ROCm/ROCR-Runtime commit: 8880610265]
Put CHIP_gfx90a next to CHIP_gfx908 to keep all the GFXv9
chips together.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I32b4b7f7746ae4bdaff7e178f13307c1bcfa93e1
[ROCm/ROCR-Runtime commit: 80e4cb6261]
This patch is to add yellow carp support on thunk.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: Icfecc3fd1f472c9924f934c6a5352448356d83df
[ROCm/ROCR-Runtime commit: a55551309c]
it is to optimize memory allocation latency, which
changes alignment from 2MB to 1GB.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I7818e9f13b17e2c0992e75b17f978dc03a018a57
[ROCm/ROCR-Runtime commit: 973b35bc06]
Query the KFD interface version once and store it in a global variable.
This makes it more efficient for KFD APIs to query the API version
later.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I267f3465f754e78fb21a7c42c5877cd68eaa9d05
[ROCm/ROCR-Runtime commit: 43ce63b68b]
This reverts commit a247255a6a.
SVM is not ready yet. This was merged by accident.
Change-Id: I372f7d293fd38429ec570bc0e0add7e612871594
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[ROCm/ROCR-Runtime commit: 4ebda913cd]
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.
For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.
However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.
This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa
[ROCm/ROCR-Runtime commit: 7c05c5240f]
This patch is to add Van Gogh support on thunk.
Change-Id: I75819329b865e4c38c097e83e3a0cb4e4f566fa2
Signed-off-by: Huang Rui <ray.huang@amd.com>
[ROCm/ROCR-Runtime commit: 9600760ff7]
1. Create P2P links
2. Determine FRAMEBUFFER_PUBLIC/PRIVATE only based
host-accessibility, not peer-accesssibility
Signed-off-by: Gang Ba <gaba@amd.com>
Change-Id: I15fccdc60386b453e2a47849a16df15157324b21
[ROCm/ROCR-Runtime commit: bedecc5957]
Whether use dgpu path will check the props which exposed from kernel.
We won't need hard code in the ASIC table.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Change-Id: I0c018a26b219914a41197ff36dbec7a75945d452
[ROCm/ROCR-Runtime commit: ad87f38dad]
KFD already implemented the fallback path for APU. Thunk will use flag
which exposed by kfd to configure is_dgpu instead of hardcode before.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Change-Id: I445f6cf668f9484dd06cd9ae1bb3cfe7428ec7eb
[ROCm/ROCR-Runtime commit: 12813691a2]
libpci was only used to find a marketing string for a device.
This patch looks for a pci.ids on disk and parses it to extract the
same string, using 'Device xxxx' as the fallback on file i/o error
or missing data from the text file. Tested by checking every vendor/
device pair against the values returned from libpci.
Change-Id: I21af3157472c1824d57fcee31393c6ee8ce07330
Signed-off-by: Jon Chesterfield <Jonathan.Chesterfield@amd.com>
[ROCm/ROCR-Runtime commit: 0a1718b753]
Check for errno == EBADF in kmtIoctl to detect misuse of the kfd_fd
in a forked child process.
Detect being in a forked child process pro-actively by implementing
a pthread_atfork callback.
Make sure all mutexes get reinitialized in the child process to avoid
deadlocks.
Check for being in a forked child process in CHECK_KFD_OPENED so that
all hsaKmt functions will return the appropriate status
HSAKMT_STATUS_KERNEL_IO_CHANNEL_NOT_OPENED.
Update InvalidKFDHandleTest to expect that error code.
Change-Id: I0238e5fba344dcaa454e97a35db2e2dcc8d1f607
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[ROCm/ROCR-Runtime commit: 87e10cd0b4]
This patch adds the support for gfx90c apu. So far we treat it as "dgpu" and
gfx900. Will update hsa gfxip table while the isa/llvm is implemented on gfx90c.
Change-Id: I6ef164bf3e751fe6dd6287cac212a500dce84b1a
Signed-off-by: Huang Rui <ray.huang@amd.com>
[ROCm/ROCR-Runtime commit: fdba74c2fb]
On NUMA system, allocate queue ctx save restore area on the closest NUMA
node to the GPU which the queue is going to run. This will improve
performance on NUMA system generally by reducing schedule latency and
fix the multi-node rccl-tests unstable performance issue.
If the closest NUMA node has no memory available, set flags NoNUMABind=1
to bypass mbind, to use default NUMA memory policy to allocate system
memory.
Change-Id: Ic62bfa5bb2efbf4f6ae79ff403e9610ddf18d45c
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 59c857476f]
Docker seccomp by default blocks mbind system call, so mbind return
failed on docker. thunk should not fail this otherwise application
cannot allocate system memory on docker.
Use pr_warn_once and pr_err_once to avoid duplicate same error messages
Change-Id: I61a7c0e4abaa3dcfe7abf2ea48db90f669f9638a
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 4da09813a3]
The gfx version item is yet to be added.
Change-Id: Ia6c487447e5a5df80c0c12fe150939175068024b
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
[ROCm/ROCR-Runtime commit: 3ecd83e52d]
Force all the GPUs to a certain type, use the below command:
HSA_FORCE_ASIC_TYPE="10.1.0 1 gfx1010 14"
meaning major.minor.step dgpu asic_name asic_id
This will faciliate the cooperation across the teams for bringing up
ASICs which reuse existing device IDs.
Change-Id: I40fe4c9b46d3ccb3e38ea52250e80e82fb50fb0f
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
[ROCm/ROCR-Runtime commit: d6539ddc24]
The queue IDs passed over to the kernel via kfd_ioctl_dbg_trap_args->ptr
should be a list of uint32_t's. Need to convert from the passed in
64 bit HSA_QUEUEID to 32 bit uint32_t's.
Change-Id: I8718566d9f9ffc90ce0b2ecc129b10c49d73186a
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
[ROCm/ROCR-Runtime commit: 608bc7c3a0]
While this may not be supported in the runtime, the kernel/firmware
support it
Change-Id: I7fe4536a6b3055f39e25f453060e899938645d91
Signed-off-by: Kent Russell <kent.russell@amd.com>
[ROCm/ROCR-Runtime commit: 1304a92e17]
GPU Resource management can disable some of the GPU nodes.
The Kernel driver could be not aware of this.
Get from Kernel driver information of all the nodes and then filter it.
Change-Id: I4eeb126a5efce2192c35f5d2b72be1811e9ded32
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
[ROCm/ROCR-Runtime commit: 3144a84b9a]
This reverts commit 84bb9072c0.
This fixes ambiguity when looking up GPU addresses with
hsaKmtQueryPointerInfo.
hsa_amd_agents_allow_access uses hsaKmtQueryPointerInfo, and
depends on finding the correct object from a GPU address. Finding
the wrong userptr object based on its CPU address leads to
incorrect GPU mappings and results in VM faults.
Change-Id: I7c5f571ee6e1f9d32687aa3eab6d96944ad032be
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[ROCm/ROCR-Runtime commit: a9bd6e6f8b]
Currently, all HSA nodes are exposed to user. So the existing
implementation assumes a one to one mapping between user
NodeId and sysfs nodeId.
GPU Resource Management will provide control over the exposed
HSA nodes. This means not all HSA nodes will be exposed to the user.
Decouple it.
The mapping from user NodeId to sysfs NodeId will be local
to topology.c and topology helper functions. For others NodeId
should be sequential from 0 to Number of Nodes exposed to user.
v1: initial implementation
v2: map node id within the topology_* functions
v3: remove two static globals
v4: add bounds check got node id
Change-Id: Id12147ece41d682430f398944bbb339ca906eb1b
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
[ROCm/ROCR-Runtime commit: 3437a356c7]
If the CPU addr of a userptr is accessible by the GPU, try to use it
instead of allocating a different GPU address. If something else is
already registered with an overlapping address range, we still need to
allocate a GPU address, because KFD does not support overlapping GPUVM
mappings.
Change-Id: I452963ee45a454f735755a0b43122b9aee5d55be
Signed-off-by: Felix Kuehling <felix.kuehling@gmail.com>
[ROCm/ROCR-Runtime commit: ab181c46c0]
Because gfx700 has local memory but other APUs don't, we should reflect
that in the code. Meanwhile, fix a bug that on gfx902 svm aperture is not
added when calling hsaKmtGetNodeMemoryProperties().
Change-Id: Id840f2db0b14fda9ee713b219a9474c15f8a9771
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
[ROCm/ROCR-Runtime commit: 110e754f64]
The information can be obtained directly from node id. Also improve the
whole logic for future compatibility.
Change-Id: I130733be4e7930d5953d5e81409905e60c2ec35e
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
[ROCm/ROCR-Runtime commit: 4bb90d048c]
On discrete GPUs place the EOP queue in VRAM. The reader/writer of this
queue is the CP and the size is small. Dispatch latency improves
through lower read latency in AQL completion phase.
Change-Id: Id8351dcddbd21fd7c7d699803c96434c9132db71
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
[ROCm/ROCR-Runtime commit: e2c353dc0d]
Previously kfd device is used to map memory for CPU access.
However this is not compatible with how TTM handles CPU mapping
on eviction - memory won't be unmapped and remapped on restore.
This fixes the issue by mmapping memory using DRM render device.
This patch requires a coordinated kernel driver change to work.
To make it compatible with old kernel driver, some temporary codes
are included. Once the coordinated kernel driver is checked in,
the temporary codes can be removed.
Change-Id: Ie7b304c4a82b7e8d5ab703acb81d66430af4f0bc
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: 68a2d286ca]
Graham Sider
Aaron Liu
chen gong
Alex Sierra
Chengming Gui
Mike Li
Felix Kuehling
Kent Russell
Harish Kasiviswanathan
Huang Rui
Gang Ba
Yong Zhao
Jon Chesterfield
Sean Keely
Philip Yang
shaoyunl
Philip Cox
Alex Voicu
Felix Kuehling
Jay Cornwall
Oak Zeng