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1dfe4959e5fd3ea978358abde92eeae6df53cbc6
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214 Commits

Author SHA1 Message Date
Qingchuan Shi 1dfe4959e5 remove finalizer usage from image ext 
Change-Id: I282f02cedce790bf42f07c588fd50e346b9ba665


[ROCm/ROCR-Runtime commit: 77e5b30c41]
 2017-05-29 20:44:52 -04:00
Sean Keely 754935ee65 Unmap GPUs when allow_access removes them from system pools. 
Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77


[ROCm/ROCR-Runtime commit: e38ff18990]
 2017-05-17 20:58:05 -04:00
Chris Freehill 9f1065771a Refactored performance test code 
Commented and flattened binary search sample.

Change-Id: Ib783292207c956d16003195924a3bcfbbde5039f


[ROCm/ROCR-Runtime commit: 8161ebb915]
 2017-05-11 14:45:45 -04:00
Konstantin Zhuravlyov 768644ba7a Purge warning in amd_hsa_code.cpp 
Change-Id: Iaa5d7af183af5e8c069365a1f0410365b46d53d5


[ROCm/ROCR-Runtime commit: a777413400]
 2017-05-08 19:39:49 -04:00
James Edwards b39fea499a Change rpm preinstall script to post install 
Change-Id: Iccc04902699bf0ba8b5269e1129b72cf69ef7f00


[ROCm/ROCR-Runtime commit: 001d43ce56]
 2017-05-07 14:02:54 -05:00
hthangir ef38e563ba On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset. 
Also fix permission in couple files.

Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a


[ROCm/ROCR-Runtime commit: 8aa19388a9]
 2017-04-18 22:37:56 -05:00
Christophe Paquot 65f6986835 Separate gfx700 and AI architectures 
Registers are different and it's cleaner to do as such

Change-Id: I36eee4c9c74deb43ca4666baa87894765a5f27b8


[ROCm/ROCR-Runtime commit: 617b6fa987]
 2017-04-07 00:14:22 -04:00
Jay Cornwall 2c71b68fdb Fix gfx9 trap handler to retrieve correct return address 
The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.

Clean up later when LLVM assembly build is introduced to the runtime.

Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178


[ROCm/ROCR-Runtime commit: f0a1c7c4c6]
 2017-04-05 17:33:49 -05:00
Sean Keely 9734bc078a Remove comments, no functional change. 
Change-Id: I923c037803a847352c2c50d9d47460cb0f01f22c


[ROCm/ROCR-Runtime commit: 8a5ff78be6]
 2017-03-28 18:22:49 -05:00
Sean Keely 941c065513 Support async. queue errors and dynamic scratch without KFD events. 
Change-Id: I4e9e7a37aa7b9c96b28ce79f562760283e02b1e0


[ROCm/ROCR-Runtime commit: 7dfeee5074]
 2017-03-28 19:18:18 -04:00
Sean Keely 5288e46340 Refactor signal_wait timing code and respect small timeouts. 
Optimized for Gromacs and SHOC.

Change-Id: Ib674710268b41003259711a0e42d3e770a82018d


[ROCm/ROCR-Runtime commit: c4544906b9]
 2017-03-23 23:55:48 -05:00
hthangir 4d121c2b97 We should be using the "used" gcc attribute. 
Change-Id: I1589273740ae66e8d7d8186a88e2c411a2e0425c
See: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#Common-Variable-Attributes


[ROCm/ROCR-Runtime commit: ba3f1cb476]
 2017-03-20 11:57:39 -04:00
hthangir d4a8e87a35 Fix the comment to specify the right type of allocation required. 
Change-Id: I8bda8d64010d466d6ca5e779d2042cca3f494ecf


[ROCm/ROCR-Runtime commit: 6c750f479d]
 2017-03-20 11:56:54 -04:00
hthangir d775242246 Disable SDMA only on gfx900 until it is validated. 
Change-Id: Ib960be3ca6d3fc4b664ba047243964b8c7a33f24


[ROCm/ROCR-Runtime commit: 7c6cde1871]
 2017-03-20 11:55:22 -04:00
Konstantin Zhuravlyov d0a8e27a35 [Loader] Fix memory allocations for code objects that 
are larger than swap space available

Change-Id: I321487f96fe0a18998301a9058430c19427e5a94


[ROCm/ROCR-Runtime commit: a08d760c70]
 2017-03-11 00:57:25 -05:00
Sean Keely b7256bae4e Support async error code 256, invalid vendor specific packet. 
Change-Id: I491f34def4c3d54403864fa42670f7847a6141cc


[ROCm/ROCR-Runtime commit: 5f50e97d18]
 2017-03-10 16:20:27 -05:00
Sean Keely 3ca460d72f Relax signal assertion. 
Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list.  This list is used
for optimized signal type selection.

Change-Id: I5879f8f822d01af504ab913482b2532feb00be98


[ROCm/ROCR-Runtime commit: 2824786b3b]
 2017-03-10 16:05:34 -05:00
Christophe Paquot d759209584 Add inc/ to some include 
Change-Id: Id027b015c8785a132835a422d97a23b0bbce208a


[ROCm/ROCR-Runtime commit: 05d587ef79]
 2017-03-09 19:45:01 -08:00
Sean Keely c02e8c67df Adjust signal sleep to reflect null kernel latency. Performance tested on Gromacs. 
Change-Id: I3851148ee8544b15d840f2c26ca73a83f8d0df2e


[ROCm/ROCR-Runtime commit: 426d41e27c]
 2017-03-09 15:20:53 -05:00
Christophe Paquot a96dc6e41b Update addrlib for gfx900. 
Change-Id: I2b7b6093406c5498e9a551327701ad8973f1cf3a


[ROCm/ROCR-Runtime commit: 29894df0b5]
 2017-03-07 14:41:16 -08:00
Ramesh Errabolu a9a54e2cc3 Extend Rocr Samples to allow collection of Perf Cntrs 
Change-Id: I9c7e75128fca28b23ec54efab00bf5d32c95a877


[ROCm/ROCR-Runtime commit: 315ae6439b]
 2017-02-28 20:29:24 -06:00
James Edwards ccbb47d79d Update readme regarding CMAKE_PREFIX_PATH. 
Change-Id: I322789f38b1984b2527554c10cb0f3be886d3e91


[ROCm/ROCR-Runtime commit: 470750cc3c]
 2017-02-20 14:33:53 -06:00
James Edwards 1bb65fb587 Modify packaging cmake files to use BUILD_VERSION* instead of RELEASE_VERSION*. 
Change-Id: I6f1b83c9faf0d40c1ac27d8998f4651341971b1b


[ROCm/ROCR-Runtime commit: 57ac399652]
 2017-02-16 16:40:20 -06:00
Ramesh Errabolu 513004fb28 Enable code for Perf Cntrs for gfx900 - AI family device 
Change-Id: I4659da1a8db17392016fc90c8ea19b5805b5d3aa


[ROCm/ROCR-Runtime commit: 42e751519b]
 2017-02-15 21:50:23 -06:00
James Edwards 212d7c3f8f Fixes to HSA CMakeList.txt files 
Change-Id: Idd176d24dfd22bd9a6a8860ab035fd5d1aca756d


[ROCm/ROCR-Runtime commit: 900f272622]
 2017-02-15 08:26:30 -06:00
James Edwards fca0ec886c Fix TeamCity builds using utils.cmake. 
Change-Id: Id15a911dad06643d9457cc4d8c907fc5796772ee


[ROCm/ROCR-Runtime commit: b7e06b471c]
 2017-02-14 15:36:21 -06:00
James Edwards f851f5adf6 Modify hsa CMakeList.txt file to use PREFIX_PATH and git describe versioning. 
Change-Id: I08668df07725369ecf8a2f35e74dd7d64c8ca94b


[ROCm/ROCR-Runtime commit: 73e942cd8a]
 2017-02-14 08:39:16 -05:00
Konstantin Zhuravlyov 2a071e1456 Bring loader in sync with stg/sc 
Change-Id: Iccce07b8fa03d37c4267a2a9bd343e6614dc43e7


[ROCm/ROCR-Runtime commit: 9887c26113]
 2017-02-10 11:21:15 -05:00
Jay Cornwall 16d8e2caa9 Implement code cache invalidation for Gfx9 
When a new enough microcode build is running use a vendor AQL packet
to submit the PM4 IB.

Change-Id: Icd3e2b322c418477420ba4a29f4455ce340ef0d2


[ROCm/ROCR-Runtime commit: 4d62b9482a]
 2017-02-09 14:15:21 -05:00
Ramesh Errabolu 34327e7167 Support Gfx9 and Pre-Gfx9 Thread Trace Drivers 
Change-Id: Ic3fea4006d76d1e3f58dde6f64c343a1261abe39


[ROCm/ROCR-Runtime commit: e91970a39b]
 2017-02-07 15:39:59 -06:00
Sean Keely de0fa51022 Fix Api table copy operation and tools version checking. 
Change-Id: Ia76d16f3ea6d0abb931813f90bc3bc2119da5999


[ROCm/ROCR-Runtime commit: 505d722b7d]
 2017-02-07 14:26:20 -05:00
Sean Keely d984194fa5 Use fixed size type for queue type arguments. 
Change-Id: I81b605c9cc9b18bcef043a4f0292212241ce5987


[ROCm/ROCR-Runtime commit: bc43f97964]
 2017-02-07 01:22:30 -05:00
Ramesh Errabolu 835866b042 Refactor Thread Trace Service as an independent library 
Change-Id: Ia7579bc16626f3e21c8df50f8a35cb4b82f6bda9


[ROCm/ROCR-Runtime commit: 74e3a49b20]
 2017-02-06 17:04:07 -05:00
Jay Cornwall dce2a864ba Fix Gfx9 write pointer setup 
Should point directly to amd_queue_t.write_dispatch_id. Only noticeable
with HWS enabled which is not yet stable.

Change-Id: I169906d45225379a3ca2729ff04d298fdbb9a9fb


[ROCm/ROCR-Runtime commit: 28f51d5808]
 2017-02-06 14:06:12 -05:00
Ramesh Errabolu 4a70f68afb Refactor Device Id to Asic Type Mapping Service 
Change-Id: I8969b41f7c4de9fdeee5131e2049053a486f64fb


[ROCm/ROCR-Runtime commit: 7755bd5487]
 2017-02-03 14:22:32 -05:00
Jay Cornwall 7b45ebfe7f Add support for ARM 
- Build system fixes
- No user-mode high-precision timer by default, use clock_gettime
- Use C11 aligned_alloc pending C++17 std::aligned_alloc

Change-Id: I268365bdfd11d1e817a89584b9e086ee5b86e1dc


[ROCm/ROCR-Runtime commit: 9e575ea96a]
 2017-01-31 16:43:49 -08:00
Jay Cornwall 7f38f6e297 Add support for gfx900 
- Route AQL doorbell directly to HW doorbell
- Reuse precompiled Gfx8 shaders on Gfx9 (ISA is compatible)
- Add a warning for unimplemented code cache invalidation

Change-Id: I92096584a1404e35779c96ae6bdc3e0e7fd04721


[ROCm/ROCR-Runtime commit: 7e0a5f9c00]
 2017-01-30 16:36:28 -06:00
Sean Keely 2755a4e0a7 Remove old names from API table interfaces. 
Change-Id: I41ca38b596e1dac85e871f583e3ffe7078b790e7


[ROCm/ROCR-Runtime commit: 796d31d94d]
 2017-01-27 17:45:26 -06:00
Christophe Paquot 2217e709da Adding the new APIs to the .def files and fixed a couple of things 
Change-Id: I247a60b8cdbd4acfed72fb6d78ac7faf69d8a556


[ROCm/ROCR-Runtime commit: 9ae1e15750]
 2017-01-27 16:51:50 -05:00
Jay Cornwall 22ffe11f5c Implement SDMA path for Gfx9 
Gfx9 requires monotonic write pointer and doorbell.
Cound fields are 1-based compared with 0-based pre-Gfx9.

- Restructure implementation to use monotonic ring indices
- Remove redundant submission size checks (handled by AcquireWriteAddress)
- Unify copy/fill per-command limit (documentation is unclear)

Change-Id: I57c1675221d2e63aa319fee700d9951671e1bd65


[ROCm/ROCR-Runtime commit: 1cd46afe6d]
 2017-01-26 13:11:21 -05:00
Christophe Paquot 4bb9fb4469 Add new 1.1 image APIs 
Note: Implementation same as 1.0 APIs for now.
      The followup change will have the complete implementation.

Change-Id: Ife633f74ff27eee0bb9b0c46952cf5233b0114e8


[ROCm/ROCR-Runtime commit: a324f21a46]
 2017-01-20 19:37:03 -05:00
Ramesh Errabolu 0bb7f56486 Add Gfx9 asic header files 
Change-Id: I04fe402ab44170dba582099670a8222c5c366e50


[ROCm/ROCR-Runtime commit: ff1d739660]
 2017-01-19 19:23:14 -06:00
Ramesh Errabolu 99ec6c549b Add agent properties for Tools 
Change-Id: I7bc49d35dc559f9c9058aae591b88c5ecc4b3ce5


[ROCm/ROCR-Runtime commit: 8ab28d1a51]
 2017-01-16 13:50:18 -06:00
Ramesh Errabolu 03668e6e06 Removing Old Commandwriter used by Profiler and Debugger 
Change-Id: I77d2172eef1724d1d4aed6d8e7a9df6cdbeb0648


[ROCm/ROCR-Runtime commit: f0263d8198]
 2017-01-13 11:51:21 -05:00
Christophe Paquot 321fdd26bf Add image 1.1 API changes to current code base 
Initial work to import the latest (1.1) hsa_ext_image extension.

Change-Id: I51d70ef26f97250c884b3def2088be0d7eb04eb3


[ROCm/ROCR-Runtime commit: 31d379c821]
 2017-01-12 14:49:54 -08:00
Kent Russell 56096ff555 Revert " Add image 1.1 API changes to current code base" 
Currently HSA HW Profiler is failing to build due to this patch

This reverts commit 91866d4bbb.

Change-Id: Iabb2b958f33ba614a24b61bb370905b3b7362708


[ROCm/ROCR-Runtime commit: 5162a76616]
 2017-01-12 06:43:54 -05:00
Christophe Paquot 91866d4bbb Add image 1.1 API changes to current code base 
Initial work to import the latest (1.1) hsa_ext_image extension.

Change-Id: I4d55adb09ba4d4dbd43d47a4bc54077d4bc531d2


[ROCm/ROCR-Runtime commit: e0ce8855dd]
 2017-01-11 17:31:37 -05:00
Sean Keely b75a8d9ed0 Allow reducing max occupancy (max scratch waves) when applications request large amounts of scratch. 
Also emit error messages to stderr if no async queue error callback was registered and queue fault messages are enabled (on by default).
Queue fault messages are controlled with env key HSA_ENABLE_QUEUE_FAULT_MESSAGE.

Change-Id: I496487b8d048b83aa95b9784e92928211f167b17


[ROCm/ROCR-Runtime commit: 0e17cc2887]
 2016-12-20 16:52:59 -06:00
James Edwards e0576546f9 Readme and comment updates to ROCm 1.4 
Change-Id: I2864a9c475b9ceb2fa08bfc35999c7e0e043b26d


[ROCm/ROCR-Runtime commit: 433a3bcde8]
 2016-12-16 11:43:36 -06:00
Chris Freehill 1df3375ec4 HSA Enabled IPC support 
Uncommented HSA IPC code.
Changed hsa_amd_ipc_memory_t to be 8 uint32_t's instead of 9 to
match spec

Change-Id: Id1523125e9b876a23c3743df1be29c98b47f6725


[ROCm/ROCR-Runtime commit: 160f8c5880]
 2016-12-15 19:16:29 -05:00