Commit Graph

325 Commits

Author SHA1 Message Date
Saleel Kudchadker c02d3fd7d8 SWDEV-301667 - Fix maxNode size for get_mempolicy
Change-Id: Ifd84c94394b86580cf39178ad0e7f85580b24edb
2022-02-19 12:48:22 -05:00
German Andryeyev 95d55fdfa8 SWDEV-323702 - Use active queue for transfer
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock

Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
2022-02-18 09:10:53 -05:00
German Andryeyev fbf531398a SWDEV-323364 - Fix a typo
Change-Id: I2031296ab9451342d5930b8b2d3d2e6277946647
2022-02-17 20:50:29 -05:00
Saleel Kudchadker 041ddc0c1c SWDEV-322605 - Fix infinite loop condition
If GlobalMemCacheLine reported is 0, runtime may run into an
infinite loop as the KernelSegmentAlignment is chosen as size of the
cache line.

Change-Id: Ide547940cc0407f16fab10ee210b4fd3ae4eaafc
2022-02-16 13:16:18 -05:00
German Andryeyev 3fd4a67670 SWDEV-316824 - Fix P2P compute copy path
Use device memory object for the GPU VA address look-up.

Change-Id: I76bf58b29205f7b3ba1bf68e9fcca69421267203
2022-02-15 13:20:13 -05:00
German Andryeyev 525a1bbf1a SWDEV-286150 - Remove GSL backend
Change-Id: Iba9a997ee7d5ff6ac00d5888ff189a4514958fe9
2022-02-09 17:16:39 -05:00
German Andryeyev be6a06384e SWDEV-307184 - Add support for the new metadata
Metadata in Codeobject version 5 is the extension of CO3 and CO4.
Add the detection of the new fields and program them in
the setup of the kernel arguments.

Change-Id: I27e58df77320ad00f4f16d35912668db803826af
2022-02-07 14:05:58 -05:00
Satyanvesh Dittakavi 824704c87b SWDEV-317716 - Add uuid in device info structure
Change-Id: Ie7f48d0faf7d722bd9bb8bd0f8962a7832dbe4f6
2022-02-03 12:17:28 -05:00
Saleel Kudchadker 33aca5a4a6 SWDEV-301947 - Use new enum for CU count
Use HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT to get compute
units. This is needed to work around assymentric CU harvesting bug on
gfx90a. Add a new device property to get the max available CUs on the
device.

Change-Id: I878f38f14f16c1af01fc0a77157aea1e816a63b8
2022-01-31 12:57:50 -05:00
Satyanvesh Dittakavi e20dd61932 SWDEV-306939 - Fix vdi errors/warnings by CppCheck
Change-Id: I56d910f8363787f1050d5d7e8064ed553c5827fd
2022-01-12 00:22:16 -05:00
Saleel Kudchadker 1fbd75b825 SWDEV-313306 - Fix Co-operative groups dtests
Add a state indicator to retain ExternalSignals when needed.
Co-operative group launch uses external signals to indicate a dependency
to the next command.

Change-Id: I6d0daa006e2377c3bbf4aeca0fd5b63c7ac8fbbb
2021-12-17 12:41:37 -08:00
Saleel Kudchadker 3239222516 SWDEV-313306 - Clear external signals
Crash was due to the fact that external signal structure was stale even
after destroyign the command. That is because we skipped wait due to a
missing check.
Detect external signals and dispatch a barrier in ReleaseGpuMemoryFence.
Also clear external_signals_ at ProfilingBegin.

Change-Id: I991387edcfe928b511bf5e780988ee131321ed5a
2021-12-13 23:03:33 -08:00
Sarbojit Sarkar aedbad0109 SWDEV-314254 - Fix for hipMemcpy3D test crash
Change-Id: Iac70bfe0d351cfb5b56fefc9a6487d3f26f2b4ef
2021-12-09 11:46:52 -05:00
German Andryeyev 008133cf41 SWDEV-305016 - Improve MGPU scaling in Tensorflow
Add a threshold for ROCR/SDMA P2P transfers. ROCR copy path
requires extra barriers in compute for synchronization. That costs
extra performance with tiny transfers.
Reduce active wait time to 10us. Tensorflow uses extra thread
per GPU with constant hipEventQuery() calls. Longer active waits
in ROCr affect CPU performance.

Change-Id: I9020358438615fa2d4617f862f00a562f0a588e7
2021-12-08 11:59:37 -05:00
Julia Jiang 376ea1e293 SWDEV-308644 - reorganize extra blit kernel in PAL stack
Change-Id: I9d853e8d417ef75b522184d83646ec4b9fa8669b
2021-12-07 14:55:20 -05:00
Satyanvesh Dittakavi 9dabdcdc3e SWDEV-309286 - save the max system mem size in device info
Change-Id: I9955625aca6ceda059aef6354d909de636b610ba
2021-12-02 10:59:07 -05:00
Saleel Kudchadker 3f82b99f5d SWDEV-308843 - Increase MaxPinnedXferSize to 128
This allows experimenting with env var GPU_PINNED_XFER_SIZE which is
still at a default of 32MB

Change-Id: I85ade700ed58d498eba29d1737601dc74d4c26a4
2021-12-01 20:37:56 -05:00
Sarbojit Sarkar 02dc6f9f9a SWDEV-310181 - Fix for AtoH Memcpy tests failure
Change-Id: Ibf8c8c01257f0516088d50d5c9f82040ed8fa067
2021-11-29 22:55:23 -05:00
kjayapra-amd d4ad981c0c SWDEV-312822 - Fix the globalWorkSize to number of sizeof(var) instead of bytes.
Change-Id: Ic6b2bbb2e8d4cb6aa8d906d4b93cd06a176160d8
2021-11-29 17:36:11 -05:00
German Andryeyev 102c19adf3 SWDEV-294669 - Avoid stall when the new signal was created
Stall in the host thread could occur earlier than the app expects.
Make sure rutnime can grow the signals to the queue size without
any stall. Also adding a new signal to the end of the pool could
break the dependency chain on signal reuse. The new logic will
insert the new signal after current to keep the chain intact.

Change-Id: I9c90b98515907db8b677528263c3e88cd9581a14
2021-11-29 10:08:06 -05:00
kjayapra-amd 2e9bc8f793 SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns."
This reverts commit 8307886644.

Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39
2021-11-28 23:39:40 -05:00
German Andryeyev 6f2e7c3199 SWDEV-313126 - Use data() method for the base array address
Reference for the first element can trigger an assert with
_GLIBCXX_ASSERTIONS build

Change-Id: I59c63c052831307edfe5dcc6384798a43e9596dd
2021-11-26 09:51:57 -05:00
Julia Jiang f5c9ad5b1d SWDEV-308644 - merge roc blit kernels
Change-Id: I378e511959fe17c03fa45066022e9670a4d181f0
2021-11-25 10:07:51 -05:00
kjayapra-amd 8307886644 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns.
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d
2021-11-19 10:32:40 -05:00
Saleel Kudchadker b192beea52 SWDEV-299893 - Set preferred node affinity
Set affinity to the closest node of the current GPU. This reduces
the latency to fetch kernel args since device would query the CPU cache
of core which did the dispatch. This behavior is controlled with
AMD_CPU_AFFINITY env var(disabled by default)

Change-Id: I65afba62cb818ea25a311b88d1c0dd5c51330292
2021-11-19 04:42:42 -05:00
German Andryeyev 8e4101b4fd SWDEV-294669 - Avoid queue drain
Use slot wait logic for direct dispatch

Change-Id: I431ba1418eb4aa066b9881934f4055b3d338ce3a
2021-11-18 13:06:12 -05:00
pghafari e38a200bf7 SWDEV-297142 - HIP-Vulkan - linux interop buffer
Change-Id: I0278e56bba632024c214beb9e1758587ccba0927
2021-11-17 06:06:58 -05:00
German Andryeyev 9877fc9dbf SWDEV-305016 - Correct timeout logic
Timeout logic should be applied always even if the wait is active.

Change-Id: I2e5db7ac8a0f9a0355ad7b40e4227d76fb002aa0
2021-11-16 23:04:34 -05:00
Julia Jiang ef3d6f7b28 SWDEV-308644 - update blit kernel setup in rocm
Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c
2021-11-15 13:28:07 -05:00
kjayapra-amd 7e32d6d909 SWDEV-309657 - Align Virtual queue size to sizeof(uint64_t).
Change-Id: Ia55d7316693bd13938875ce53f7849d5eb658e8c
2021-11-12 10:35:36 -05:00
German Andryeyev bbb635bc32 SWDEV-305016 - Add a timeout wait into IsHwEventReady()
Just signal check will still submit the marker and then later
runtime will have a timeout, but the barrier packet is still
generated. Hence early timeout will allow to skip the marker.

Change-Id: Ieb7d89becbcff43a4f4c46715354ca65ab4a80b9
2021-11-02 11:37:23 -04:00
German Andryeyev 7e12cf6318 SWDEV-257789 - Initial change to skip kernel arg copy
The optimization is controlled with ROCR_SKIP_KERNEL_ARG_COPY.
This is initial check-in for experiments. Extra changes are
necessary for full support:
- handle graph capture with the original sysmem alloc
- avoid memobject references, otherwise there is a race condition with
reusage of the arg buffer
- Remove arg setup from hip

Change-Id: Ib0af710f93e79834711fa4049a7c66093711e68b
2021-10-28 20:35:35 -04:00
German Andryeyev 30bba18a06 SWDEV-303567 - reset kernel arg buffer to chunk 0
Change-Id: I2974e31af9700705554b0f274ede6f8b9a9d6e7b
2021-10-27 22:15:55 -04:00
German Andryeyev f78b3a8919 SWDEV-303567 - Add chunks for the pool of kernel arguments
The kernel arg pool will be divided into 8 chunks to avoid long stalls,
when the pool will be reused.

Change-Id: I228e6ca1c09e428c1775f1e5b685220a9a5d71af
2021-10-26 16:31:37 -04:00
Bing Ma 02f939a40d SWDEV-306602 - [SANITIZER_AMDGPU] Force copyBuffer to use ROCr functions when ASAN is ON
Change-Id: I04a4cdd5ab8c5543f2a0f08c139c45ac7aebe64a
2021-10-14 12:55:27 -04:00
kjayapra-amd 88ed58735d SWDEV-232903 - Move hipmemset Dword optimization to ROCclr.
Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097
2021-10-13 11:32:15 -04:00
Jason Tang 55a0cf0b0c SWDEV-306697 - Fix OCLGlobalOffset segfaults
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.

Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121
2021-10-12 15:13:28 -04:00
Sarbojit Sarkar c06c9f7b93 SWDEV-306302 - Fix for OCLCreateImage test failure
Change-Id: I781504bd1ff599ed75c5ea730be03b71f69761b2
2021-10-07 19:52:58 +00:00
jujiang 90b0e8430a SWDEV-306207 - clean up CL definition in ROCclr
Change-Id: I92e2c7c63ebddd119df390784e372ab2f42f3b0d
2021-10-07 11:45:43 -04:00
German Andryeyev 7fe696b6ef SWDEV-303567 - Increase the size of AQL queue
ROC_AQL_QUEUE_SIZE will control the size of AQL queue.
The current sefault value is 4096.

Change-Id: Icd2a4ee3ba554c06aa05b08defd922d2c63e43fd
2021-10-06 08:27:36 -04:00
kjayapra-amd 7413b7f79b SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85
2021-10-05 18:12:44 -04:00
German Andryeyev d17108e8d0 SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1
2021-10-05 17:20:59 -04:00
kjayapra-amd 3081f7ca53 SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563
2021-10-05 12:38:44 -04:00
Tao Sang 10abe8ab37 SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d
2021-10-04 18:11:32 -04:00
Sarbojit Sarkar 22a847f3ce SWDEV-301823 - Optimize hipMemset2D/3D
Change-Id: Ibe560149a263c2ac6b08e4eb1a1d331d2aeac78c
2021-09-27 14:10:06 -04:00
Sourabh cbb8d82bdb SWDEV-292525 - [vdi] Path to streamOps shaders
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
Jason Tang f212fc91ca SWDEV-1 - More 'delete' clean up
info_.extensions_ and settings_ are deleted at amd::Device()::~Device().

Change-Id: I06f240a42e5c131dbd4e61a759f905bcdf84b45a
2021-09-21 11:17:24 -04:00
German Andryeyev f116959b54 SWDEV-302383 - Get active state from device
The queue can be destroyed at the time the app will request
the event status. Hence just get the active state from the device.

Change-Id: I887ecb0cfe414c2119247228b0d1255b8308da1e
2021-09-14 19:01:44 -04:00
German Andryeyev d8a86e4870 SWDEV-282419 - Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE for unset
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE

Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
2021-09-13 15:05:20 -04:00
German Andryeyev 65ddfcc6a8 SWDEV-294669 - Keep one more slot for HW processing
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.

Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975
2021-09-13 13:56:05 -04:00