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29acb61caeed2f1fdfbe8fcc847fc94de5605155
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12 Коммитов

Автор SHA1 Сообщение Дата
German Andryeyev 0ecf22bb53 SWDEV-336024 - Clear device heap to 0 
This reverts commit 8624574866.

Reason for revert: Fix regressions

Change-Id: I7d883e1c3cbd27bb64b581ec800243ad7dfe24fd


[ROCm/clr commit: 07c1b9a998]
 2022-05-19 09:10:08 -04:00
German Andryeyev 8624574866 SWDEV-336024 - Clear device heap to 0 
The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.

Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb


[ROCm/clr commit: 04bfd93569]
 2022-05-11 11:03:56 -04:00
kjayapra-amd 31c0525344 SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261. 
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca


[ROCm/clr commit: 7fb80a027a]
 2022-03-31 09:02:33 -04:00
kjayapra-amd f74515778c SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns." 
This reverts commit 7220267211.

Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39


[ROCm/clr commit: 2e9bc8f793]
 2021-11-28 23:39:40 -05:00
kjayapra-amd 7220267211 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns. 
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d


[ROCm/clr commit: 8307886644]
 2021-11-19 10:32:40 -05:00
kjayapra-amd 9f68891f68 SWDEV-232903 - Change pattern64 to uint64_t from size_t to handle 32 bit machines. 
Change-Id: I423cd14d145556544563027931562d7b8bf9442d


[ROCm/clr commit: 4c8b32b13c]
 2021-10-18 14:31:09 -04:00
kjayapra-amd 6f62f832cb SWDEV-232903 - Move hipmemset Dword optimization to ROCclr. 
Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097


[ROCm/clr commit: 88ed58735d]
 2021-10-13 11:32:15 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write 
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
 2021-02-15 17:02:38 -08:00
Laurent Morichetti b3297f189d Replace cl_* integral types with standard types. 
cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t

Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58


[ROCm/clr commit: d9d9c69399]
 2020-02-12 13:16:06 -08:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00