AI/rocm-systems
2
0
Форкнуть 0
Код Задачи Запросы на слияние Действия Пакеты Проекты Релизы Вики Активность
4 615 коммитов 3 Ветки 0 Теги
29acb61caeed2f1fdfbe8fcc847fc94de5605155
Граф коммитов

77 Коммитов

Автор SHA1 Сообщение Дата
Sarbojit Sarkar e6f0d30295 SWDEV-343921 - Updating default stack size for OpenCl tasks 
Change-Id: I37cdd8808dddaa7ac0544b76d18de64b27e443bd


[ROCm/clr commit: c72a396c1f]
 2022-08-26 04:57:00 -04:00
jie1zhan e668b22b11 SWDEV-352127 - Fix clinfo issue, add new asic id 
Change-Id: Idc6ff6fe647878f32f8dbb0613cbb879ea21ecdf


[ROCm/clr commit: 2aa7e5819f]
 2022-08-25 08:23:21 +08:00
Satyanvesh Dittakavi af659de4c1 SWDEV-336448 - Support loading comgr versioned dll 
Change-Id: I03283fc2a200d778c5efa43e509624bba9ce0541


[ROCm/clr commit: 64c1c4757f]
 2022-08-19 00:38:19 -04:00
Alex Xie 3a32ec1232 SWDEV-351337 - Add new asic id 
Change-Id: Ie07f7a6b9a4bb797124e6644c91fb62ba014cf6b


[ROCm/clr commit: aafa057c9a]
 2022-08-12 13:14:06 -04:00
Sarbojit Sarkar a0981a092b SWDEV-343921 - added Max stack size 
Change-Id: I5c1a088e05215ca951afc9d92f8d298c5e3a65f1


[ROCm/clr commit: 27a08a132f]
 2022-08-02 07:13:18 -04:00
sdashmiz 3389e6077a SWDEV-334233 - add support for p2p in windows 
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: I9109120b5444c400e65cfff869cb36e876ffd1fc


[ROCm/clr commit: e176e27bf7]
 2022-07-14 15:07:33 -04:00
kjayapra-amd dafc544279 SWDEV-344950 - Enable gfx1100 and gfx1102 on ROCm backend. 
Change-Id: Ic559a804e6d504b73a7cea4aba086790956ee018


[ROCm/clr commit: e2b49690f2]
 2022-07-05 20:25:42 -07:00
Christophe Paquot dc2aab85b2 SWDEV-322620 - Virtual Memory Management 
Introducing a VirtualMemObj map as it is needed to differentiate
between virtual address ranges and actual physical memory
This is because a whole VA range can have several physical memories
as chunks.

Change-Id: Ie2a972b4faf3f7d552cfa53e77898f80ad75740a


[ROCm/clr commit: 905088e4e7]
 2022-06-06 11:32:22 -07:00
German Andryeyev 0ecf22bb53 SWDEV-336024 - Clear device heap to 0 
This reverts commit 8624574866.

Reason for revert: Fix regressions

Change-Id: I7d883e1c3cbd27bb64b581ec800243ad7dfe24fd


[ROCm/clr commit: 07c1b9a998]
 2022-05-19 09:10:08 -04:00
Sarbojit Sarkar ee5bcf6444 SWDEV-331066 - support for LimitStackSize 
Change-Id: Ie6ae74f008b4f72de83663194aafb0ebdddfc8b6


[ROCm/clr commit: 51a00aeefe]
 2022-05-19 00:24:06 -04:00
German Andryeyev 8624574866 SWDEV-336024 - Clear device heap to 0 
The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.

Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb


[ROCm/clr commit: 04bfd93569]
 2022-05-11 11:03:56 -04:00
Maxime Chambonnet 38928e85c1 SWDEV-1 - ROC CLR typos 
This is cherry-picked from this github issue:
https://github.com/ROCm-Developer-Tools/ROCclr/issues/28

Change-Id: I236f4f25a2dabe05883159af0fab0bad06ab0fd0


[ROCm/clr commit: d45794e985]
 2022-04-11 14:24:39 -04:00
German Andryeyev b813a78c80 SWDEV-307185 - Move memory allocation under device layer 
It can be too early to allocate memory at the begining of
Device::create() under PAL

Change-Id: I4bd76db7be3f6fb246243ea68022d8b0f860471d


[ROCm/clr commit: 3af3fe10de]
 2022-03-21 16:17:22 -04:00
Saleel Kudchadker 4a9f9f1671 SWDEV-301667 - Remove guarantee 
Remove guarantee from AddMemObj as one can call it multiple times for
different devices

Change-Id: I49dd76068b3c4c709f17541159052302dcdb374d


[ROCm/clr commit: 3bf1d5ac97]
 2022-03-08 16:20:10 -08:00
German Andryeyev 7d5ed33e8f SWDEV-307185 - Create heap for device memory allocator 
Pass the allocated heap with the kernel arguments

Change-Id: Icdec09b7f937845c39e21cbca7071dc3ba791af9


[ROCm/clr commit: 7b114a2b8b]
 2022-03-04 00:44:41 -05:00
German Andryeyev 3c4f97f66c SWDEV-286150 - Remove GSL backend 
Change-Id: Iba9a997ee7d5ff6ac00d5888ff189a4514958fe9


[ROCm/clr commit: 525a1bbf1a]
 2022-02-09 17:16:39 -05:00
Todd tiantuo Li 1f9f598d92 SWDEV-297292 - add gfx90c:xnack+ support as gfx90d 
Change-Id: I90e28981a7cbc0f9a0105c16e9dda3ad8ac57f51


[ROCm/clr commit: fbbae8055f]
 2022-02-02 14:24:19 -08:00
German Andryeyev 9c0b3d2d2f SWDEV-318505 - Update HSAIL xnack path 
Fix a typo with new line

Change-Id: I7fee63409b491a1f214117b68cfffa0492aa0743


[ROCm/clr commit: b169956c78]
 2022-01-27 13:07:11 -05:00
German Andryeyev ea28025939 SWDEV-318505 - Update HSAIL xnack path 
Report proper target id for xnack in HSAIL path. Runtime
will use ISA table and report hsailName().
Fix offline compilation path for PAL.

Change-Id: Ic0250bf6b9c193d867aec9800a319da1bf00c3ee


[ROCm/clr commit: a543d4a860]
 2022-01-24 09:27:32 -05:00
Satyanvesh Dittakavi 85c2cac111 SWDEV-306939 - Fix vdi errors/warnings by CppCheck 
Change-Id: I56d910f8363787f1050d5d7e8064ed553c5827fd


[ROCm/clr commit: e20dd61932]
 2022-01-12 00:22:16 -05:00
Julia Jiang 41eef3076e SWDEV-308644 - reorganize extra blit kernel in PAL stack 
Change-Id: I9d853e8d417ef75b522184d83646ec4b9fa8669b


[ROCm/clr commit: 376ea1e293]
 2021-12-07 14:55:20 -05:00
Julia Jiang ea2741f631 SWDEV-308644 - merge roc blit kernels 
Change-Id: I378e511959fe17c03fa45066022e9670a4d181f0


[ROCm/clr commit: f5c9ad5b1d]
 2021-11-25 10:07:51 -05:00
kjayapra-amd cfb15c6c5d SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported. 
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85


[ROCm/clr commit: 7413b7f79b]
 2021-10-05 18:12:44 -04:00
Jason Tang e94aec09bd SWDEV-1 - Some 'delete' clean up 
Change-Id: I02564f0f0e349375bde1471e9f82df268703367b


[ROCm/clr commit: 73967c3b17]
 2021-09-09 12:12:40 -04:00
Todd tiantuo Li 9458b7ea4d SWDEV-1 - Rembrandt support 
Change-Id: Id5c37e130fb2c0bdc01b84997c85324121ec4df9


[ROCm/clr commit: ec411737aa]
 2021-08-22 23:56:08 -07:00
Jason Tang 4e818587a2 SWDEV-297294 - Fix TargetID typo 
Change-Id: I351e38cbcaaf926f0561c96cf6e455e7167fd4be


[ROCm/clr commit: f42103c6a8]
 2021-08-22 23:56:08 -07:00
Alex Xie 1ca153409c SWDEV-288853 - [OpenCL]: ASIC 1013 Bringup 
This a cherry pick from the ASIC's branch.

Change-Id: Ic6e888f8fa96103d1e79432dd75e68faabd8cf6c


[ROCm/clr commit: ce5cc020af]
 2021-08-22 23:56:08 -07:00
Aaron Liu 8979836575 SWDEV-294027 - [Lnx][YC] Add Yellow Carp support 
Only add Roc path and don't use Pal path.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I7117e2dc3c3ad4c8d563e9bbdc721f70ddba51fd


[ROCm/clr commit: c6574cb906]
 2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 04e5354d88 SWDEV-292021 - Fix Device Reset 
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041


[ROCm/clr commit: 924695fb5e]
 2021-08-22 23:56:08 -07:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
Vladislav Sytchenko 6c612d8ce7 SWDEV-274815 - [PAL] Navi24 support 
Change-Id: I934797bda471618c3f69484a1552b37345ae638b


[ROCm/clr commit: f6c00765e7]
 2021-08-22 23:56:07 -07:00
Aaron Liu e1b277f4ce SWDEV-290474 - [Lnx][VanGogh] Add VanGogh support 
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Christophe Paquot <christophe.paquot@amd.com>
Change-Id: Iff0253a181bbfc1984304014a9e3b542b2556635


[ROCm/clr commit: fe2d7424e5]
 2021-08-22 23:56:07 -07:00
Alex Xie 5e002ce6f0 SWDEV-290306 - [LNX][Navi24][mainline]clinfo test failed on Navi24 
Add Navi 24 support

Change-Id: I7343384cf6fb8c532321e57e202c196ef054f459


[ROCm/clr commit: b818301d53]
 2021-08-22 23:56:07 -07:00
Christophe Paquot b8de199652 SWDEV-276396 - Implement hipDeviceReset 
Add a Purge function to MemObjMap

Change-Id: Iac51dfda9a7b7c45f2f4a0dc35f7a623121aba1a


[ROCm/clr commit: d13581efa7]
 2021-08-22 23:56:07 -07:00
Vladislav Sytchenko de280603a7 SWDEV-289548 - [PAL] Revive Raven 2 support 
Revert back to using the Raven (gfx902) target ID for Raven 2 (gfx909).
This is due to the HSAIL compiler not supporting gfx909.

In theory there should be no issue with running Raven isa on Raven 2.

Change-Id: I425edebc99075799eda5522fad231b8fb3184873


[ROCm/clr commit: 0b1481d4f1]
 2021-08-22 23:56:07 -07:00
kjayapra-amd 8f1e9bb054 SWDEV-288690 - Updating the return value with roc::Device::init 
Change-Id: I132fa424cf9bec608e5c8429e93d20e78b76c6f0


[ROCm/clr commit: d2bf9f9b58]
 2021-08-22 23:56:07 -07:00
Jason Tang e8ca936563 SWDEV-287332 - Disable NullDevice in HIP 
Change-Id: I45c6010d2a3fcd0576438e3c72fbed78dff09b6b


[ROCm/clr commit: 7932b5a562]
 2021-05-26 09:27:59 -04:00
Ravi C Akkenapally 51663d1605 SWDEV-245531 - GLInterop: Add Buffer Interop support 
Change-Id: I38326173475e84f8eca2605522542ef89a3cf524


[ROCm/clr commit: 0aa524363d]
 2021-05-19 12:24:24 -07:00
kjayapra-amd aae0d4ca51 SWDEV-286346 - Implement Arena Memory Object for externally created memory. 
Change-Id: I8530602d89edf83ad367c52167e48a1559ee1e18


[ROCm/clr commit: 1c49d8816c]
 2021-05-18 10:59:52 -04:00
Jason Tang 6cd1f5854e SWDEV-277566 - Separate code object loading from building 
Change-Id: I87b8178f55e8ef23762dfe11fab71665ba680f00


[ROCm/clr commit: 211ba25b4e]
 2021-05-13 08:41:35 -04:00
Brian Sumner 567d9cc617 SWDEV-285332 - move common context into parent 
Change-Id: I99ceb62ad948e1fa9d1dcaa5ede98626cc95bea7


[ROCm/clr commit: 6d09a83b2d]
 2021-05-09 09:18:39 -07:00
Vladislav Sytchenko c585ae92a7 SWDEV-280473 - Support HSAIL shared library build 
This change makes HSAIL usage similar to that of Comgr. By default, the
runtime will statically link against it, however if HSAIL_DYN_DLL is
defined, then the runtime will try to dynamically load HSAIL.

Currently stick to statically linking to HSAIL. In a feature patch the
dynamic loading behaviour will be enabled.

Change-Id: I6a78a4375975cf847f236b200404c8cf941d012b


[ROCm/clr commit: c7b50bb890]
 2021-04-14 12:25:54 -04:00
Vladislav Sytchenko 7b3014ec69 SWDEV-280473 - Remove HSAIL support from the ROCm backend 
In adition to removing the HSAIL logic from the ROCm backend, guard all
of the HSAIL includes in the common layer behind the WITH_COMPILER_LIB
define. This is to avoid including HSAIL headers when building with
no support for it.

In common logic replace the use of the aclType enum with the new
Program::file_type_t enum. This is essentially a local copy of the HSAIL
enum to avoid including any HSAIL headers.

Change-Id: Ica0651d1b29dfccc255cc584eb82a5cb35e1b520


[ROCm/clr commit: cbeb372e46]
 2021-04-12 14:55:06 -04:00
Jason Tang 636bdbd0fa SWDEV-277559 - Remove AMDIL 
The rest of AMDIL support will be removed along with orca backend.

Change-Id: I0462501e7147dc4b99870fd02034d0a4a0496e55


[ROCm/clr commit: 1a38be8972]
 2021-04-09 14:15:15 -04:00
Konstantin Zhuravlyov 48a2ce0404 SWDEV-76911 - Target ID workarounds in vdi runtime: 
- Add HSAIL ID for Hawaii as gfx702
  - Add HSAIL ID for Renoir without xnack as gfx90c

Fixes: SWDEV-271289, SWDEV-272761
Change-Id: I92cf4619cdfd550462ff8ec3740443ef1e5a5f96


[ROCm/clr commit: 3010cf0a58]
 2021-04-08 12:14:25 -04:00
Todd tiantuo Li 142a5d196c SWDEV-1 - enable gfx90c for ROC and PAL paths 
Change-Id: If5c4f1ca1b136e14b9e11cd27b1beff386adc377


[ROCm/clr commit: 0d7ded0bfb]
 2021-04-01 12:02:08 -07:00
Vladislav Sytchenko 9f2bb57232 SWDEV-1 - Remove unannounced asic 
Change-Id: I0ec360e7f924dcfbc26bc70981a714abb57804c9


[ROCm/clr commit: b4064ad557]
 2021-03-03 23:21:41 -05:00
Vladislav Sytchenko 3cd2c487d3 SWDEV-193973 - Enable HSAIL for all Navi Asics 
Change-Id: I0a48442f9a970de3d449e512293bc4600c62db13


[ROCm/clr commit: 4e1232a110]
 2021-02-26 11:56:09 -05:00
kjayapra-amd d26aceba19 SWDEV-274058 - Porting HIP, ROCclr gfx90a changes to mainline. 
Change-Id: I4f4220df77e57f749a00c1dbb66743ac5af4959a


[ROCm/clr commit: 46a50965c4]
 2021-02-24 09:55:54 -05:00
German Andryeyev b5e80a048a SWDEV-86035 - Enable PAL for gfx8 
Change-Id: Ia6623993e44aeb4bdf317628ee8a84af6c4cacc7


[ROCm/clr commit: e7c636c5e7]
 2021-02-11 14:25:43 -05:00