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Συγγραφέας SHA1 Μήνυμα Ημερομηνία
Satyanvesh Dittakavi 85c2cac111 SWDEV-306939 - Fix vdi errors/warnings by CppCheck
Change-Id: I56d910f8363787f1050d5d7e8064ed553c5827fd


[ROCm/clr commit: e20dd61932]
2022-01-12 00:22:16 -05:00
German Andryeyev b8ab281765 SWDEV-317061 - Fix 32-bit HSAIL complib load
Use __stdcall decl to match the library defines

Change-Id: Id4178443d5a9bb4e5401d80b3b5d15c7bbea0330


[ROCm/clr commit: e0a4e0df0e]
2022-01-04 16:48:18 -05:00
haoyuan2 74c05e9bc1 SWDEV-316150 - align with OCL to use wavefront64 on Navi21/22/23/24
Change-Id: Ic47bc7cc6300c217c02c2bbbda9940a3b5c9597d


[ROCm/clr commit: 3d5d9e2691]
2021-12-28 12:39:18 -08:00
Saleel Kudchadker 500f6a6513 SWDEV-313306 - Fix Co-operative groups dtests
Add a state indicator to retain ExternalSignals when needed.
Co-operative group launch uses external signals to indicate a dependency
to the next command.

Change-Id: I6d0daa006e2377c3bbf4aeca0fd5b63c7ac8fbbb


[ROCm/clr commit: 1fbd75b825]
2021-12-17 12:41:37 -08:00
Saleel Kudchadker 42625f0527 SWDEV-313306 - Clear external signals
Crash was due to the fact that external signal structure was stale even
after destroyign the command. That is because we skipped wait due to a
missing check.
Detect external signals and dispatch a barrier in ReleaseGpuMemoryFence.
Also clear external_signals_ at ProfilingBegin.

Change-Id: I991387edcfe928b511bf5e780988ee131321ed5a


[ROCm/clr commit: 3239222516]
2021-12-13 23:03:33 -08:00
German Andryeyev c759986e28 SWDEV-300515 - Apply CU granularity on the CU count
Report granularity for possible app query

Change-Id: I98857c6f4cc7ae590927ea35ce57d181abe7860b


[ROCm/clr commit: f613831471]
2021-12-10 10:47:28 -05:00
Sarbojit Sarkar 4630f3ade0 SWDEV-314254 - Fix for hipMemcpy3D test crash
Change-Id: Iac70bfe0d351cfb5b56fefc9a6487d3f26f2b4ef


[ROCm/clr commit: aedbad0109]
2021-12-09 11:46:52 -05:00
German Andryeyev 5ad02b78c4 SWDEV-305016 - Improve MGPU scaling in Tensorflow
Add a threshold for ROCR/SDMA P2P transfers. ROCR copy path
requires extra barriers in compute for synchronization. That costs
extra performance with tiny transfers.
Reduce active wait time to 10us. Tensorflow uses extra thread
per GPU with constant hipEventQuery() calls. Longer active waits
in ROCr affect CPU performance.

Change-Id: I9020358438615fa2d4617f862f00a562f0a588e7


[ROCm/clr commit: 008133cf41]
2021-12-08 11:59:37 -05:00
Julia Jiang 41eef3076e SWDEV-308644 - reorganize extra blit kernel in PAL stack
Change-Id: I9d853e8d417ef75b522184d83646ec4b9fa8669b


[ROCm/clr commit: 376ea1e293]
2021-12-07 14:55:20 -05:00
Christophe Paquot 1b87d3a497 SWDEV-307109 - Don't force Persistent for HIP
With SAM on, don't force Persistent for allocations
in HIP. This makes ROCCLR go down paths we don't want
for HIP.

Change-Id: If54cc16fa891d4cfdc761c6ab21ad707627e822a


[ROCm/clr commit: 5243552768]
2021-12-06 12:16:08 -05:00
Satyanvesh Dittakavi b219bf8292 SWDEV-309286 - save the max system mem size in device info
Change-Id: I9955625aca6ceda059aef6354d909de636b610ba


[ROCm/clr commit: 9dabdcdc3e]
2021-12-02 10:59:07 -05:00
Saleel Kudchadker 97456a157b SWDEV-308843 - Increase MaxPinnedXferSize to 128
This allows experimenting with env var GPU_PINNED_XFER_SIZE which is
still at a default of 32MB

Change-Id: I85ade700ed58d498eba29d1737601dc74d4c26a4


[ROCm/clr commit: 3f82b99f5d]
2021-12-01 20:37:56 -05:00
anusha GodavarthySurya 02e46ec231 SWDEV-284895 - Adding kind metadata and launch init/fini marked kernels
Change-Id: If2b21c4b98567632c426943e0b69aca8d6f1ec2a


[ROCm/clr commit: 102aa9d6d9]
2021-12-01 08:17:44 -08:00
Sarbojit Sarkar c8a6920b91 SWDEV-310181 - Fix for AtoH Memcpy tests failure
Change-Id: Ibf8c8c01257f0516088d50d5c9f82040ed8fa067


[ROCm/clr commit: 02dc6f9f9a]
2021-11-29 22:55:23 -05:00
kjayapra-amd f75cfb049a SWDEV-312822 - Fix the globalWorkSize to number of sizeof(var) instead of bytes.
Change-Id: Ic6b2bbb2e8d4cb6aa8d906d4b93cd06a176160d8


[ROCm/clr commit: d4ad981c0c]
2021-11-29 17:36:11 -05:00
German Andryeyev 861b9fb84c SWDEV-294669 - Avoid stall when the new signal was created
Stall in the host thread could occur earlier than the app expects.
Make sure rutnime can grow the signals to the queue size without
any stall. Also adding a new signal to the end of the pool could
break the dependency chain on signal reuse. The new logic will
insert the new signal after current to keep the chain intact.

Change-Id: I9c90b98515907db8b677528263c3e88cd9581a14


[ROCm/clr commit: 102c19adf3]
2021-11-29 10:08:06 -05:00
kjayapra-amd f74515778c SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns."
This reverts commit 7220267211.

Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39


[ROCm/clr commit: 2e9bc8f793]
2021-11-28 23:39:40 -05:00
German Andryeyev b0b0c3049f SWDEV-313126 - Use data() method for the base array address
Reference for the first element can trigger an assert with
_GLIBCXX_ASSERTIONS build

Change-Id: I59c63c052831307edfe5dcc6384798a43e9596dd


[ROCm/clr commit: 6f2e7c3199]
2021-11-26 09:51:57 -05:00
Julia Jiang ea2741f631 SWDEV-308644 - merge roc blit kernels
Change-Id: I378e511959fe17c03fa45066022e9670a4d181f0


[ROCm/clr commit: f5c9ad5b1d]
2021-11-25 10:07:51 -05:00
kjayapra-amd 7220267211 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns.
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d


[ROCm/clr commit: 8307886644]
2021-11-19 10:32:40 -05:00
Saleel Kudchadker 04a391004a SWDEV-299893 - Set preferred node affinity
Set affinity to the closest node of the current GPU. This reduces
the latency to fetch kernel args since device would query the CPU cache
of core which did the dispatch. This behavior is controlled with
AMD_CPU_AFFINITY env var(disabled by default)

Change-Id: I65afba62cb818ea25a311b88d1c0dd5c51330292


[ROCm/clr commit: b192beea52]
2021-11-19 04:42:42 -05:00
German Andryeyev c116411e00 SWDEV-294669 - Avoid queue drain
Use slot wait logic for direct dispatch

Change-Id: I431ba1418eb4aa066b9881934f4055b3d338ce3a


[ROCm/clr commit: 8e4101b4fd]
2021-11-18 13:06:12 -05:00
pghafari e7df603b2a SWDEV-297142 - HIP-Vulkan - linux interop buffer
Change-Id: I0278e56bba632024c214beb9e1758587ccba0927


[ROCm/clr commit: e38a200bf7]
2021-11-17 06:06:58 -05:00
German Andryeyev 95c01935b8 SWDEV-305016 - Correct timeout logic
Timeout logic should be applied always even if the wait is active.

Change-Id: I2e5db7ac8a0f9a0355ad7b40e4227d76fb002aa0


[ROCm/clr commit: 9877fc9dbf]
2021-11-16 23:04:34 -05:00
Julia Jiang e3f6db3d64 SWDEV-308644 - update blit kernel setup in rocm
Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c


[ROCm/clr commit: ef3d6f7b28]
2021-11-15 13:28:07 -05:00
kjayapra-amd 2fdfb47092 SWDEV-309657 - Align Virtual queue size to sizeof(uint64_t).
Change-Id: Ia55d7316693bd13938875ce53f7849d5eb658e8c


[ROCm/clr commit: 7e32d6d909]
2021-11-12 10:35:36 -05:00
German Andryeyev 0b03dde692 SWDEV-286150 - Add detailed thread trace support in RGP
- Create hash values for binaries
- Add the binaries into RGP trace
- Add corresponding hash value for every dispatch

Change-Id: I2c3ce004d69f37d0d46bc4744e12f24273517f5e


[ROCm/clr commit: 2a298f2ec3]
2021-11-10 14:46:02 -05:00
German Andryeyev 92be4f5781 SWDEV-286150 - Fix a crash when LC is forced
Change-Id: I1127490502012cdbc0391e45b5d9310f04f9482b


[ROCm/clr commit: b0af08ac04]
2021-11-05 12:35:11 -04:00
German Andryeyev 7a9f92d95e SWDEV-305016 - Add a timeout wait into IsHwEventReady()
Just signal check will still submit the marker and then later
runtime will have a timeout, but the barrier packet is still
generated. Hence early timeout will allow to skip the marker.

Change-Id: Ieb7d89becbcff43a4f4c46715354ca65ab4a80b9


[ROCm/clr commit: bbb635bc32]
2021-11-02 11:37:23 -04:00
German Andryeyev 7821cddb3e SWDEV-257789 - Initial change to skip kernel arg copy
The optimization is controlled with ROCR_SKIP_KERNEL_ARG_COPY.
This is initial check-in for experiments. Extra changes are
necessary for full support:
- handle graph capture with the original sysmem alloc
- avoid memobject references, otherwise there is a race condition with
reusage of the arg buffer
- Remove arg setup from hip

Change-Id: Ib0af710f93e79834711fa4049a7c66093711e68b


[ROCm/clr commit: 7e12cf6318]
2021-10-28 20:35:35 -04:00
German Andryeyev 2d2d33dd9c SWDEV-303567 - reset kernel arg buffer to chunk 0
Change-Id: I2974e31af9700705554b0f274ede6f8b9a9d6e7b


[ROCm/clr commit: 30bba18a06]
2021-10-27 22:15:55 -04:00
Alex Xie da48f060f4 SWDEV-305752 - OCL WIN Conformance select test fail
Change-Id: I73571c262a14d6b27d8cf91b6d1a13e1974ddc96


[ROCm/clr commit: 0e321f45c1]
2021-10-27 19:54:24 -04:00
German Andryeyev 22182e12bd SWDEV-286150 - Switch PAL to 678 interface
Change-Id: I3c130998902654e1dffc954ddf33530ea998ac34


[ROCm/clr commit: 4aea2ad172]
2021-10-27 17:25:02 -04:00
Alex Xie d84cde7888 SWDEV-308726 - OCL WIN - Conformance SVM Test failing
SVM mapping should not use direct mapping in Windows PAL

Change-Id: I005115bdce6ef99f471bb08fa8d042fa644587a6


[ROCm/clr commit: fa73e0cfcc]
2021-10-27 03:20:47 -04:00
German Andryeyev d8201bc1ce SWDEV-303567 - Add chunks for the pool of kernel arguments
The kernel arg pool will be divided into 8 chunks to avoid long stalls,
when the pool will be reused.

Change-Id: I228e6ca1c09e428c1775f1e5b685220a9a5d71af


[ROCm/clr commit: f78b3a8919]
2021-10-26 16:31:37 -04:00
Sarbojit Sarkar 2e1ec62950 SWDEV-306773 - Pal fix for 2D/3D memset
Change-Id: Id705e9292e17621ea70e283d7494212809456e27


[ROCm/clr commit: c218022296]
2021-10-25 00:37:18 -04:00
kjayapra-amd 9f68891f68 SWDEV-232903 - Change pattern64 to uint64_t from size_t to handle 32 bit machines.
Change-Id: I423cd14d145556544563027931562d7b8bf9442d


[ROCm/clr commit: 4c8b32b13c]
2021-10-18 14:31:09 -04:00
kjayapra-amd f7053598c5 SWDEV-232903 - Adding string to guarantee message, which is required on windows.
Change-Id: I86d3d53126aa4baa1ffc27295e4f908ac7028551


[ROCm/clr commit: 5a33a15c42]
2021-10-14 15:17:25 -04:00
Bing Ma 213b5dffd1 SWDEV-306602 - [SANITIZER_AMDGPU] Force copyBuffer to use ROCr functions when ASAN is ON
Change-Id: I04a4cdd5ab8c5543f2a0f08c139c45ac7aebe64a


[ROCm/clr commit: 02f939a40d]
2021-10-14 12:55:27 -04:00
kjayapra-amd 6f62f832cb SWDEV-232903 - Move hipmemset Dword optimization to ROCclr.
Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097


[ROCm/clr commit: 88ed58735d]
2021-10-13 11:32:15 -04:00
Jason Tang e4db6ef66a SWDEV-306697 - Fix OCLGlobalOffset segfaults
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.

Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121


[ROCm/clr commit: 55a0cf0b0c]
2021-10-12 15:13:28 -04:00
Sarbojit Sarkar 548bcfb23b SWDEV-306302 - Fix for OCLCreateImage test failure
Change-Id: I781504bd1ff599ed75c5ea730be03b71f69761b2


[ROCm/clr commit: c06c9f7b93]
2021-10-07 19:52:58 +00:00
jujiang 7efd69cecd SWDEV-306207 - clean up CL definition in ROCclr
Change-Id: I92e2c7c63ebddd119df390784e372ab2f42f3b0d


[ROCm/clr commit: 90b0e8430a]
2021-10-07 11:45:43 -04:00
German Andryeyev 51f7944fcb SWDEV-303567 - Increase the size of AQL queue
ROC_AQL_QUEUE_SIZE will control the size of AQL queue.
The current sefault value is 4096.

Change-Id: Icd2a4ee3ba554c06aa05b08defd922d2c63e43fd


[ROCm/clr commit: 7fe696b6ef]
2021-10-06 08:27:36 -04:00
kjayapra-amd cfb15c6c5d SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85


[ROCm/clr commit: 7413b7f79b]
2021-10-05 18:12:44 -04:00
German Andryeyev 2cb7467eff SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1


[ROCm/clr commit: d17108e8d0]
2021-10-05 17:20:59 -04:00
kjayapra-amd ead79defbe SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563


[ROCm/clr commit: 3081f7ca53]
2021-10-05 12:38:44 -04:00
Tao Sang e425c5e79b SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d


[ROCm/clr commit: 10abe8ab37]
2021-10-04 18:11:32 -04:00
German Andryeyev 4aed0e4a01 SWDEV-296301 - Avoid deadlocks in the hostcall path
Change the scope of hostcall buffer access lock during destruction.
Make sure wait() returns the signal value after timeout. That
matches ROCr behaviour for HSA signal wait.

Change-Id: I3df34207e0c2e21972ec8052777e5742bda1dca0


[ROCm/clr commit: 9a9d10a10b]
2021-10-04 15:00:44 -04:00
Julia Jiang 1778d99932 SWDEV-302493 - Comgr API backward compatible
Change-Id: I3d796d10fa1dbb7edb0510f8ed7d44e3b4993bd7


[ROCm/clr commit: 3098324ef7]
2021-09-29 11:43:43 -04:00