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Autor(a) SHA1 Mensagem Data
Evgeny Mankov 2478fc078f Formatting, no functional changes 
[ROCm/clr commit: d9a94191f2]
 2016-02-10 17:21:18 +03:00
Evgeny Mankov d9a94191f2 Formatting, no functional changes 2016-02-10 17:21:18 +03:00
Evgeny Mankov 3a032ff317 Formatting, no functional changes 
[ROCm/hip commit: 254da4ec53]
 2016-02-10 17:21:18 +03:00
Evgeny Mankov 254da4ec53 Formatting, no functional changes 2016-02-10 17:21:18 +03:00
streamhsa 03c2768897 Remove test for atomicInc and atomicDec 
[ROCm/clr commit: 90add185fd]
 2016-02-10 21:02:52 +08:00
streamhsa 90add185fd Remove test for atomicInc and atomicDec 2016-02-10 21:02:52 +08:00
streamhsa 4c861f0284 Remove test for atomicInc and atomicDec 
[ROCm/hip commit: 51bff8757c]
 2016-02-10 21:02:52 +08:00
streamhsa 51bff8757c Remove test for atomicInc and atomicDec 2016-02-10 21:02:52 +08:00
Yair Shachar a815a4337f Disable scratch Host allocation - via debug registration flags. 
Change-Id: Ia6e5f86ec3979c4a49800f7af4509442a4e5be27
Signed-off-by: Yair Shachar <Yair.Shachar@amd.com>
 2016-02-10 07:52:32 -05:00
Yair Shachar 8359dc3119 Disable scratch Host allocation - via debug registration flags. 
Change-Id: Ia6e5f86ec3979c4a49800f7af4509442a4e5be27
Signed-off-by: Yair Shachar <Yair.Shachar@amd.com>


[ROCm/ROCR-Runtime commit: a815a4337f]
 2016-02-10 07:52:32 -05:00
streamhsa 688a9a19a5 Updated readme for test 
[ROCm/clr commit: 56f1832e70]
 2016-02-10 20:05:59 +08:00
streamhsa 56f1832e70 Updated readme for test 2016-02-10 20:05:59 +08:00
streamhsa 1c89a8853a Updated readme for test 
[ROCm/hip commit: 6f2a94fb93]
 2016-02-10 20:05:59 +08:00
streamhsa 6f2a94fb93 Updated readme for test 2016-02-10 20:05:59 +08:00
streamhsa 5d857b2bc3 Resolved test issues 
[ROCm/clr commit: 2f8d56e903]
 2016-02-10 20:01:16 +08:00
streamhsa 2f8d56e903 Resolved test issues 2016-02-10 20:01:16 +08:00
streamhsa 837875df37 Resolved test issues 
[ROCm/hip commit: 4035b71df4]
 2016-02-10 20:01:16 +08:00
streamhsa 4035b71df4 Resolved test issues 2016-02-10 20:01:16 +08:00
foreman 77053c3c72 P4 to Git Change 1235953 by johtaylo@johtaylo-JTBUILDER03-increment on 2016/02/10 03:00:10 
SWDEV-2 - Change OpenCL version number from 2031 to 2032.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1778 edit


[ROCm/clr commit: 4a8a26801c]
 2016-02-10 03:10:47 -05:00
foreman 4a8a26801c P4 to Git Change 1235953 by johtaylo@johtaylo-JTBUILDER03-increment on 2016/02/10 03:00:10 
SWDEV-2 - Change OpenCL version number from 2031 to 2032.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1778 edit
 2016-02-10 03:10:47 -05:00
gargrahul 91a5b0aa77 Removed atomicInc and atomicDec support from HIP 
[ROCm/clr commit: 51f46d9ddf]
 2016-02-10 04:29:55 +05:30
gargrahul 51f46d9ddf Removed atomicInc and atomicDec support from HIP 2016-02-10 04:29:55 +05:30
gargrahul 1ab2294657 Removed atomicInc and atomicDec support from HIP 
[ROCm/hip commit: 8c40a4ace4]
 2016-02-10 04:29:55 +05:30
gargrahul 8c40a4ace4 Removed atomicInc and atomicDec support from HIP 2016-02-10 04:29:55 +05:30
foreman 027f022623 P4 to Git Change 1235782 by asalmanp@asalmanp-opencl-stg on 2016/02/09 15:30:16 
SWDEV-68792 - [OpenCL][HWS/CWSR] Adding support for Hardware Scheduler and Compute Wave Save restore (CWSR) feature on ORCA

	Adding a temporary w/a for a CP uCode bug in HWS mode. Due to this bug, CP uCode loops through a RUNLIST unless there is a submission on all queues in HWS mode. This causes some overhead and performance drop in PCMark8 on CZ in HWS mode. To work around this issue, it was suggested to submit a dummy packet during initialization on all available queues on HWS mode so that CP uCode can break the loop. This w/a should be removed once CP uCode provides a final fix for this issue.

	ReviewBoardURL = http://ocltc.amd.com/reviews/r/9616/

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#160 edit


[ROCm/clr commit: 45715f0c48]
 2016-02-09 17:25:20 -05:00
foreman 45715f0c48 P4 to Git Change 1235782 by asalmanp@asalmanp-opencl-stg on 2016/02/09 15:30:16 
SWDEV-68792 - [OpenCL][HWS/CWSR] Adding support for Hardware Scheduler and Compute Wave Save restore (CWSR) feature on ORCA

	Adding a temporary w/a for a CP uCode bug in HWS mode. Due to this bug, CP uCode loops through a RUNLIST unless there is a submission on all queues in HWS mode. This causes some overhead and performance drop in PCMark8 on CZ in HWS mode. To work around this issue, it was suggested to submit a dummy packet during initialization on all available queues on HWS mode so that CP uCode can break the loop. This w/a should be removed once CP uCode provides a final fix for this issue.

	ReviewBoardURL = http://ocltc.amd.com/reviews/r/9616/

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#160 edit
 2016-02-09 17:25:20 -05:00
Peng Sun a2550c7ce0 Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into doc_update 
[ROCm/clr commit: b61f0453c0]
 2016-02-09 15:08:39 -06:00
Peng Sun b61f0453c0 Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into doc_update 2016-02-09 15:08:39 -06:00
Peng Sun 691aa5cda6 Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into doc_update 
[ROCm/hip commit: 1fb48b0714]
 2016-02-09 15:08:39 -06:00
Peng Sun 1fb48b0714 Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into doc_update 2016-02-09 15:08:39 -06:00
Peng Sun 37a3263766 Fix TODO-Doc in hip_texture.h 
[ROCm/clr commit: 6731505c5f]
 2016-02-09 10:58:23 -06:00
Peng Sun 6731505c5f Fix TODO-Doc in hip_texture.h 2016-02-09 10:58:23 -06:00
Peng Sun 00ef2c28a2 Fix TODO-Doc in hip_texture.h 
[ROCm/hip commit: 28025f6a74]
 2016-02-09 10:58:23 -06:00
Peng Sun 28025f6a74 Fix TODO-Doc in hip_texture.h 2016-02-09 10:58:23 -06:00
Ben Goz 7070f7ec5e Adding support to hsaKmtMapMemoryToGPUNodes 
Change-Id: Iab6222402a43c3cd31b0efc5a316a6482986258e
Signed-off-by: Ben Goz <ben.goz@amd.com>
 2016-02-09 17:34:29 +02:00
Ben Goz 18aab410cc Adding support to hsaKmtMapMemoryToGPUNodes 
Change-Id: Iab6222402a43c3cd31b0efc5a316a6482986258e
Signed-off-by: Ben Goz <ben.goz@amd.com>


[ROCm/ROCR-Runtime commit: 7070f7ec5e]
 2016-02-09 17:34:29 +02:00
Evgeny Mankov 9f596e0aab Device property concurrentKernels is added to hipDeviceProp_t struct. 
For HCC path concurrentKernels is set to true since all ROCR hardware supports this feature.
For NVCC path concurrentKernels is obtained from CUDA's device property cudaDeviceProp::concurrentKernels.


[ROCm/clr commit: 4d4ca3ef3f]
 2016-02-09 17:10:35 +03:00
Evgeny Mankov 4d4ca3ef3f Device property concurrentKernels is added to hipDeviceProp_t struct. 
For HCC path concurrentKernels is set to true since all ROCR hardware supports this feature.
For NVCC path concurrentKernels is obtained from CUDA's device property cudaDeviceProp::concurrentKernels.
 2016-02-09 17:10:35 +03:00
Evgeny Mankov c38a69ef33 Device property concurrentKernels is added to hipDeviceProp_t struct. 
For HCC path concurrentKernels is set to true since all ROCR hardware supports this feature.
For NVCC path concurrentKernels is obtained from CUDA's device property cudaDeviceProp::concurrentKernels.


[ROCm/hip commit: 950c3baacd]
 2016-02-09 17:10:35 +03:00
Evgeny Mankov 950c3baacd Device property concurrentKernels is added to hipDeviceProp_t struct. 
For HCC path concurrentKernels is set to true since all ROCR hardware supports this feature.
For NVCC path concurrentKernels is obtained from CUDA's device property cudaDeviceProp::concurrentKernels.
 2016-02-09 17:10:35 +03:00
foreman 7080c5d4f8 P4 to Git Change 1235458 by johtaylo@johtaylo-JTBUILDER03-increment on 2016/02/09 03:00:10 
SWDEV-2 - Change OpenCL version number from 2030 to 2031.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1777 edit


[ROCm/clr commit: 9b8568bedb]
 2016-02-09 03:09:16 -05:00
foreman 9b8568bedb P4 to Git Change 1235458 by johtaylo@johtaylo-JTBUILDER03-increment on 2016/02/09 03:00:10 
SWDEV-2 - Change OpenCL version number from 2030 to 2031.

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1777 edit
 2016-02-09 03:09:16 -05:00
foreman 718365b83a P4 to Git Change 1235456 by kebai@kebai_win1 on 2016/02/09 02:47:34 
SWDEV-86836 - Enhance caching library class to prepare one-stage kernel caching by:
	0. Moving cache storage setup into constructor
	1. Controlling cache storage size
	2. Explicit cache cleanup
	    a. -kcache-wipe is off by default; when turned on, the caching directory would be wiped off
	    b. Here it's just an option. The implementation (the call of wipeCacheFolders()) will be added in the compiler library
	3. Enforcing cache miss (actual compilation enforcing and adding a new entry to the cache storage).
	    a. -kcache-enforce-miss is off by default; when turned on, the real compilation will be enforced
	    b. Here it's just an option. The implementation will be added in the compiler library
	ReviewBoardURL = http://ocltc.amd.com/reviews/r/9726/

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/OPTIONS.def#134 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/caching/cache.cpp#12 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/caching/cache.hpp#7 edit


[ROCm/clr commit: c5265e08c6]
 2016-02-09 02:52:58 -05:00
foreman c5265e08c6 P4 to Git Change 1235456 by kebai@kebai_win1 on 2016/02/09 02:47:34 
SWDEV-86836 - Enhance caching library class to prepare one-stage kernel caching by:
	0. Moving cache storage setup into constructor
	1. Controlling cache storage size
	2. Explicit cache cleanup
	    a. -kcache-wipe is off by default; when turned on, the caching directory would be wiped off
	    b. Here it's just an option. The implementation (the call of wipeCacheFolders()) will be added in the compiler library
	3. Enforcing cache miss (actual compilation enforcing and adding a new entry to the cache storage).
	    a. -kcache-enforce-miss is off by default; when turned on, the real compilation will be enforced
	    b. Here it's just an option. The implementation will be added in the compiler library
	ReviewBoardURL = http://ocltc.amd.com/reviews/r/9726/

Affected files ...

... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/OPTIONS.def#134 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/caching/cache.cpp#12 edit
... //depot/stg/opencl/drivers/opencl/compiler/tools/caching/cache.hpp#7 edit
 2016-02-09 02:52:58 -05:00
Maneesh Gupta 4df8743f84 which_hip -> hipconfig 
[ROCm/clr commit: f8bfc7f54c]
 2016-02-09 11:51:26 +05:30
Maneesh Gupta f8bfc7f54c which_hip -> hipconfig 2016-02-09 11:51:26 +05:30
Maneesh Gupta 1803451df7 which_hip -> hipconfig 
[ROCm/hip commit: 7cc7f88717]
 2016-02-09 11:51:26 +05:30
Maneesh Gupta 7cc7f88717 which_hip -> hipconfig 2016-02-09 11:51:26 +05:30
Maneesh Gupta 978aac7fe0 Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into privatestaging 
[ROCm/clr commit: 0df78ac9bf]
 2016-02-09 10:57:46 +05:30
Maneesh Gupta 0df78ac9bf Merge branch 'privatestaging' of https://github.com/AMDComputeLibraries/HIP-privatestaging into privatestaging 2016-02-09 10:57:46 +05:30