Commit Graph

32 Commits

Author SHA1 Message Date
Satyanvesh Dittakavi 1b25484f0f SWDEV-447405 - Reset the last SDMA engine after every few copies
The copies can get blocked if the last SDMA engine is used by another
copy and this can lead to perf drop in some of the tests like Gromacs.
Resetting the last engine by checking the engine status and fetching the
new mask after few copies can avoid this.

Change-Id: I8fe8ea678db508d291c6242f3741fa9215e99921
2024-03-12 02:10:27 -04:00
Saleel Kudchadker f316a30e5d SWDEV-408180 - Add a new hipMemcpyKind
Add hipMemcpyDeviceToDeviceNoCU to force a non blit copy path. This
helps in cases where an app may determine that CU may be busy and copies
with SDMA may be quicker.

Change-Id: I59b415dd8f6022c244e8d75f265464d5c635df1e
2023-10-20 13:18:10 -04:00
kjayapra-amd 6f5277c701 SWDEV-408473 - Add wait time of 10 us if the waiting signal copy was < 24K.
Change-Id: I438ec9eb07e5034042a4a9a5e6e51d74daba2c83
2023-08-23 10:46:33 -04:00
kjayapra-amd a034995f81 SWDEV-408213 - Move the init_heap blit kernel inside linear blit kernel grouping.
Change-Id: Id540018d4cceab5f01f614f7d49ef42505e69039
2023-06-29 10:36:53 -04:00
Saleel Kudchadker 0a3d4bd4d4 SWDEV-408180 - Remove largeBar memcpy
- Remove large bar memcpy path. Since we end up waiting for a barrier,
its defeating the true intent of the copy, Also memcpy over PCIE\XGMI is
introducing variability in perf for HPC apps like GROMACS

Change-Id: I3b5c9d9ce93333959c39023bf4f703e2ccb6e3af
2023-06-27 18:15:26 -04:00
Saleel Kudchadker 5865c642d4 SWDEV-384557 - Fix engine status query
- Maintain a map of SDMA engine# to stream allocated following a greedy
approach
- Anything past that will query SDMA engine status always and go with a
SDMA or Blit copy path

Change-Id: Ibfaed7f951ab84d80cb0430596a4d11b5aec9202
2023-04-21 00:57:26 -04:00
Saleel Kudchadker 20ca8b8116 SWDEV-384557 - Leverage SDMA engine status query
Change-Id: I5f386f2965de24a229ea43b6c4da82099692f91f
2023-04-05 07:50:53 +00:00
Anusha GodavarthySurya 274f2de391 SWDEV-364576 - initialize device malloc heap state using blit kernel
Change-Id: I5d0172aff7d2c04b322a4d828b8a2b438158b80f
2023-01-07 06:53:53 +00:00
Ioannis Assiouras 72b45e2a1f SWDEV-369581 - Convey copy API metadata to ROCclr
Change-Id: I569462d6d268700d419510255e201bf7d80d6714
2022-12-09 00:27:15 -05:00
Ajay 373a7d1195 SWDEV-347670 - GPU StreamWait and StreamWrite support in Windows PAL backend
Change-Id: Ic4881305b6332e217f3d3127dce7e9d9d0a7df11
2022-09-15 13:57:40 -04:00
Saleel Kudchadker 175ad024d3 SWDEV-260345 - Manage constant buffer for blit
- Leverage managed buffer that would use chunks for fill pattern. Use a
different chunk for the next fill to avoid wait

Change-Id: I254483c867e112f66564ffd8f55e0a605d8896c9
2022-07-12 12:41:02 -04:00
Ajay d2f837d25f SWDEV-332522 - streamOpsWrite & streamOpsWait to accept memory offset
Change-Id: I4b6ecb4d80c093d038d86616a637c4bb465ae24e
2022-04-25 14:59:36 -04:00
kjayapra-amd 7fb80a027a SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261.
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca
2022-03-31 09:02:33 -04:00
German Andryeyev 3fd4a67670 SWDEV-316824 - Fix P2P compute copy path
Use device memory object for the GPU VA address look-up.

Change-Id: I76bf58b29205f7b3ba1bf68e9fcca69421267203
2022-02-15 13:20:13 -05:00
kjayapra-amd 7413b7f79b SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85
2021-10-05 18:12:44 -04:00
Sourabh cbb8d82bdb SWDEV-292525 - [vdi] Path to streamOps shaders
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
Saleel Kudchadker 21ba34d0fe SWDEV-297448 - Add 64bit and 16bit write support
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
2021-09-08 12:30:04 -04:00
agunashe d96481fb36 SWDEV-293742 - Update copyright end year VDI repo
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
Ravi C Akkenapally 0a5f9a3b10 SWDEV-179105 - Stream Operations: Add support for Wait and Write
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808
2021-02-15 17:02:38 -08:00
German Andryeyev dbc7abaecf SWDEV-257787 - Add engine tracking per signal
- The logic will trace compute, sdma read/write operations and
apply signals when necessary
- ROC_CPU_WAIT_FOR_SIGNAL, ROC_SYSTEM_SCOPE_SIGNAL
and ROC_SKIP_COPY_SYNC were added to control the tracking

Change-Id: I9e8e6174c63bf7784f7ab00964e2918c8667d364
2021-01-25 12:34:45 -05:00
German Andryeyev 8698aeef0d Add HSA signal global tracking logic.
Implement the global class for signals tracking per device queue.
Switch to the new tracking mechanism.

Change-Id: I3c4dda04b34e6d18d6a95510d84102909633b415
2021-01-08 12:57:33 -05:00
Jason Tang d4316141b7 SWDEV-263539 - More Target ID fix in GSL path
On behalf of Tony Tye. The bootleg passes CQE Baffin/Ellesmere test.

Change-Id: I4c21d21b3aaba360682ef15b8a4dda239f8af276
2020-12-14 16:48:55 -05:00
Anusha Godavarthy Surya 093f7fa3ca SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name
Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622
2020-08-06 01:14:06 -04:00
Tao Sang fdef6f722f Apply constexpr on global constant varaibles
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef
2020-07-22 22:14:13 -04:00
German Andryeyev 2ce6bbebc4 Fix async mem clear
Optimization for the fence release removed a sync for mem fill.
Add simple const buffer management forr the filled pattern to avoid
pattern overwriting with the async fills.

Change-Id: I63773ac09ceec31d5396d24570e4647ff096326b
2020-05-20 11:13:41 -04:00
Michael LIAO 503ef06555 Clear executable permission.
Change-Id: Ia0d363b1ba89d7947e5b5a55cb67edba86f0515e
2020-05-07 10:38:58 -04:00
Alex Xie 6c5a42b33c SWDEV-232894 Port hipMemcpy optimizations from HCC to VDI
Apply the optimization to change for OpenCL too.
Clean up some unnecessary checks.

Change-Id: I840261fe35baeeadeba7388e86779d482f509aad
2020-04-30 11:06:28 -04:00
German Andryeyev 89133a7301 SWDEV-232807
[ROCm][TCT][HIP] cooperative stream test case is failing.

Make sure lockXfer() in the blit manager returns a valid value.
Port the latest PAL backend logic into the ROCr backend.
This change doesn't fix the issue, reported in the ticket.

Change-Id: I54101a824f49a2dcfbbf5414cb5b3af41745306d
2020-04-23 15:01:02 -04:00
kjayapra-amd 7458bf9964 SWDEV-229840 - Improve error messages on ROCCLR Layer.
Change-Id: Iab7d9156cdc206db86385aa05023a0095ed40f92
2020-04-19 20:01:49 -04:00
jujiang 518a75ca66 SWDEV-196333-hipCopyhammer_H2D&hipCopyHammer_D2H tests fix return false case
Change-Id: I919e098f8b1b8c41b200bd32dcf108977c472b43
2020-02-24 15:08:21 -05:00
Laurent Morichetti b4c6143a2f Update copyright info
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
Laurent Morichetti 20c7173849 Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00