- Don't notify if the batch is empty, because that means
the current command was processed already.
- Disable pinning optimization to avoid a race condition on stall.
- TS marker submition requires extra AQL barrier
to track the status.
Change-Id: I17eff4ad12ac66cfe1bb44048bebb1891805279d
[ROCm/clr commit: 24299e25bd]
1. Fix the size of the memory when releasing.
2. Make sure we only count the device memory
Change-Id: Ib4dcda79f313c4ee9cc1c7bab53f8076bce5f583
[ROCm/clr commit: 639d67866c]
Since the allocation can be a suballocation, we should print both the
VA range for the allocation and the underlying memory object.
Change-Id: Ic9c707bbb78113b366d1b2c688e6fd33bdc8fd94
[ROCm/clr commit: 9e8a2f3266]
The settings need to be populated ASAP, otherwise the dummy context is
not created properly.
Change-Id: Iede0066308bb601dc68164e894775a646a0372f1
[ROCm/clr commit: 263173914f]
GPU waits have noticeable overheads on compute with extra
AQL barrier packet and on SDMA with power saving features. This
change introduces a wait on CPU for 30 us in case the app has tiny
operations.
Change-Id: I761ba3af595f3f48544980058a9077dda15aa5f9
[ROCm/clr commit: ac387f9b03]
This change unifies the hostcall implementation for all the backends,
by pushing the common logic to the device layer. This is done by
replacing the use of hsa_signal_t with device::Signal (a light wrapper
around it).
Change-Id: I7b6fca7930b5a0b199da5d85e2e048354cc04e7b
[ROCm/clr commit: 671778bdd3]
- Avoid GPU wait on the marker submission and update the command
batch after HSA signal callback upon HSA barrier completion.
Change-Id: I5c1c97212aefc2ae4b99aa9e2a81627ee9a38c1c
[ROCm/clr commit: 6966d8098e]
In pitch workaround, we need to copy the image to copy buffer
when application wants to read image to buffer. After this
patch, we unconditionally copy the image data to the copy buffer.
Change-Id: I71b0d19459542dfbb3ca51a2c8a3a81367fa2fb5
[ROCm/clr commit: 5330679473]
The existing workgroup calculation logic for GWS initialization is
incorrect. It tries to add together workgroups across dimensions,
leading to major under-count in 2D and 3D kernels. An (x,y,z) kernel
uses x * y * z blocks, not x + y + z.
In addition, the previous logic was incorrect for the case of launching
a single-threaded kernel. It calculated 0 workgroups, leading to
initializing GWS to -1.
Change-Id: I1bb20a0d5b6e0cc10ac55901c28d8f93aac61c09
[ROCm/clr commit: 54d1d69c0a]
- The logic will trace compute, sdma read/write operations and
apply signals when necessary
- ROC_CPU_WAIT_FOR_SIGNAL, ROC_SYSTEM_SCOPE_SIGNAL
and ROC_SKIP_COPY_SYNC were added to control the tracking
Change-Id: I9e8e6174c63bf7784f7ab00964e2918c8667d364
[ROCm/clr commit: dbc7abaecf]
- ROCR fails the call for some reason, then the signal will
become invalid and can hang on a wait. The logic will reset the
active signal in such cases
Change-Id: Ia131420200f1bbd7c9a162b8f1b06db8cecf41c6
[ROCm/clr commit: ce2e5eba6b]
- There is a performance regression with a HW wait for HSA signal
on ROCr async operation. For now move the logic back to CPU wait.
- Fix profiling issue with multiple HSA signal per single timestamp
object. Some copies require multiple ROCR calls and if profiling is
required, then the execution time is derived from all used signals.
Change-Id: Id003e4abb8c2de378eedc152a7e389500fc6f4ce
[ROCm/clr commit: 5a8946190a]
Remove targetId_, gfxipMajor_, gfxipMinor_ and gfxipStepping_ from
device::Info as they are now available in device::Isa.
Change-Id: I381b1d4798ebf50655740e004a01ac7f86dbf668
[ROCm/clr commit: c2308216dd]
Jason Tang
Vladislav Sytchenko
kjayapra-amd
German Andryeyev
Ravi C Akkenapally
Tao Sang
Alex Xie
Payam
Rahul Garg
cjatin
Joseph Greathouse
Saleel Kudchadker
Tony Tye
Jason Tang