Commit Graph

463 Commits

Author SHA1 Message Date
GunaShekar, Ajay ed903e8889 SWDEV-543366 - Bump PAL_CLIENT_INTERFACE_MAJOR_VERSION 916 --> 932 (#725)
Co-authored-by: Lin, Qun <Quentin.Lin@amd.com>
Co-authored-by: Lin,Qun <qlin@amd.com>
2025-08-08 08:45:42 -07:00
Xie, Pengda cd46294b31 SWDEV-520384 - Improve Fat Binary loading latency (#390)
Init and fini kernel needs to be launched when we load and unload code object. Avoid looping through all kernels within a code object just to run the init and fini kernels. Compiler currently only generates 1 init and fini kernel.
2025-08-05 14:02:05 -07:00
Xie, Jiabao(Jimbo) a5d932f160 SWDEV-460151 - add gfx1201 to amd-staging clr (#183)
* SWDEV-460151 - add gfx1201 to amd-staging clr

* SWDEV-460151 - removed pal macro

---------

Co-authored-by: Jimbo Xie <jiabaxie@amd.com>
2025-07-11 08:51:47 -07:00
Sang, Tao 397f303d97 SWDEV-508776 - support VGPRs validation (#274)
Clarify some VGPRs terms description.
Fix some wrong query logics of availableVGPRs_ and
availableRegistersPerCU_ in device info.
Add hipDeviceAttributeMaxAvailableVgprsPerThread
attribute query.
Remove hardcoding of following
 info_.vgprAllocGranularity_
 info_.vgprsPerSimd_
2025-07-09 10:46:52 -04:00
Lin, Qun b584fc8cd1 SWDEV-508869 - Replace asicRevision with gfxip triple in paldevice (#601)
asicRevision is not unique in pal path now, use gfxip triple to match isa is more straight forward in pal path.
2025-06-27 10:09:21 +08:00
Lin, Qun 9699cc3864 SWDEV-508869 - Fix Linux build error for HIP on PAL (#176) 2025-06-27 07:51:22 +08:00
Assiouras, Ioannis f7482ef0a6 SWDEV-529449 - Bug fix when retrieving a memobj from the IPC mem handle 2025-05-13 19:18:22 +01:00
Andryeyev, German da198ac5b2 SWDEV-531678 - Remove split path from the dispatch (#283)
The split path for blit kernels are no longer necessary, since the new blit kernels
don't use the copy size as the global workload
2025-05-12 12:50:32 -04:00
Patel, Jaydeepkumar 6858b0fca1 SWDEV-521135 - Make common way to set/parse UUID bytes from PAL props. (#63) 2025-05-12 17:00:30 +05:30
Six, Lancelot c35e9643ec SWDEV-517078: Fix gfx11 trap handler (#212)
Fix incorrect edits done when porting the 2nd level trap handler from
the hsa-runtime.

Change-Id: I7bc5160be47b8f669efe05c4d194bc3c47fc0661
2025-05-11 01:12:28 +01:00
Xie, AlexBin faac50c77a SWDEV-528860 - reserve some memory in visible frame buffer (#251) 2025-05-09 20:08:23 -04:00
Assiouras, Ioannis 9d6a0d1a4d SWDEV-521011 - Fix alignment in PalResource::CreateSvm 2025-05-01 02:22:49 +01:00
Andryeyev, German 84a4f293f4 SWDEV-526836 - add PipelineStageBlt flag (#229)
CP sync requires PipelineStageBlt flag.
2025-04-30 14:27:41 -04:00
Jiang, Julia eb62fe9f62 SWDEV-522634 - Fix device properties in hipInfo (#203) 2025-04-29 11:29:47 -04:00
GunaShekar, Ajay 99ef573399 SWDEV-523028 - print PAL failure return values in logs (#81)
* print PAL failure return values in logs
* dump kernel info incase of PAL failure
2025-04-29 11:23:43 +05:30
Critchley, Paul 7e9d5eab7c SWDEV-523611 - [Tools][OCL] OpenCL fails to capture with PalTrace (#198)
Finalize DevDriver initialization after device creation
2025-04-28 08:02:34 -07:00
Li, Todd tiantuo 95cdc83eaf SWDEV-511055 - fix HIP PAL memory allocation workaround for APU (#40) 2025-04-24 15:07:16 -07:00
Critchley, Paul 4f2a4b12a9 SWDEV-527731 - [Ubertrace] OpenCL driver reports wrong Instrumentation API Version (#211) 2025-04-24 14:06:17 -07:00
Xie, Jiabao(Jimbo) 9a8c9e70b2 SWDEV-441487 - add gfx1150/1 support to amd-staging clr (#182)
Co-authored-by: Jimbo Xie <jiabaxie@amd.com>
2025-04-23 20:43:03 +05:30
Andryeyev, German 3fd7650fe3 SWDEV-459758 - Pass workgroup size explicitly (#185)
It's easier for compiler to move explicit kernel arguments into user SGPRs
2025-04-15 15:22:15 -04:00
Andryeyev, German f6c804edc0 SWDEV-526836 - Switch PAL backend to CmdReleaseThenAcquire() (#175) 2025-04-15 11:49:53 -04:00
Six, Lancelot 7b72c1b786 SWDEV-517078 - Update 2nd level trap handlers (#148)
* SWDEV-517078 - Maintain the trap handler ABI version in CLR

The trap handler ABI version is communicated to the debugger using
the r_version field in the r_debug structure.  This structure is
an external dependency, which makes it complicated to keep the trap
handler source (in CRL) and the ABI version number (external dependency)
in sync.

This patch proposes to patch the trap handler ABI version number in
_amdgpu_r_debug before communicating it to the debugger.

We can't directly include sc's executable.hpp file in CRL as it relies
on conflicting definition of ELF related types, so instead we need to
rely on a-priori knowledge on the r_debug structure.  Fortunately, this
structure is part of a stable ABI, so its layout is guaranteed to be
kept stable.

Update the 2nd level trap handler to follow updates from the
ROCr-runtime.  The trap handlers are stripped from parts dedicated to
architectures unsupported by CLR.

Bump the r_debug.r_version to track the ABI changes in the trap handler.
2025-04-11 18:59:54 +01:00
Andryeyev, German 94cd9bc4f7 SWDEV-525725 - Enable resource cache for SVM (#156)
- Make sure reserved_va_ updated before svmPtr overwrite
2025-04-10 10:54:28 -04:00
Patel, Jaydeepkumar 9e7248aa36 SWDEV-521011 - Allow max stack size as per ISA. (#73) 2025-04-08 10:15:38 +05:30
Andryeyev, German e974f7fde1 SWDEV-497841 - Add VmHeapArray support (#76)
Add VmHeapArray class to reduce the pressure on VA reservation, since
multiple memory pools can be active at the same time.
2025-04-03 21:04:18 +05:30
Patel, Jaydeepkumar b5c9cbc236 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29) 2025-04-02 16:33:29 +05:30
GunaShekar, Ajay 686dd56a4e SWDEV-523853 - Use RecordRenderOps instead of RecordRenderOp (#97) 2025-03-26 09:28:40 +05:30
agunashe f1b8ee7b7f SWDEV-513810 - APU: memory allocations threshold 0.75-->1
Needs further debugging but for now can test the change

Need to verify if this fixes all the below issues-
SWDEV-512754, SWDEV-511675, SWDEV-511055, SWDEV-504085, SWDEV-499503
Also verify original issues
SWDEV-471863, SWDEV-490991

Change-Id: Ic845f851de1b98e8ed9aa0f07afddec3858119e9
2025-03-11 05:30:43 -04:00
Pengda Xie b02b1858c0 SWDEV-497619 - Ensure suballocSize is integer multiple of 4096
Change-Id: Iefc452d73566f58cfb63391a68c836f30d77dd6c
2025-03-07 15:36:57 -05:00
Branislav Brzak c2d1776ebd SWDEV-516564 - SWDEV-512817 - Remove mentions of gfx940 and gfx941
Change-Id: Ia069fcb9c6948c3fc9a00961593c9dcc59609375
2025-03-05 04:26:07 -05:00
Julia Jiang b7eaec76fc SWDEV-513294 - fix regression on SVM sub-test failure in Conformance
Change-Id: Ic2449dd34a9cd2b623d5f8fbe89fd042566a56e3
2025-02-20 15:40:23 -05:00
German Andryeyev 296dce5570 SWDEV-497841 - Add virtual memory heap
Add initial implementation of virtual memory heap with
dynamic virtual memory mapping support for memory pools.
DEBUG_HIP_MEM_POOL_VMHEAP controls the new method.

Change-Id: I8dc5be2e0f34ab472f1800f43bb6243639a5e500
2025-02-20 10:55:49 -05:00
German Andryeyev 63cf3057ba SWDEV-497619 - Allocate extra space in CB
Compute doesn't support IB chaining, but RGP may collect
perf counters, which require more space in CB.
Increase CB size if RGP is enabled.

Change-Id: Iaa0a620ead8541a679b0dfe5e5711af5afdba545
2025-02-20 10:40:09 -05:00
agunashe ea804e16f8 SWDEV-507967 - Deprecate gfx9, gfx8, gfx7 on Windows
PAL_CLIENT_INTERFACE_MAJOR_VERSION from 872 --> 910

Change-Id: I03dfa2924ccdae4c2f13f09d5f34ee58298e1343
2025-02-17 02:59:41 -05:00
Aidan Belton-Schure 179801a750 SWDEV-508279 - Improve HIP event profiling
There are 2 functional changes to this patch:
* Use GPU timing for internal markers for HIP.
* Measure CPU time closer to GPU timer, to reduce delta between GPU/CPU timestamp measurements.

There are some smaller non-functional updates:
* waifForFence -> waitForFence typo
* Remove unused drmProfiling

Change-Id: I4c5fa600a842ab60e454888779edcac8449a902a
2025-02-13 04:15:40 -05:00
kjayapra-amd cf6aabb823 SWDEV-511672 - Special case the Remote USWC memory usage for HIP, if the alloc size is large.
Change-Id: I524c1402b249cedfd58b56f494caa2ac057e1623
2025-02-11 06:42:18 -05:00
taosang2 32daa8f384 SWDEV-501963 - Add missing codes for gfx950
Cherry-pick https://gerrit-git.amd.com/c/compute/ec/clr/+/1162997

Change-Id: I6b3c6bf55c61cffd43cd6f17b75998f751b75723
2025-01-31 14:34:49 -05:00
Aidan Belton-Schure 451b0ce768 SWDEV-482851 - Do not release last suballocator chunk
Change-Id: Ib28dc9df68e454ee0c0c699c1ff17588fd55f802
2025-01-13 10:14:40 -05:00
Daniel Livingston 541c449ce2 SWDEV-489003 - [Ubertrace] OCL/HIP profiles are missing event instrumentation
Adds UberTrace support for pre-dispatch markers and barrier begin/end markers.

Moves shared definitions out of palgpuopen.hpp into shared header
palcapturemgr.hpp.

Change-Id: I9f464c689e7ff12c54eca043fc1ad65e1836a64f
2025-01-10 11:28:52 -05:00
Jatin Jaikishan Chaudhary 446ed661a0 Revert "SWDEV-505971 - change setArgument arg from uint32_t to uint64_t"
This reverts commit a6f2a2c2af.

Reason for revert: There needs to be memcpy size change

Change-Id: If4f51769731e54743ac705b19b4f81b2d5925d5a
2025-01-06 18:03:23 -05:00
Jatin Chaudhary a6f2a2c2af SWDEV-505971 - change setArgument arg from uint32_t to uint64_t
We are passing this arg as an address, and memcpy complains about
overreading (8 bytes instead of 4).

Change-Id: Ica9207f6c5f6056a4bfc968280c76e779ded13ae
2025-01-06 08:16:59 -05:00
taosang2 d82d6a78cf SWDEV-479958 - Support different address mode
Support different address modes in X, Y, Z directions

Change-Id: If1db5a8af33c92dd14b48968c3e8eceb97daea6c
2024-12-23 16:39:54 -05:00
Sourabh Betigeri 03dbcd8ca7 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8
2024-12-12 19:29:24 -05:00
Gerardo Hernandez 03e4057fce SWDEV-496392 - Remove references to ASIC Polaris22 in pal::Settings and pal::Device (it is being retired)
Change-Id: I6318abf3e46ed250d087a3d2266d2ae3d4c8c000
2024-12-10 06:01:32 -05:00
Ajay 7d763fb803 SWDEV-498474 - APU: when total allocated is greater than 75% of invisible
Only when memory type is Local and the invisible memory is +ve
Should also fix SWDEV-490991

Change-Id: I78a4925a234ba90c63909bde5b7dc217568b4de3
2024-12-09 12:06:57 -05:00
Sourabh Betigeri 2ca644cf22 Revert "SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs"
This reverts commit bd5d8e9baf.

Reason for revert: hipInfo fails on windows. Updating llvm amd-mainline-closed

Change-Id: I57e1fa1945188b0bc0a799c4f3d540f2b7713003
2024-12-02 16:46:12 -05:00
Sourabh Betigeri bd5d8e9baf SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I449ffca44bbb04d13348d112e896d603c70fd485
2024-11-30 17:54:32 -05:00
Anusha GodavarthySurya 06e6561eb5 SWDEV-489084 - Avoid using queue colliding with the graph launch stream
Change-Id: I3ecaf8836c8e0883441275139041c702aba0937e
2024-11-29 08:15:58 -05:00
Ioannis Assiouras 2cc9f59774 SWDEV-494409 - Fixed segfault caused by aligned_free called on unaligned memory
Change-Id: I8ddea5c309b568db25c92789bf71be341d19c3ba
2024-11-22 03:08:04 +00:00
Jaydeep Patel 4aa52155ee SWDEV-491149 - OCL does not need to update scratch as it can't update stack size using API unlike hipDeviceSetLimit.
for HIP, Update should be only if compiler notifies use of stack size.

Change-Id: Ic781bcac6fcf586da39ec4aafd4809da3652ede3
2024-11-01 01:05:07 -04:00