550547f404
Initial exception support for signals.
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Also separate signal ABI block allocations from the runtime interface object.
Change-Id: If16763338db664f29163a1348f8f4c38cf0597b2
[ROCm/ROCR-Runtime commit: 2732b18092
2017-08-11 18:41:34 -05:00
ce72ce0c92
adding aqlprofile member to HsaApiTable
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Change-Id: Id674186dfa2e83295a51f770ccc0400f1cb51a98
[ROCm/ROCR-Runtime commit: 287afd3a52
2017-08-09 16:09:39 -05:00
200067f1be
Adding HSA_API macro to the API method declarations to be consistent with other HSA header files, TCS removing
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Change-Id: Ic217d3b2bdbb22d3600c5ecaacb7ab53bf26096a
[ROCm/ROCR-Runtime commit: 4824a2db0b
2017-08-08 10:46:12 -04:00
c0c32288ac
aqlprofile block list, explicit numbers assigned, IA removed
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Change-Id: I9f9358f8e03e13eb81845de2e33dd5f3da27811a
[ROCm/ROCR-Runtime commit: 47322942b3
2017-08-03 11:39:21 -04:00
d224dc274f
aql-profile api: reducing blocks list to compute only and new gfx9 blocks
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Change-Id: Ib506b82ea407afec4f5d4bcad755d4d57b92e34b
[ROCm/ROCR-Runtime commit: c66f68041c
2017-08-02 12:21:24 -04:00
ea88523fc7
Fix compilation issue reported with GLIBC 2.12 (RHEL 6.9)
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Change-Id: I770b72ba1d61475a76aa72d0c52ebfb380db6019
[ROCm/ROCR-Runtime commit: 9ee0108e58
2017-07-28 11:11:01 -04:00
b6d71a8fe6
hsa_ven_amd_aqlprofile.h: include <hsa.h> fix
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Change-Id: Idfd2fdde112d502d4b4a3365512ec601f7e56a5b
[ROCm/ROCR-Runtime commit: ab67b8511b
2017-07-12 15:43:58 -05:00
dd8804d7ad
Remove use of anonymous member in C builds.
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Tools/CodeXL will retain older versions of structs if them need them.
Change-Id: I568d7b445778dd575ef71000b4b839300572288e
[ROCm/ROCR-Runtime commit: a0a3587345
2017-07-12 16:40:00 -04:00
41ab59b1e7
Fix queue interception in tools.
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1. Correct amd::AqlQueue::ExecutePM4 to support interception.
2. Minor fixes to AqlPacket and SoftCP.
3. Minimal change to disable interception of runtime internal queues.
Change-Id: I103fece2ebf9a188d27f01e61221c737405d7253
[ROCm/ROCR-Runtime commit: bc0bd00746
2017-07-12 16:39:43 -04:00
17d0e450cb
Correct handling of slow clocks under linux.
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Change-Id: I9a1b08d5457caa6739220603bbd37b00febc64d7
[ROCm/ROCR-Runtime commit: 29b5b5c029
2017-07-12 12:49:49 -04:00
19f96afee1
Properly order signal copy agent tagging with copy operation.
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Change-Id: Ic428c958551279fbea1b2449afba930b82804ede
[ROCm/ROCR-Runtime commit: 3e50adc7ce
2017-07-11 13:10:00 -04:00
cafbebc2a5
Decrement hsa_init ref counter when init fails.
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Change-Id: If9376344d4b559e601932d070731132c8450104e
[ROCm/ROCR-Runtime commit: c9f0427cb0
2017-07-07 21:21:03 -05:00
ce82829fc1
hsa-runtime integration
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Change-Id: I48968966ffe164218ebff88d0e3a1268e96bf1dd
[ROCm/ROCR-Runtime commit: 4174f07fd1
2017-07-05 10:55:30 -04:00
1351f204d4
Support Perf Cntrs (PMC) and Thread Trace (SQTT) over AQL queues
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Change-Id: I716b722895d90b46914c31377e791ad602acecc1
[ROCm/ROCR-Runtime commit: 08e0bca567
2017-06-15 12:58:31 -04:00
415027b89f
Revert "Implement memory fault analysis through context save area"
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This reverts commit 498f3a71885b4df54b10
2017-06-14 14:21:53 -04:00
498f3a7188
Implement memory fault analysis through context save area
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When a fatal memory fault occurs the scheduler context-saves all queues
in the process and notifies the runtime through the memory event. The
saved state contains all GPR/LDS data at the moment of the fault.
Retrieve this state and present it to the user if HSA_DEBUG_FAULT is set
to "analyze" and the wavefront caused the fault. If amdgcn-capable objdump
is in the PATH invoke this to disassemble code around the PC.
Queue lifetime is now managed by the runtime to allow querying the
context save state for all active queues.
Change-Id: I6fee662fad1c4f9aa125bf5c53d7d0ea1ab32f95
[ROCm/ROCR-Runtime commit: 75c9506f9d
2017-06-13 23:12:28 -04:00
79a238eb78
Update hsa_isa_t entries
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- Add 7.0.2 (consumer hawaii)
- Add 9.0.1 (gfx900 with xnack)
- Add 9.0.2
- Add 9.0.3
Change-Id: I6a07797027c4eaf47038837c5ae51e05b2aba0e4
[ROCm/ROCR-Runtime commit: d98e99949a
2017-06-12 14:34:11 -04:00
f5c06c5911
The fallback path covers not just ARM64, need this for Power as well.
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Change-Id: I7bbf76f77bd3ac47a0a0987c1e880e23834588e2
[ROCm/ROCR-Runtime commit: a0957bc679
2017-06-07 14:45:29 -05:00
dfbad5fa07
Enable SDMA on gfx9, disable on gfx8
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gfx9 has passed qualification. gfx8 stability is under investigation.
Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834
[ROCm/ROCR-Runtime commit: 5db53ceda1
2017-06-02 15:14:14 -05:00
42bb22d0cc
Add preferred agent info to pointer info struct.
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Lookup blit agent via pointer info in memory_fill.
Change-Id: I02feaf68bb9726858e8cb0ede6bc5f2b3707f5af
[ROCm/ROCR-Runtime commit: c3e2a88ade
2017-05-31 05:16:05 -04:00
754935ee65
Unmap GPUs when allow_access removes them from system pools.
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Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77
[ROCm/ROCR-Runtime commit: e38ff18990
2017-05-17 20:58:05 -04:00
768644ba7a
Purge warning in amd_hsa_code.cpp
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Change-Id: Iaa5d7af183af5e8c069365a1f0410365b46d53d5
[ROCm/ROCR-Runtime commit: a777413400
2017-05-08 19:39:49 -04:00
b39fea499a
Change rpm preinstall script to post install
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Change-Id: Iccc04902699bf0ba8b5269e1129b72cf69ef7f00
[ROCm/ROCR-Runtime commit: 001d43ce56
2017-05-07 14:02:54 -05:00
ef38e563ba
On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset.
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Also fix permission in couple files.
Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a
[ROCm/ROCR-Runtime commit: 8aa19388a9
2017-04-18 22:37:56 -05:00
2c71b68fdb
Fix gfx9 trap handler to retrieve correct return address
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The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.
Clean up later when LLVM assembly build is introduced to the runtime.
Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178
[ROCm/ROCR-Runtime commit: f0a1c7c4c6
2017-04-05 17:33:49 -05:00
9734bc078a
Remove comments, no functional change.
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Change-Id: I923c037803a847352c2c50d9d47460cb0f01f22c
[ROCm/ROCR-Runtime commit: 8a5ff78be6
2017-03-28 18:22:49 -05:00
941c065513
Support async. queue errors and dynamic scratch without KFD events.
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Change-Id: I4e9e7a37aa7b9c96b28ce79f562760283e02b1e0
[ROCm/ROCR-Runtime commit: 7dfeee5074
2017-03-28 19:18:18 -04:00
5288e46340
Refactor signal_wait timing code and respect small timeouts.
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Optimized for Gromacs and SHOC.
Change-Id: Ib674710268b41003259711a0e42d3e770a82018d
[ROCm/ROCR-Runtime commit: c4544906b9
2017-03-23 23:55:48 -05:00
4d121c2b97
We should be using the "used" gcc attribute.
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Change-Id: I1589273740ae66e8d7d8186a88e2c411a2e0425c
See: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#Common-Variable-Attributes
[ROCm/ROCR-Runtime commit: ba3f1cb476
2017-03-20 11:57:39 -04:00
d4a8e87a35
Fix the comment to specify the right type of allocation required.
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Change-Id: I8bda8d64010d466d6ca5e779d2042cca3f494ecf
[ROCm/ROCR-Runtime commit: 6c750f479d
2017-03-20 11:56:54 -04:00
d775242246
Disable SDMA only on gfx900 until it is validated.
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Change-Id: Ib960be3ca6d3fc4b664ba047243964b8c7a33f24
[ROCm/ROCR-Runtime commit: 7c6cde1871
2017-03-20 11:55:22 -04:00
d0a8e27a35
[Loader] Fix memory allocations for code objects that
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are larger than swap space available
Change-Id: I321487f96fe0a18998301a9058430c19427e5a94
[ROCm/ROCR-Runtime commit: a08d760c70
2017-03-11 00:57:25 -05:00
b7256bae4e
Support async error code 256, invalid vendor specific packet.
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Change-Id: I491f34def4c3d54403864fa42670f7847a6141cc
[ROCm/ROCR-Runtime commit: 5f50e97d18
2017-03-10 16:20:27 -05:00
3ca460d72f
Relax signal assertion.
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Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list. This list is used
for optimized signal type selection.
Change-Id: I5879f8f822d01af504ab913482b2532feb00be98
[ROCm/ROCR-Runtime commit: 2824786b3b
2017-03-10 16:05:34 -05:00
d759209584
Add inc/ to some include
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Change-Id: Id027b015c8785a132835a422d97a23b0bbce208a
[ROCm/ROCR-Runtime commit: 05d587ef79
2017-03-09 19:45:01 -08:00
c02e8c67df
Adjust signal sleep to reflect null kernel latency. Performance tested on Gromacs.
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Change-Id: I3851148ee8544b15d840f2c26ca73a83f8d0df2e
[ROCm/ROCR-Runtime commit: 426d41e27c
2017-03-09 15:20:53 -05:00
ccbb47d79d
Update readme regarding CMAKE_PREFIX_PATH.
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Change-Id: I322789f38b1984b2527554c10cb0f3be886d3e91
[ROCm/ROCR-Runtime commit: 470750cc3c
2017-02-20 14:33:53 -06:00
212d7c3f8f
Fixes to HSA CMakeList.txt files
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Change-Id: Idd176d24dfd22bd9a6a8860ab035fd5d1aca756d
[ROCm/ROCR-Runtime commit: 900f272622
2017-02-15 08:26:30 -06:00
fca0ec886c
Fix TeamCity builds using utils.cmake.
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Change-Id: Id15a911dad06643d9457cc4d8c907fc5796772ee
[ROCm/ROCR-Runtime commit: b7e06b471c
2017-02-14 15:36:21 -06:00
f851f5adf6
Modify hsa CMakeList.txt file to use PREFIX_PATH and git describe versioning.
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Change-Id: I08668df07725369ecf8a2f35e74dd7d64c8ca94b
[ROCm/ROCR-Runtime commit: 73e942cd8a
2017-02-14 08:39:16 -05:00
2a071e1456
Bring loader in sync with stg/sc
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Change-Id: Iccce07b8fa03d37c4267a2a9bd343e6614dc43e7
[ROCm/ROCR-Runtime commit: 9887c26113
2017-02-10 11:21:15 -05:00
16d8e2caa9
Implement code cache invalidation for Gfx9
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When a new enough microcode build is running use a vendor AQL packet
to submit the PM4 IB.
Change-Id: Icd3e2b322c418477420ba4a29f4455ce340ef0d2
[ROCm/ROCR-Runtime commit: 4d62b9482a
2017-02-09 14:15:21 -05:00
de0fa51022
Fix Api table copy operation and tools version checking.
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Change-Id: Ia76d16f3ea6d0abb931813f90bc3bc2119da5999
[ROCm/ROCR-Runtime commit: 505d722b7d
2017-02-07 14:26:20 -05:00
d984194fa5
Use fixed size type for queue type arguments.
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Change-Id: I81b605c9cc9b18bcef043a4f0292212241ce5987
[ROCm/ROCR-Runtime commit: bc43f97964
2017-02-07 01:22:30 -05:00
dce2a864ba
Fix Gfx9 write pointer setup
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Should point directly to amd_queue_t.write_dispatch_id. Only noticeable
with HWS enabled which is not yet stable.
Change-Id: I169906d45225379a3ca2729ff04d298fdbb9a9fb
[ROCm/ROCR-Runtime commit: 28f51d5808
2017-02-06 14:06:12 -05:00
7b45ebfe7f
Add support for ARM
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- Build system fixes
- No user-mode high-precision timer by default, use clock_gettime
- Use C11 aligned_alloc pending C++17 std::aligned_alloc
Change-Id: I268365bdfd11d1e817a89584b9e086ee5b86e1dc
[ROCm/ROCR-Runtime commit: 9e575ea96a
2017-01-31 16:43:49 -08:00
7f38f6e297
Add support for gfx900
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- Route AQL doorbell directly to HW doorbell
- Reuse precompiled Gfx8 shaders on Gfx9 (ISA is compatible)
- Add a warning for unimplemented code cache invalidation
Change-Id: I92096584a1404e35779c96ae6bdc3e0e7fd04721
[ROCm/ROCR-Runtime commit: 7e0a5f9c00
2017-01-30 16:36:28 -06:00
2755a4e0a7
Remove old names from API table interfaces.
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Change-Id: I41ca38b596e1dac85e871f583e3ffe7078b790e7
[ROCm/ROCR-Runtime commit: 796d31d94d
2017-01-27 17:45:26 -06:00
2217e709da
Adding the new APIs to the .def files and fixed a couple of things
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Change-Id: I247a60b8cdbd4acfed72fb6d78ac7faf69d8a556
[ROCm/ROCR-Runtime commit: 9ae1e15750
2017-01-27 16:51:50 -05:00
22ffe11f5c
Implement SDMA path for Gfx9
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Gfx9 requires monotonic write pointer and doorbell.
Cound fields are 1-based compared with 0-based pre-Gfx9.
- Restructure implementation to use monotonic ring indices
- Remove redundant submission size checks (handled by AcquireWriteAddress)
- Unify copy/fill per-command limit (documentation is unclear)
Change-Id: I57c1675221d2e63aa319fee700d9951671e1bd65
[ROCm/ROCR-Runtime commit: 1cd46afe6d
2017-01-26 13:11:21 -05:00
Sean Keely
Evgeny
hthangir
Ramesh Errabolu
Kenny Ho
Jay Cornwall
Konstantin Zhuravlyov
James Edwards
Christophe Paquot
Konstantin Zhuravlyov