Moved the bit_rate and max_bandwidth back into links in the
amdsmi_link_metrics_t struct as this change was impacting
other teams. Modified the C and python API's, wrapper, and
CLI accordingly.
Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
Moved the bit_rate and max_bandwidth back into links in the
amdsmi_link_metrics_t struct as this change was impacting
other teams. Modified the C and python API's, wrapper, and
CLI accordingly.
Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
[ROCm/amdsmi commit: 645c313f00]
* Add gpu metrics caching defaulted to 100ms
* AMDSMI_GPU_METRICS_CACHE_MS is used to set the caching rate limits
---------
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
* Add gpu metrics caching defaulted to 100ms
* AMDSMI_GPU_METRICS_CACHE_MS is used to set the caching rate limits
---------
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
[ROCm/amdsmi commit: 42096c1398]
add hip table version to 13, API_ID_LAST is not changed from version=12 since no new struct has been added.
Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>
[ROCm/rocprofiler-sdk commit: d2393c97f8]
add hip table version to 13, API_ID_LAST is not changed from version=12 since no new struct has been added.
Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>
Cache packet creation in all cases to reduce the number of allocations/
destruction operations made down to KFD. There is a bug that we
encounter after a period of runtime in KFD where allocations fail to be
visable to the GPU (suspect this is a FW issue, similar to other FW
issues they have had along the same lines). This sidesteps that issue in
rocprof (and likely should be done regardless)
Co-authored-by: Benjamin Welton <bewelton@amd.com>
[ROCm/rocprofiler-sdk commit: 7e3ea0c58e]
Cache packet creation in all cases to reduce the number of allocations/
destruction operations made down to KFD. There is a bug that we
encounter after a period of runtime in KFD where allocations fail to be
visable to the GPU (suspect this is a FW issue, similar to other FW
issues they have had along the same lines). This sidesteps that issue in
rocprof (and likely should be done regardless)
Co-authored-by: Benjamin Welton <bewelton@amd.com>
A hang would occur when a memory error occurs because the
AQLQueue destructor would be waiting for a signal that
wouldn't come. This change allows it to break out of the
wait loop.
A hang would occur when a memory error occurs because the
AQLQueue destructor would be waiting for a signal that
wouldn't come. This change allows it to break out of the
wait loop.
[ROCm/ROCR-Runtime commit: c065d9a7e2]
Replace ROCm SMI (rsmi) API calls with AMDSMI (amdsmi) API calls
in rocrtst.
Signed-off-by: Alysa Liu <Alysa.Liu@amd.com>
[ROCm/ROCR-Runtime commit: 4fab4d70e6]
Move the wallclock frequency query from GpuAgent to driver layer to improve
code organization and support multiple driver types. This change:
1. Add GetWallclockFrequency API to KFD/XDNA drivers
2. Move libdrm GPU info query from GpuAgent to driver implementation
3. Update GpuAgent to use the new driver API
Signed-off-by: Honglei Huang <Honglei1.Huang@amd.com>
Move the wallclock frequency query from GpuAgent to driver layer to improve
code organization and support multiple driver types. This change:
1. Add GetWallclockFrequency API to KFD/XDNA drivers
2. Move libdrm GPU info query from GpuAgent to driver implementation
3. Update GpuAgent to use the new driver API
Signed-off-by: Honglei Huang <Honglei1.Huang@amd.com>
[ROCm/ROCR-Runtime commit: 412e386b50]
- Implemented GetTileConfig in KfdDriver to retrieve tile configuration for
a specific node.
- Added a stub implementation of GetTileConfig in XdnaDriver.
- Updated driver.h to include a virtual GetTileConfig method.
- Extended hsa_internal.h with a new hsa_get_tile_config function.
- Integrated hsa_get_tile_config into hsa.cpp to call the driver-specific
implementation.
- Updated driver headers to declare the new GetTileConfig method.
Signed-off-by: Honglei Huang <Honglei1.Huang@amd.com>