Commit Graph

14 Commits

Author SHA1 Message Date
systems-assistant[bot] be2e7314fa SWDEV-532473 - Add Pcie atomic support check to failing tests (#575)
Co-authored-by: Rahul Manocha <rmanocha@amd.com>
2025-09-09 09:01:25 -07:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Sang, Tao 438882ceb7 SWDEV-514141 - Fix zero clock rate issues (#4)
1.Remove clock functions from some tests that don't need them.
2.In some memory pool tests and coherency tests, timer-based kernel
delay isn't reliable, use pinned host based notification instead.
3.Add CHECK_PCIE_ATOMICS_SUPPORT before some tests.
4.catch/unit/memory/hipMemoryAllocateCoherent.cc is removed
as it is useless and originally excluded in building.
5.Some tests can still pass even if clock rate =0, thus they
  will be kept as is.
6.Some logic and format improvement in some tests.

Change-Id: I6b3c6bf54c61cffd45cd6f17c75998f751b75725

[ROCm/hip-tests commit: ec8ff45a1d]
2025-06-11 21:11:25 +05:30
Jaydeep Patel 569616832a SWDEV-496544 - Memory needs visibility system wide as CPU and GPU both needs to see updated value by each other.
Change-Id: Ia80e69455aeb06b9281f75313ba39b621d6929c5


[ROCm/hip-tests commit: 5244a426c7]
2025-01-24 13:28:17 -05:00
Vladana Stojiljkovic e057b9e471 SWDEV-450735 - Add compiler option for using clock64
Change-Id: I9efed88d691ee1b2b4465286b3340b820f7bf627


[ROCm/hip-tests commit: 5b67a2a4a0]
2024-08-29 10:26:11 +02:00
Todd tiantuo Li aa470f00aa SWDEV-333557 - add catch multiproc to Windows build
Change-Id: Ib1b976c9071527e508703496db234f2623a2cf84


[ROCm/hip-tests commit: 050370661e]
2023-11-06 08:25:50 -05:00
ROCm CI Service Account d3b771c91d SWDEV-385161 - Deprecate usage of env vars in HIP samples and tests (#363)
* SWDEV-385161 - Deprecate usage of env vars in HIP samples and tests env vars such as HIP_PATH, ROCM_PATH, HIP_COMPILER, HIP_RUNTIME, HSA_PATH etc are removed.

Change-Id: I280e20b291cfb14675846aae72d97fa5b3ad567d

[ROCm/hip-tests commit: 34976df246]
2023-08-14 12:06:14 +05:30
ROCm CI Service Account 6647d396b2 SWDEV-403960 - [catch2][dtest] Enable xnack+ check condition (#364)
Change-Id: I9627d75d0d3258cf261c8e4bfe6c7c3c35c8f9c1

[ROCm/hip-tests commit: 042234e0b2]
2023-07-11 11:37:23 -07:00
ROCm CI Service Account 011b44b482 SWDEV-393910 - Port gfx940 changes to mainline. (#321)
Change-Id: I77e70bcb15fbd38b1c79c1f68b7e483b2b3e0daf

[ROCm/hip-tests commit: d33ccb3569]
2023-06-29 08:57:51 +05:30
ROCm CI Service Account d8b7cb28ff SWDEV-337452 - Changing Clock64 to WallClock64 in tests for gfx11. (#78)
Change-Id: I484fe9ff7cd56c70a37a3ac5a4a55812f8557259


[ROCm/hip-tests commit: 87fac87657]
2023-01-06 15:05:21 -08:00
ROCm CI Service Account a33bf1e10d SWDEV-308368 - Fix coherent test bugs (#2985)
1. Remove hipDeviceAttributePageableMemoryAccess checking as it is used to check xnack+ rather than fine-grained synchronization.
Note: hipHostMalloc() will alloc memory with fine-grained access and atomic by default when env HIP_HOST_COHERENT=1. For more information, see hip_programming_guide.
2. Fix some other bugs.

Change-Id: Ieaaed1b15b4d258193d834104b17d9f03a9e4781

[ROCm/hip-tests commit: 15593f343d]
2022-10-19 16:48:44 +05:30
ROCm CI Service Account 86f728efd2 SWDEV-329590 - Addresses coherency test failures on Navi21 (#2652)
- Tests using HSA_XNACK=1 restricted to MI200
- Added checks to verify HMM and Pageable memory access attributes to avoid failures

Change-Id: Ic0b107264378ce0c4f0aab770c941ae2b57342c2

[ROCm/hip-tests commit: fb25b090eb]
2022-05-17 11:31:19 +05:30
ROCm CI Service Account 0a584393c5 SWDEV-323849 - Fix for dtests failures (#2539)
Change-Id: Iffd78656d7f67b11d3eb6d1e7859bb6168b68a57

[ROCm/hip-tests commit: 7fa5b6ddfe]
2022-03-10 15:04:48 +05:30
lthakur cfb30bc703 SWDEV-293806 - Adding tests to check behvior related to fine and coarse grain (#2402)
Change-Id: Ia437adf138e6952ff42b6081c39da5bfaf931e53

[ROCm/hip-tests commit: 3fbea0cd5a]
2021-11-25 15:11:10 +05:30