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432 Melakukan

Penulis SHA1 Pesan Tanggal
Vladislav Sytchenko ffbf368f4c SWDEV-293519 - [PAL] Limit mgpu SVM logic only to mgpu cases
Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.

HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.

Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456
2021-08-22 23:56:08 -07:00
Aaron Liu c6574cb906 SWDEV-294027 - [Lnx][YC] Add Yellow Carp support
Only add Roc path and don't use Pal path.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I7117e2dc3c3ad4c8d563e9bbdc721f70ddba51fd
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 924695fb5e SWDEV-292021 - Fix Device Reset
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 6566361144 SWDEV-283981 - Revert "SWDEV-283981 - [PAL] Support hostcall SQ interrupt"
This reverts commit 9df70fa03ce60d47247eb0e8f278e1f8dbd33d6e.

Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.

Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 0a59c9c4c3 SWDEV-291787 - Fix Windows build
Change-Id: I1b97a1100e4c498f53aaad7157f21d0c5f8a130d
2021-08-22 23:56:08 -07:00
jujiang 84b971c7c1 SWDEV-291787 - Fix persistent direct map
Change-Id: Ic1507cc6d63e9ed574e8e169bce7bf56f4792c19
2021-08-22 23:56:08 -07:00
German Andryeyev 2babcfbdbb SWDEV-290384 - Enable active wait on CPU if HIP requested
Change-Id: Idea5adf7a4705cb999da6785e6229fe3200dce17
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 4589343c3e SWDEV-283981 - [PAL] Support hostcall SQ interrupt
Change-Id: Ic6f0ad384404712d5eeb1eaf600e231a8f8631f7
2021-08-22 23:56:08 -07:00
German Andryeyev c144383971 SWDEV-290384 - Disable HSA callback for any host wait
Change-Id: Ie876deb62859f5551f4ed69eb8187ac3fa35f42a
2021-08-22 23:56:08 -07:00
German Andryeyev ff15c0893e SWDEV-292018 - Switch to internal signals for markers
Add ref counting to ProfilingSignal class to track the last release.
If a signal was used in the marker, then don't reuse it,
but create a new one for internal usage.
Don't rely on HSA callback for the command status update if there
are no pending dispatches.

Change-Id: I19f14ed9d80acfe79993b343b2187635f8428a20
2021-08-22 23:56:07 -07:00
Sourabh Betigeri 6408b9b906 SWDEV-290685 - Relacing release fence instead of acquire for hipStreamWrite()
Change-Id: Ic2946b68c427d3e058948c0813863a27c21b903d
2021-08-22 23:56:07 -07:00
German Andryeyev e4dae85ade SWDEV-290495 - Add HSA_AMD_AGENT_INFO_SVM_DIRECT_HOST_ACCESS query
Change-Id: Ib18a53a9016eb5c5ffd51bf6835cba7299ec8421
2021-08-22 23:56:07 -07:00
Sourabh Betigeri e4ddb5e08a SWDEV-290685 - Dispatch a barrier packet with acquire system scope to ensure ordering before a hipStreamWrite()
Change-Id: I8853ad86a6634d55a98173ca3f79d93b85c08f85
2021-08-22 23:56:07 -07:00
Vladislav Sytchenko 6ff4839d76 SWDEV-273235 - Remove dependency on ADL
Currently ADL is only being included if we build HSAIL and not LC. The
only configuration that does this is Ellesmere on Linux.

As the appprofile logic doesn't do anything right now, it should be
safe to remove it.

Change-Id: I13ce8c27af08c25b95edcbfd2ee1ce447b0bfd39
2021-08-22 23:56:07 -07:00
agunashe d96481fb36 SWDEV-293742 - Update copyright end year VDI repo
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
Saleel Kudchadker cd21af757e SWDEV-260448 - Honor NUMACTL for Direct Dispatch
Setting AMD_CPU_AFFINITY=1 will keep Async Handler thread within the
bounds set by numactl.

Change-Id: Id01b30df5127d65c29ac072bf74a04986b7128de
2021-08-22 23:56:07 -07:00
German Andryeyev f4032401cf SWDEV-289378 - Avoid CPU TS overwrite if GPU TS is available
Change-Id: I444ec284669b6a6fff31182e213b47c562c90192
2021-08-22 23:56:07 -07:00
German Andryeyev 4fd506cfe1 SWDEV-289378 - Avoid CPU TS overwrite if GPU TS is available
Change-Id: I2fc1a43c048b4fa1e42f27c4cf5c72fc7ae84e9c
2021-08-22 23:56:07 -07:00
pvellien c11c02f2c7 SWDEV-285333 - Introduce Address sanitizer hostcall service
Change-Id: Id29aacd09d0a9934a027446c57c7095804e1a454
2021-08-22 23:56:07 -07:00
Vladislav Sytchenko f6c00765e7 SWDEV-274815 - [PAL] Navi24 support
Change-Id: I934797bda471618c3f69484a1552b37345ae638b
2021-08-22 23:56:07 -07:00
Jason Tang b793811ef6 SWDEV-287088 - Workaround VM page fault on Windows
Some chunk memory are not guaranteed to be resident during
initial allocation. Use CPDMA to force resident.

Change-Id: If1a2da3e75f136caaa4c7a29d8f604d6af2639fa
2021-08-22 23:56:07 -07:00
German Andryeyev ce8dad2ecc SWDEV-290160 - Switch to global HSA signals
Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.

Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1
2021-08-22 23:56:07 -07:00
Alex Xie b5b1ccc990 SWDEV-290122 - OpenGL tests fails with CL_MEM_ALLOCATION_ERROR
Change-Id: I34d7063f05dd46c32cf59a88c455691ba5099679
2021-08-22 23:56:07 -07:00
Saleel Kudchadker 8e08880cc3 SWDEV-247372 - Add logging for debug
Change-Id: Id5a27034005a7deba37072d8a4c6f250104a96c8
2021-08-22 23:56:07 -07:00
German Andryeyev c49f1069ab SWDEV-290160 - Don't send notification for batch markers
Batch marker already has a barrier with HSA signal callback

Change-Id: I69fc63d72320c2e9cc2d2e59ebd3f07c0bd0e3b5
2021-08-22 23:56:07 -07:00
Sourabh Betigeri b2a1dc26ba SWDEV-286446 - This patch enables stream operations on vega10, vega20, MI100 and MI200
Change-Id: I6f07036d8ee6e4c6b55196a13288f8107488d824
2021-08-22 23:56:07 -07:00
Saleel Kudchadker d3213eca90 SWDEV-247372 - Reset hasPendingDispatch
Reset hasPendingDispatch_ if we insert barrier for time marker.

Change-Id: Id038fd4e1c910c0a657978fee00630e49c372321
2021-08-22 23:56:07 -07:00
Aaron Liu fe2d7424e5 SWDEV-290474 - [Lnx][VanGogh] Add VanGogh support
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Christophe Paquot <christophe.paquot@amd.com>
Change-Id: Iff0253a181bbfc1984304014a9e3b542b2556635
2021-08-22 23:56:07 -07:00
German Andryeyev a1629cad26 SWDEV-290371 - Add lock protection for signal
Add lock protection for signal processing
If signal is reused, then disable reference to it from HIP
Increase the pool signal size to 32

Change-Id: I7d529b35910f83ce577c9eca6d3386759611ccc0
2021-08-22 23:56:07 -07:00
Saleel Kudchadker 0af6ba9428 SWDEV-286092 - Use Barrier Header for event
Change-Id: I9701fbab587e2ea31e58449e8c8b07341a7aa161
2021-08-22 23:56:07 -07:00
Alex Xie b818301d53 SWDEV-290306 - [LNX][Navi24][mainline]clinfo test failed on Navi24
Add Navi 24 support

Change-Id: I7343384cf6fb8c532321e57e202c196ef054f459
2021-08-22 23:56:07 -07:00
Saleel Kudchadker b416ad7b9d SWDEV-247372 - Active wait timeout env var
- Create an env var ROC_ACTIVE_WAIT_TIMEOUT to set active wait timeout
- Record profiling informaion if marker_ts_ property is valid.

Change-Id: If0d8aec8d9b0715027cf0f7c3dc8a4c722a6bae6
2021-08-22 23:56:07 -07:00
Arya.Rafii 8b22111f4b SWDEV-289250 - Should return a nullptr for PAL so we can assume it's a host ptr
Change-Id: I530eb39104bbe727c3e38186f6db4e64285b3fc8
2021-08-22 23:56:07 -07:00
Christophe Paquot d13581efa7 SWDEV-276396 - Implement hipDeviceReset
Add a Purge function to MemObjMap

Change-Id: Iac51dfda9a7b7c45f2f4a0dc35f7a623121aba1a
2021-08-22 23:56:07 -07:00
German Andryeyev 85c70a7495 SWDEV-284671 - Add HW event wait to improve hipDeviceSynchronize
If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.

Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596
2021-08-22 23:56:07 -07:00
Vladislav Sytchenko 0b1481d4f1 SWDEV-289548 - [PAL] Revive Raven 2 support
Revert back to using the Raven (gfx902) target ID for Raven 2 (gfx909).
This is due to the HSAIL compiler not supporting gfx909.

In theory there should be no issue with running Raven isa on Raven 2.

Change-Id: I425edebc99075799eda5522fad231b8fb3184873
2021-08-22 23:56:07 -07:00
kjayapra-amd d2bf9f9b58 SWDEV-288690 - Updating the return value with roc::Device::init
Change-Id: I132fa424cf9bec608e5c8429e93d20e78b76c6f0
2021-08-22 23:56:07 -07:00
German Andryeyev 89b69638d1 SWDEV-240804 - Update ReadMostly attribute
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.

Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
2021-08-22 23:56:07 -07:00
cjatin 228662bf3f SWDEV-283267 - Fix a bug where rocclr appends compiler options twice
Change-Id: I54ca6e8458cf6414c263df7a8bf61f7ce39a64df
2021-08-22 23:56:07 -07:00
German Andryeyev a9a1e21445 SWDEV-240804 - Add coarse grain memory support
Add an extension to memory advise to disable cache coherency for
better performance

Change-Id: I283703d81d9c36ddfa2c8fffa15eef60e2195056
2021-08-22 23:56:07 -07:00
German Andryeyev d93df7037c SWDEV-287137 - Add blocking signal logic
With HIP API callback runtime has to stall the queue until the
callback is done. Rocclr will introduce SW blocking HSA signal,
which will be released after the callback is done.

Change-Id: I6411f3efab31b468e3b87ebb5c8d155e116b613d
2021-08-22 23:56:07 -07:00
Vladislav Sytchenko 7f0c18457d SWDEV-273235 - Initial support for Windows CMake
This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.

Currently supported compilers:
    HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
    LC    - enabled by ROCCLR_ENABLE_LC    (defaults to ON)

Currently supported runtimes:
    HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
    PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)

Any configuration is supported as long as at least one compiler and one
runtime is enabled.

Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.

Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf
2021-08-22 23:56:00 -07:00
Jason Tang 1b832c0182 SWDEV-287945 - LinuxPro: Disable PAL for gfx9+
Change-Id: Ief81629e53a4c0ca529a510dac5063a8885257bf
2021-05-27 11:05:43 -04:00
German Andryeyev 148a5cac39 SWDEV-287137 - Fix regression with dependent signals
- Make sure barrier with dependent signals issues before queue
index reservation
- Don't issue extra barrier if it's already a barrier command
with dependent signals

Change-Id: I179a8b7adac79eed698f4a4d9eca2606d8e913aa
2021-05-26 12:36:56 -04:00
Jason Tang 7932b5a562 SWDEV-287332 - Disable NullDevice in HIP
Change-Id: I45c6010d2a3fcd0576438e3c72fbed78dff09b6b
2021-05-26 09:27:59 -04:00
German Andryeyev fa2e154a8b SWDEV-278894 - Use GPU waits for HIP events
Save HW events in amd::Event.
Use HW events for synchronization

Change-Id: I98cf9c2d0ec3c7fcaf254b749ac6c568d7270ae0
2021-05-25 13:41:15 -04:00
Jason Tang 8cac880779 SWDEV-277566 - HSAIL: put back the original setKernels logic for now
In HSAIL path, kernel akc info is obtained after code object
loading, and kernel signature creation requires the akc info
when one of the kernel argument is a reference object.

Change-Id: I9cdb1dbf2c72f4620b0b6e46a88402a2473c3e97
2021-05-20 11:16:48 -04:00
Ravi C Akkenapally 0aa524363d SWDEV-245531 - GLInterop: Add Buffer Interop support
Change-Id: I38326173475e84f8eca2605522542ef89a3cf524
2021-05-19 12:24:24 -07:00
kjayapra-amd 1c49d8816c SWDEV-286346 - Implement Arena Memory Object for externally created memory.
Change-Id: I8530602d89edf83ad367c52167e48a1559ee1e18
2021-05-18 10:59:52 -04:00
Jason Tang ed923eb12e SWDEV-269983 - Re-enable OpenCL Offline Compilation in ROCr path
Change-Id: I160c56a6964219c56c85ebeb5f475be535c39022
2021-05-18 10:46:46 -04:00