Remove assert for kernel arg size, because COv5 reports a value
bigger than the actual usage in the most of cases
Change-Id: I8e15bc45a9e21b58a5894f9977511ca84408ce61
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock
Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
OCL2.2 requires SPIR-V and runtime doesn't support it.
Make sure PAL backend doesn't report any SPIR-V support.
Change-Id: I8d179069674205b54f7d20d149bcb675bee5cdb0
Metadata in Codeobject version 5 is the extension of CO3 and CO4.
Add the detection of the new fields and program them in
the setup of the kernel arguments.
Change-Id: I27e58df77320ad00f4f16d35912668db803826af
Use HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT to get compute
units. This is needed to work around assymentric CU harvesting bug on
gfx90a. Add a new device property to get the max available CUs on the
device.
Change-Id: I878f38f14f16c1af01fc0a77157aea1e816a63b8
Report proper target id for xnack in HSAIL path. Runtime
will use ISA table and report hsailName().
Fix offline compilation path for PAL.
Change-Id: Ic0250bf6b9c193d867aec9800a319da1bf00c3ee
With SAM on, don't force Persistent for allocations
in HIP. This makes ROCCLR go down paths we don't want
for HIP.
Change-Id: If54cc16fa891d4cfdc761c6ab21ad707627e822a
- Create hash values for binaries
- Add the binaries into RGP trace
- Add corresponding hash value for every dispatch
Change-Id: I2c3ce004d69f37d0d46bc4744e12f24273517f5e
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.
Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121
Change the scope of hostcall buffer access lock during destruction.
Make sure wait() returns the signal value after timeout. That
matches ROCr behaviour for HSA signal wait.
Change-Id: I3df34207e0c2e21972ec8052777e5742bda1dca0
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.
Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
PCMark10 counts the time spent in clCreateKernel as part of execution
time, so as workaround for the PAL path, move code object loading
back to clBuildProgram.
Change-Id: I3b9cf1879ece08ab59f447ec165b0525bc8593a4
Redshift sees around a 3x performance uplift this change.
Turning this on for OpenCL might cause unwanted behaviour, due to
apps like RSX running in the background all the time.
Change-Id: I9f32d5f2e05b6697a8aaa9ddf74474b5531bb7e1
Note that this requires base driver CL#2340320+ to have SQ interrupt
functionality enabled by default.
Change-Id: I04b936819ebe1eb7cf5de1db4fafe83af3a1b5f6
Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.
HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.
Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset
Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
This reverts commit 9df70fa03ce60d47247eb0e8f278e1f8dbd33d6e.
Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.
Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7
German Andryeyev
kjayapra-amd
Saleel Kudchadker
Todd tiantuo Li
Payam
Alex Xie
Satyanvesh Dittakavi
haoyuan2
Julia Jiang
Christophe Paquot
Sarbojit Sarkar
Jason Tang
Vladislav Sytchenko
agunashe
pvellien