Updates:
* [rocm-smi] Provide a thread-safe logging feature
* [rocm-smi] Adding logrotation into install/upgrade/remove
scripts
* [rocm-smi] Updated cmake lists to include rocm_smi_logger
* [rocm-smi] Updated DEB/RPM install/remove logging file &
folder with all users having r/w privledges for
/var/log/rocm_smi_lib/ROCm-SMI-lib.log
* [rocm-smi] Added ability to do a glob search for multiple files
(globFileExists), assists doing file searches with * strings
* [rocm-smi] Added ability to log system details when RSMI_LOGGING
is turned on (getSystemDetails())
* [rocm-smi] Added logging to provide which ROCm API is being called
when RSMI_LOGGING is on
* [rocm-smi] Added logging to provide SYSFS path and read value,
when RSMI_LOGGING is on. Provides error reponse on failure.
* [rocm-smi] Added logging to provide SYSFS path and read value,
when RSMI_LOGGING is on. Provides error reponse on failure.
* [rocm-smi] Added environment variable RSMI_LOGGING to control
when logging is enabled or disabled. By default, by not
setting this env. variable, logging is turned off. When
setting RSMI_LOGGING=<any value>, logging is enabled
which is placed in /var/log/rocm_smi_lib/ROCm-SMI-lib.log file.
Setting RSMI_LOGGING is allowed in both debug and release builds.
* [rocm-smi] Removed an initialize procedure which keeps
debug_inf_loop. Seems this feature is not being used.
Change-Id: I79b48387609c6233c6f05b04fb8bba66b68c2399
Signed-off-by: Charis Poag <Charis.Poag@amd.com>
Add support for HSA_ENABLE_PEER_SDMA env variable that can be used to
disable use of SDMA engines for device-to-device transfers. Note that
setting HSA_ENABLE_SDMA=0 will disable all SDMA transfers and override
HSA_ENABLE_PEER_SDMA values.
Change-Id: I737b3c2b2efcf3ff237f98bc748f49b8252ed24a
For aqua_vanjaram APU mode, KFDEvictTest and KFDSVMEvictTest are
skipped. Those tests passed on dGPU mode with memory reporting partition
support on GFX 9.4.3.
Change-Id: I56357843c6743b01b807359dbb37b32391fd9a25
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Add support functions to remap the first page of device memory (GPU/GTT)
to share host ASAN logic.
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Change-Id: I4c27d5417ba80a172dccb0a079a597c5dc1c8f85
Update documentation for hsa_amd_pointer_info to clarify which fields
are invalid when the allocation type is HSA_EXT_POINTER_TYPE_UNKNOWN.
Change-Id: Idaed985962c4a98d281ebe01bef8ec2459da3985
Some workloads running on multi-GPU create 1 process per GPU. So each
process creates a GPU agent on every GPU, but will only create queues on
one GPU. This would cause un-necessary scratch reservation.
Change-Id: I50a216f0bcc0b5f707f3943147390b0ecec1ac22
If the required scratch allocation is too large, ROCr will attempt to
reduce it by lowering the dispatch's targeted occupancy. The reduction
loop however was prone to overflow if waves_per_cu was not a multiple of
waves_per_group. Ensure no overflow by aligning waves_per_cu to
waves_per_group.
On GC 9.4.3 dGPU, dispatches with a large grid size and a
waves_per_group of e.g. 16 may require to reduce occupancy such that
waves_per_cu is less than waves_per_group to ensure the allocation size
is small enough. Allow this while also ensuring the tmpring scratch wave
count is kept divisible by the number of SEs per XCC.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: Ie4016dcd8166a9ae69e9decc26a3eec882b49480
When we merge thunk into ROCr, kfdtest will be in a different folder
structure. Add the new location to ensure that we can build now and in
the future with no disruptions
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I6517e061cb0da7137d903abbc380bfc7126f40d4
Scratch cache reserved memory is only available for scratch memory use
so do not report this memory as available to the user via the
HSA_AMD_AGENT_INFO_MEMORY_AVAIL api.
Change-Id: I52f96e62536458bcaa52b9f4be5de856d5680dc4
Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
Change-Id: I10e30fdc2bec587cef9427faa4874957988c34b3
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
If MES is enabled, wptr has to be non paged memory,
Add an API to check this condition.
Change-Id: I53af1f6687d5332d102e7062c3d760e33b96e722
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
If Dev0 and Dev1 are not the same gfx, we should temporarily
set the target ASIC for compiling Shader code.
Signed-off-by: Shane Xiao <shane.xiao@amd.com>
Signed-off-by: Shikai Guo <shikai.guo@amd.com>
Change-Id: I5836beb16ade519f5a148d3d2b9c2875554f0c35
gobhardw
Charis Poag
David Yat Sin
Philip Yang
Bing Ma
Ammar ELWazir
Ranjith Ramakrishnan
Cole Ramos
Graham Sider
Kent Russell
Yifan Zhang
Saleel Kudchadker
Sam Wu
Giovanni LB
fei.zheng
Shane Xiao