Graf Tiomantas

177 Tiomáintí

Údar SHA1 Teachtaireacht Dáta
Sean Keely 5af558f739 Place GPU local resources in nearest NUMA node.
For minimal latency we should place command queues and blit code
in the nearest numa node to each GPU.  Add an allocator matching
the current runtime default allocator interface to each GpuAgent
that allocates on the closest numa node as represented by kfd
topology.  Use this allocator for queue ring buffers and blit
objects.

Change-Id: I181127f9c27bafe68976312963146616e3f58369
2021-09-14 17:49:24 -04:00
Sean Keely 907679c989 Register the default queue error handler for all internal queues.
Also make failure to handle queue errors fatal.

Motivation is to improve detection of queue error conditions
that currently appear as application hangs.

Change-Id: I655643616dc0bd303d7df3ce8aca2c099bec3d46
2021-08-27 20:11:58 -04:00
Sean Keely 270d042ef8 Minor interface improvement to pointer info.
Take in const void* rather than void*.  This does not break the
abi or existing code.  Existing code would need to cast away any
const which is unnecessary and annoying.

Change-Id: I28787e8fab1b600bf6871ea82835e10a4f475c5b
2021-08-04 16:43:23 -04:00
Sean Keely bb4dfbba1e Correct data race in GpuAgent::GetXgmiBlit.
Threads may race against xgmi_peer_list_ when dynamically assigning
peers to sdma engines.

Change-Id: I300c10f0cfa0ff7d6a5515364070a0895e2f4644
2021-07-30 16:10:59 -04:00
Sean Keely 4455250be1 Add HSA_CU_MASK
New environment variable HSA_CU_MASK allows users to
specify a cu mask to every queue allocated from any
GPU.  hsa_amd_queue_cu_set_mask is restricted from
escaping this mask.

A new API hsa_amd_queue_cu_get_mask is added to query
the current cu mask.

Change-Id: I846c03a5faaca9b95067c31db84b59cc9fce2f03
2021-07-29 02:23:34 -05:00
Laurent Morichetti ef1955ad42 Fix incorrect packet index in ttmp6
ttmp6.packet_index is reported as 0 for all waves, regardless of the
dispatch packet position in the queue, due to an issue in the clearing
of the previous trap_id and saved status.halt bit.

Fixed TTMP6_SAVED_STATUS_HALT_MASK to only be one bit, 1<<29.

Change-Id: Ia4934e51123a40d71de658efc387a1f3a6344f05
2021-07-16 18:03:26 -05:00
Jay Cornwall f3d942b67f Report union of wave errors as a bitmask in trap handler
Also fix incorrect PC increment on host trap.

Change-Id: Ic8bbf2b90f9f879ba62b558b909d010a8939a663
2021-07-16 18:03:26 -05:00
Jay Cornwall 7e4088309d Add new trap handler, bump debug API version
Also fix hsaKmtRuntimeEnable error handling. Continue if ioctl fails.

Change-Id: I754ccba5910ccfef6f1ada1415593ef89ce33aba
2021-07-16 18:03:26 -05:00
Sean Keely 206e87d28b Support debugging hw exceptions.
Change-Id: I9780147294af2e9457fa54693580735452ee2ae6
2021-07-16 18:03:26 -05:00
Sean Keely 981c6bd8c3 Remove unused GpuAgent.local_region_ member.
Change-Id: I99526e6b1f64e810f7fed5d922c540d252a46d80
2021-06-07 19:59:58 -04:00
Sean Keely 0b7d9db964 Correct scratch in use computation.
Old logic did not consider memory held in the scratch cache to be
free when deciding whether or not to reclaim.

Change-Id: I7f7c7549c72d743edbf7c53489fe9a453dc4177a
2021-04-22 20:07:25 -04:00
Sean Keely 77046a1aaa Revert "Revert SVM and XNACK support."
This reverts commit 5bd153974d.

Conflicts:
	opensrc/hsa-runtime/core/util/flag.h

Change-Id: I16daf41588e6139126d66af54b0693de2e7e39f3
2021-04-21 14:49:43 -05:00
Konstantin Zhuravlyov 15e54d684d Expose iterator for executables
Change-Id: I0c5d39fc33c15a6eb8ee10ff181c2dcf2e042675
2021-04-16 20:51:48 -04:00
Sean Keely 5bd153974d Revert SVM and XNACK support.
KFD is not ready yet.

Change-Id: I61deb292ddb92185d33504c2115169888d56e211
2021-04-02 02:10:59 -04:00
Sean Keely 7333c77e22 Squash merge of cfreehil/amd-temp-gfx90a onto amd-staging.
Includes some workarounds and HMM.
Conflicts:
	opensrc/hsa-runtime/core/runtime/amd_topology.cpp
	opensrc/hsa-runtime/core/util/flag.h

Change-Id: I22976f07964a43dbb228a6231777dbd599112b8d
2021-04-02 02:10:15 -04:00
Sean Keely 45fbe5b192 Block ROCm 4.1+ running against 4.0 and prior kfd.
Sramecc is misreported in kfd 4.0 and prior.  To prevent possible
corruption due to d16 instructions, deny use of gfx906 with older
kfds and correct misreport for gfx908.  Denial of gfx906 may be
overridden by setting HSA_IGNORE_SRAMECC_MISREPORT=1.

Change-Id: I7d5c3a716fad01c348f8b88cd508cedbf914c989
2021-04-01 00:03:32 -04:00
Laurent Morichetti ea6ee0aa81 New trap handler ABI (v5)
Park the wave, if it is stopped, to avoid halting it at an s_endpgm
instruction if the architecture does not support it.

Free ttmp6 by converting the dispatch_ptr into a queue packet index
(25-bit) and storing it in ttmp7[24:0].

Save the exception PC in ttmp11[22:7] ttmp6[31:0].

Change-Id: Iaa3c5baf5b488c0b534044d338f12bffa63ddce2
2021-03-04 21:44:14 -05:00
Laurent Morichetti 7e0f391a08 Correct the trap handler
ttmp11 no longer has an "excp_raised" field.

Change-Id: I8e673ca404c2b802470bbc9f76e7925782076c5a
2021-03-04 21:21:26 -05:00
Sean Keely 34ac62274a Correct legacy copy path.
Legacy p2p copy path incorrectly transfered in whole pages rather than
the requested size.

Change-Id: I9aa7337754f9e32f587a0cc5305f8ffeb6196f10
2021-02-10 19:53:02 -05:00
Sean Keely 01f42dbe46 Add hsa_amd_signal_value_pointer.
Enables partial signal interop with non-HSA devices.

Change-Id: Ic39bca84ed1709cbd2cc24b1eb0f4fc6cccb39cf
2021-02-10 18:47:54 -05:00
Laurent Morichetti 9ca79d072a New trap handler ABI (v4)
Replace the stop reasons ttmp11.trap_raised and ttmp11.excp_raised
with ttmp11.wave_stopped which indicates that the trap handler has
halted the wave as the result of an event (trap, single-step or
exception).

If the wave is stopped because of a trap, also record the trap_id in
ttmp11.saved_trap_id[7:0].

Save status.halt in ttmp11.saved_status_halt, so that it can be
restored when resuming a wave (changing a wave's state from stopped to
running or single-stepping).

Change-Id: I7322f59b60e8cc1b92bf5f067dba606a3109ef49
2021-02-05 09:56:01 -08:00
Laurent Morichetti 8aec53969f Don't terminate waves halted at s_endpgm
To support single stepping the instruction preceding an s_endpgm,
unwind the PC by 8 bytes and set ttmp11[9] to notify the debugger
that the wave is halted with a modified PC.

Bump the debug r_version for this new trap handler ABI.

Change-Id: I55e4e0d65576f92da14a336266c31c513baab547
2021-01-21 20:51:38 -08:00
Laurent Morichetti 8808ed3177 Correct gfx10.3+ trap handler.
Change-Id: I77d2b41c8882014a430d741ecd777718a1f61561
2021-01-21 09:24:20 -08:00
Sean Keely 7bc6aac5d2 Correct computation of scratch slot requirements.
Each SE must be assigned equal numbers of slots and slots
must be assigned in units of whole groups.

Change-Id: I8f3677237fa6f2e2d25e3e78210c5a7a0ad792f3
2021-01-13 15:09:00 -05:00
Sean Keely 9fe8ccc3ee Revert "Revert "Cache scratch allocations.""
This reverts commit 7e2ba23566.

Change-Id: I3f3c257270016559f8b2e70151664f0931db28d2
2021-01-13 15:08:53 -05:00
Tony Tye 6bbf6b1c9c Improve Isa class
- Use consistent naming in Isa class.
- Remove unused Isa methods.
- Simplify Isa methods.

Change-Id: I7c4045d08fbfe0d94b3181db8ebc5e5ed8c8cc82
2021-01-10 18:23:54 +00:00
Tony 853ccc762e Store target ID in isa registry
Store target ID string in isa registry and use for returning agent and
isa name.

Change-Id: I72a20d8ff963c73d86392158aff3853e4c9bfdbd
2021-01-10 18:23:54 +00:00
Sean Keely 7e2ba23566 Revert "Cache scratch allocations."
This reverts commit 27e044ae4d.

Change-Id: I698b33bacb2be3de6c8185fe89597a60a79521c5
2021-01-08 11:57:40 -06:00
Sean Keely 27e044ae4d Cache scratch allocations.
Avoids calling to KFD to map/unmap scratch allocations for
every large scratch using dispatch.

Change-Id: I9fab5705251ec82b03e4f2f2ca6da7cdccabefb9
2020-11-20 15:07:01 -05:00
Sean Keely 32d0fcafa9 Limit clock synchronization to 16Hz.
Improves HIP event performance in directed benchmarks where
clock sync latency is significant.

Change-Id: I78b724a14a8f5b6a9a2b9f4d85afe9d8b81808a6
2020-11-20 15:06:13 -05:00
Konstantin Zhuravlyov 3a08d0964e Implement Target ID Proposal
Changes from Konstantin Zhuravlyov, Tony Tye

Change-Id: I532801193afa9d5b8ac2a877b5497eab661f0597
2020-11-10 13:42:35 -05:00
Sean Keely 2a0c6774fb Use SDMA for small copies in VRAM.
For small copies cache flush latency is larger than data transfer
latency in local VRAM.  Select SDMA for small copies.

Environment key HSA_FORCE_SDMA_SIZE is added for easy adjustment
of the small copy size.  This may be removed after tuning is done.

Change-Id: I733fa0ae01c616617c5de50e71226b51fd589ef2
2020-09-03 03:11:57 -05:00
Sean Keely f4fe7ddf47 Make explicit reference between init modules.
Make explicit reference to hsa_api_trace.cpp from
initialization of hsa_table_interface.cpp.  Breaks
the ability to use hsa_table_interface.cpp in plugins.

Change-Id: I22a42d3a132512b0d9ec7a1ca629b169e7f8eba7
2020-07-15 16:02:15 -04:00
Sean Keely f6e6eae86d Remove unnecessary HSA_API declarations.
The excess declarations mark implemenation functions as default
visibility.  Normally this is not an issue since our linker script
will specify which visible symbols will be permitted into the dynamic
symbol table.  However, for static linking methods which apply linker
directives during incremental linking symbol visibility must be correct
in the (non-dynamic) symbol table.

Change-Id: I13dc8dd1019368e8943920d36335a91f0c555a92
2020-07-07 16:41:34 -04:00
Laurent Morichetti 23df617150 Set the correct bit in m0 for gfx10
The size of the m0 payload for MSG_INTERRUPT has changed in gfx10. It is
now 23bit wide instead of 24bit wide in gfx9.

Since we are generating different binaries for gfx9 and gfx10, we can
conditionally set DEBUG_INTERRUPT_CONTEXT_ID_BIT to 23 for gfx9 and
22 for gfx10.

Change-Id: Ifc15a9fa4399d35328ab58b742f791f1660bcd9a
2020-06-30 22:02:41 -04:00
Ramesh Errabolu f7350c6020 Update ROCr implementation of Queue ID
Change-Id: Iec48b1978e4d01563e71cfb58aed8f1bbc446443
2020-06-26 13:25:00 -05:00
Sean Keely cc7a197ff8 Use correct queue id for gws assignment.
Change-Id: I9157951abce65b60dfe0e1db5819510a7703547f
2020-06-26 14:24:06 -04:00
Tony 91cb98dab6 Code object reader improvements
- Make code object reader use mmap when loading from a file on Linux.
- Support computing code object URI for memory either fro the loaded
  host executables, or from all mmapped files. Define the environment
  variable HSA_LOADER_ENABLE_MMAP_URI to non 0 to search the mmap
  files, otherwise only the loaded executables will be seatched.
- For mmap search, determine file size and ommit offset and size URI
  fragment when the code object is the whole file even when specifying
  a file size explicitly or specifying memory that has been mmaped.
- Always return a non-empty code object URI.
- When a code object reader is created, complete all fields to ensure
  it can be used in a multi-threaded manner using only const
  operations.
- Add missing exception handlers in the AMD vendor extentions.
- More rigorous checking for errors.

Change-Id: I07797b1dc60c5c64245142d77becf9f7c9643395
2020-06-25 12:18:50 -04:00
Sean Keely e9a4eff8a1 Update licensing and remove duplicate licenses.
Change-Id: I0aab6f310d96bf6c5a918e7a9c03713a00dc5c4a
2020-06-22 14:19:30 -04:00
Sean Keely 0be21c54a6 Move loader interface functions into rocr namespace.
For static linking all non-API functions must have internal linkage
or be in project namespace to avoid colliding with application symbols.

Change-Id: I3398e40a387cca36f3ddef2b978306c765161d72
2020-06-19 22:34:26 -04:00
Ramesh Errabolu fa13208698 Add rocr namespace to core header and impl files
Change-Id: I1e1b33f9bba1078d049bc19797889988c3e43360
2020-06-19 22:34:21 -04:00
Sean Keely ce19721c88 Update copyright date.
Change-Id: If4bf4c20cf051878bfe759080bb7345d884dd53d
2020-06-19 22:34:01 -04:00
Ramesh Errabolu 0ca0691ca7 Build ROCr core and image libraries as one shared object
Change-Id: I3a16c1227e7db2e386ab33886965596fa0fb0c87
2020-06-19 22:33:36 -04:00
Laurent Morichetti db6a781f0c Preserve the exec mask for the queue error case
Save and restore exec_lo/exec_hi around the mGetDoorbellId macro in
the signal_error case just like we do in the signal_debugger case.

Also reset the wave_id (ttmp4/ttmp5) to 0 since it isn't preserved.
0 will be detected as a new wave by the debugger api library.

Change-Id: I5123caa9431154ec1584bae85e42648c97c64c37
2020-06-18 02:25:11 -04:00
Tony 047b80ab41 Do not add offset/size to code object URI if loading from complete file
Change-Id: I7cb1e803e0bcdbc24935273af431fbcc88404bfd
2020-06-12 05:10:35 -04:00
Laurent Morichetti da6d892058 Handle address watch exceptions
Set ttmp11[8] and send a signal for the debugger when the handler
is entered because of an address watch exception.

Change-Id: Icc83a79027bb7ca1e50e19e2f00464cb9ca862f3
2020-06-02 15:25:15 -04:00
Konstantin Zhuravlyov 9eb735ec24 Add support for code object URI to ROCr
Adds the following:
	- New factory method to create a code object reader from
          file with offset and size.
	- A pair of queries on a loaded code object to get the URI name/length.
	- A bump to the AMD vendor loader extension API and its associated table.

Change-Id: I17c83e9c2447d29a43c438459395365f786a3611
2020-06-01 11:07:50 -04:00
Sean Keely 4e0bf29704 Separate memory map info printing from vmfault handler.
Allows the print utility to be called from GDB.

Change-Id: Ia27ff9ba23ad6c0117ba1278693d4c8b0473bdc1
2020-05-28 23:34:49 -04:00
Sean Keely 29b660c91e Correct IPC fragment reuse.
Memory from the suballocator may be exported via IPC.  If this
happens then the allocating process should not reuse that memory
since it would still be connected to the remote process.  IPC exported
memory must be released back to the driver.

Change-Id: I2ab0c814f63191f753fc3640cc4140ee144bf07f
2020-05-28 21:46:02 -04:00
Laurent Morichetti 584ef1e1ca Clear mode.debug_en if !status.halt
The 1st level trap handler jumps to the 2nd level trap handler on
context save requests or regular traps if (mode.debug_en
&& !status.halt) is true.

If we return from the 2nd level trap handler without status.halt=1, then
we need to make sure mode.debug_en is cleared, or we will re-enter the
2nd level trap handler again and again when trapsts.savectx is set.

Change-Id: I4db6369de8c91a32842f488a4df5c9d94fa65aa9
2020-05-19 18:31:29 -07:00