Commit Graph

332 Commits

Author SHA1 Message Date
Saleel Kudchadker f2a7ea3927 SWDEV-271010 - Increase active wait time
Increase wait time for active wait to 50us

Change-Id: I8f269ab25ecc6775e655b9eb36fafc5f41a59c95


[ROCm/clr commit: d034c48405]
2021-03-11 13:16:59 -08:00
Jason Tang 64f4e4c01c SWDEV-3 - Backport M0 changes
Change-Id: I36f676713442479ede142b7e887656f0b658bc7b


[ROCm/clr commit: 8d01cbddbe]
2021-03-10 10:25:42 -05:00
Vladislav Sytchenko 16aedba832 SWDEV-232428 - Fix CI regressions caused by 9eb113d
Change-Id: I6523a8abc19dc5b01f7eacb3a949da01afae60d5


[ROCm/clr commit: 07702bb28f]
2021-03-09 13:50:13 -05:00
Vladislav Sytchenko b1b12e51d1 SWDEV-232428 - Fix CI regressions caused by 9eb113d
Change-Id: I36e9ce964f4d7733450eee356d425d23e1d7ff2c


[ROCm/clr commit: 27e3b875f7]
2021-03-09 11:09:55 -05:00
Vladislav Sytchenko 9eb113d991 SWDEV-232428 - PAL Hostcall support
Since the majority of the Hostcall implementation now sits in the
commmon layer, the PAL backend simply just needs to invoke it. One thing
that is missing though is HSA signal support.

The newly added pal::Signal class is a light emulaion of what HSA
signals provide. The current implementation is just enough to get
Hostcall working, but it can be expanded in the future if needed to
fully emulate HSA signals.

The major difference for now between PAL and ROCm hostcall
implemenations is that PAL doesn't support blocking signals. This will
be enabled in the near future. For now use active wait for PAL.

Change-Id: I746557354ab9d71a7d4a31f9320fcc2fee5aee7f


[ROCm/clr commit: 99e8ac55cd]
2021-03-09 10:44:34 -05:00
German Andryeyev e51ecdaff3 SWDEV-274145 - process ACCESS_QUERY for all devices
HIP requires to return AccessedBy query for all device, but ROCr
can process one per query. Hence send the queries for all
available devices and then accumulate the results in runtime.

Change-Id: I082f9adb8e31c775a8ad1bf7a5af37440ef4bd16


[ROCm/clr commit: e9c484d1ce]
2021-03-08 14:19:13 -05:00
German Andryeyev 7c1443eb05 SWDEV-272449 - Create RGP manager before CommitSettingsAndInit()
Enabling DebugVMID requires a certain sequence in
PAL initialization. StartLateDeviceInit() must be called before
CommitSettingsAndInit().

Change-Id: I7385a8cc89e7a8ad97a6b56ad6acbd2cf2f29728


[ROCm/clr commit: dee99ca807]
2021-03-05 11:36:12 -05:00
German Andryeyev 3a4d69def2 SWDEV-272496 - Detect callbacks and force AQL barrier
HIP tests require HIP callbacks to be processed in another thread.
This change will use a thread from HSA signal callbacks to make
sure a HIP callback was done asynchronously.
Also process the callback before changing the status of command

Change-Id: Icef85d0e0f808663882cf6881ff1be3e5eca29ac


[ROCm/clr commit: 7f32d0b425]
2021-03-05 11:33:51 -05:00
Jason Tang 44eb6b02dc SWDEV-1 - Change file mode back to 644
Change-Id: I433740d65c8f648e346107f6d8fa57d69463b713


[ROCm/clr commit: c13f9df42a]
2021-03-05 10:17:58 -05:00
Vladislav Sytchenko 437a38aa6a SWDEV-274766 - Fix temporary file name on Windows
Change-Id: Ie06e0d14ab27f40b230ed6051cf95f4902f07c7a


[ROCm/clr commit: 8bb7399323]
2021-03-04 14:38:46 -05:00
kjayapra-amd d4707ff166 SWDEV-259566 - Adding support to retrieve handle for offsetted pointer.
Change-Id: I4a700c31a9ab481c4ea43923af57e83247555ab0


[ROCm/clr commit: 95e3a6d985]
2021-03-04 12:28:59 -05:00
Vladislav Sytchenko 9f2bb57232 SWDEV-1 - Remove unannounced asic
Change-Id: I0ec360e7f924dcfbc26bc70981a714abb57804c9


[ROCm/clr commit: b4064ad557]
2021-03-03 23:21:41 -05:00
German Andryeyev e8b1e484f5 SWDEV-274199 - Enable SVM tracking
ROCr/KFD doesn't validate memory pointers. Enable validation inside
ROCclr, using SVM tracking mechanism.

Change-Id: I581e32ff37187f9ed8d9a302e8fd9f6ca935bdd7


[ROCm/clr commit: fbde61de7f]
2021-03-03 13:18:56 -05:00
Vladislav Sytchenko fe244055b7 SWDEV-1 - [PAL] Force luxmark to use HSAIL on gfx10+
Change-Id: I929d6d15365d3a6e9fd7eaed0b8b4910694f9504


[ROCm/clr commit: d8c1da5669]
2021-03-02 16:16:56 -05:00
Ravi C Akkenapally 1d842c07ec SWDEV-179105 - Stream Operations: Add feature querying support
Change-Id: I01cb85223b83f3655e5e21ad16639da406e5cd3e


[ROCm/clr commit: e94d482c8f]
2021-03-02 11:02:15 -08:00
Vladislav Sytchenko f22b6ede06 SWDEV-232428 - Fix typo from ac53942
Change-Id: Iec1f07e04ca3ae8ad72d38034bc136b59eb89dfe


[ROCm/clr commit: 8c4cf8c1b0]
2021-03-02 12:34:38 -05:00
Tao Sang e6bde7467e SWDEV-270973 - Add missing copyright headers
Change-Id: I6bb17650f74371dae6e29c59fd6bb2022cc062fe


[ROCm/clr commit: c1c5c89cd0]
2021-03-02 12:01:54 -05:00
kjayapra-amd 5ee300da46 SWDEV-270013 - Assign Kern_args segment only for gfx90a.
Change-Id: Icc890041eb27800cb78ef9e3d7bbe02658f53821


[ROCm/clr commit: a7abe44436]
2021-03-02 11:07:37 -05:00
German Andryeyev f6cc68deac SWDEV-272496 - Fix multiple timing issues
- Don't notify if the batch is empty, because that means
the current command was processed already.
- Disable pinning optimization to avoid a race condition on stall.
- TS marker submition requires extra AQL barrier
to track the status.

Change-Id: I17eff4ad12ac66cfe1bb44048bebb1891805279d


[ROCm/clr commit: 24299e25bd]
2021-03-01 12:46:57 -05:00
Alex Xie d82e14bf2c SWDEV-272382 - [OCL][LNX] OCLMemoryInfo[1] subtest of oclruntime is failing
1. Fix the size of the memory when releasing.
2. Make sure we only count the device memory

Change-Id: Ib4dcda79f313c4ee9cc1c7bab53f8076bce5f583


[ROCm/clr commit: 639d67866c]
2021-02-28 16:00:51 -05:00
Vladislav Sytchenko 3cd2c487d3 SWDEV-193973 - Enable HSAIL for all Navi Asics
Change-Id: I0a48442f9a970de3d449e512293bc4600c62db13


[ROCm/clr commit: 4e1232a110]
2021-02-26 11:56:09 -05:00
Vladislav Sytchenko cae2f29c10 SWDEV-86035 - [PAL] Correct allocation logging
Since the allocation can be a suballocation, we should print both the
VA range for the allocation and the underlying memory object.

Change-Id: Ic9c707bbb78113b366d1b2c688e6fd33bdc8fd94


[ROCm/clr commit: 9e8a2f3266]
2021-02-24 11:35:49 -05:00
kjayapra-amd d26aceba19 SWDEV-274058 - Porting HIP, ROCclr gfx90a changes to mainline.
Change-Id: I4f4220df77e57f749a00c1dbb66743ac5af4959a


[ROCm/clr commit: 46a50965c4]
2021-02-24 09:55:54 -05:00
Jason Tang 09259cd49f SWDEV-198364 - Only enable clgl sharing in ROCm path when building LinuxPro
Change-Id: Ie4d87e252519d090a62b930f7ebb315d3477b690


[ROCm/clr commit: 54a7170e40]
2021-02-23 14:15:04 -05:00
Vladislav Sytchenko dfdb975c7d SWDEV-270013 - Fix uninitialized variable warning
Change-Id: Ic4c8090e94e82798c294ac4532ca20efbc5a3a54


[ROCm/clr commit: c93f66a5ec]
2021-02-23 11:49:28 -05:00
Vladislav Sytchenko c122c28e5d SWDEV-86035 - [PAL] Propagate gl2Uncached setting to the backend
Change-Id: I594f304a20d448fe198ec27901e6c97b265c1183


[ROCm/clr commit: dbcf023cb1]
2021-02-21 13:52:38 -05:00
Vladislav Sytchenko 007671faf8 SWDEV-86035 - [PAL] Fix runtime init
The settings need to be populated ASAP, otherwise the dummy context is
not created properly.

Change-Id: Iede0066308bb601dc68164e894775a646a0372f1


[ROCm/clr commit: 263173914f]
2021-02-20 16:39:13 -05:00
German Andryeyev 33c1e3d14d SWDEV-272496 - Wait on CPU before switching to GPU wait
GPU waits have noticeable overheads on compute with extra
AQL barrier packet and on SDMA with power saving features. This
change introduces a wait on CPU for 30 us in case the app has tiny
operations.

Change-Id: I761ba3af595f3f48544980058a9077dda15aa5f9


[ROCm/clr commit: ac387f9b03]
2021-02-17 15:19:17 -05:00
Vladislav Sytchenko 086bdf83b4 SWDEV-232428 - Push hostcall implementation to the device layer
This change unifies the hostcall implementation for all the backends,
by pushing the common logic to the device layer. This is done by
replacing the use of hsa_signal_t with device::Signal (a light wrapper
around it).

Change-Id: I7b6fca7930b5a0b199da5d85e2e048354cc04e7b


[ROCm/clr commit: 671778bdd3]
2021-02-16 17:19:57 -05:00
Jason Tang ac06dab550 SWDEV-265304 - Disable GFX8 in LinuxPro ROCr build
Change-Id: Ia26bb025a133a4acb255a539a45668975019cc6e


[ROCm/clr commit: c65be06c4c]
2021-02-16 13:32:47 -05:00
Vladislav Sytchenko 42c3dc5c6e SWDEV-271486 - [PAL] Temporarily disable reporting sramecc support
Change-Id: I089af8f8a4645ce5353f351dbf3a018cd31df216


[ROCm/clr commit: ac237ac094]
2021-02-16 10:39:18 -05:00
Vladislav Sytchenko 27fea99659 SWDEV-270013 - Fix Windows build
Change-Id: I9573ef8b9d94367b8fa1dd90d40a93ddc4992f18


[ROCm/clr commit: 660e543f49]
2021-02-16 10:03:51 -05:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
2021-02-15 17:02:38 -08:00
kjayapra-amd 4583cbafee SWDEV-270013 - Allocate kernel_arguments from kern_arg & finegrain pool instead of coarse grain.
Change-Id: Id4c6977934fdd6ef2311f6e75593801f1e51983c


[ROCm/clr commit: 2df099df9e]
2021-02-15 18:20:08 -05:00
German Andryeyev 64360211fe SWDEV-86035 - switch PAL interface to 656 version
Change-Id: I162ba6e49aa866c013f37a114df5bb7ea3e08874


[ROCm/clr commit: 70f06c79fa]
2021-02-12 13:08:59 -05:00
German Andryeyev b5e80a048a SWDEV-86035 - Enable PAL for gfx8
Change-Id: Ia6623993e44aeb4bdf317628ee8a84af6c4cacc7


[ROCm/clr commit: e7c636c5e7]
2021-02-11 14:25:43 -05:00
Payam 72b49f0800 SWDEV-257937 - Updated fix for ROC_BARRIER_SYNC=0
Change-Id: I7e28e541b654db57fb0890d7dbb7519cfb2d93db


[ROCm/clr commit: a2e0b0495c]
2021-02-11 14:01:45 -05:00
German Andryeyev 1ac2b818e6 SWDEV-271806 - Disable pinning for views.
Only parent object should pin system memory

Change-Id: Ic9a0a34e3aff2263501c564c3cebd33f4f7e2455


[ROCm/clr commit: fb142e7b2f]
2021-02-11 13:05:58 -05:00
Vladislav Sytchenko 4f2684594f SWDEV-252745 - Fix uninitialized variable
Change-Id: I9167dc3c85779771a44626f2f88eec4134c5a5ad


[ROCm/clr commit: ee1ec3258d]
2021-02-11 10:26:38 -05:00
Rahul Garg ff35f82881 SWDEV-271182 - Fix HdpMemFlushCntl and HdpRegFlushCntl
Change-Id: Ib690b475c2c4514c862ded5fc2bdd1049e27bd46


[ROCm/clr commit: df0b14ff47]
2021-02-10 11:40:35 -05:00
cjatin 43a470093d SWDEV-252745 - Adding precompiled headers to build option
Change-Id: Iab03e8a75215d80c91817ee0227d034fefa9dfad


[ROCm/clr commit: 5cfea2981b]
2021-02-09 23:33:55 -05:00
German Andryeyev e60c7aa890 SWDEV-269654 - Fix HIP stream busy query
- Avoid GPU wait on the marker submission and update the command
batch after HSA signal callback upon HSA barrier completion.

Change-Id: I5c1c97212aefc2ae4b99aa9e2a81627ee9a38c1c


[ROCm/clr commit: 6966d8098e]
2021-02-09 12:57:12 -05:00
Vladislav Sytchenko ac5394299f SWDEV-232428 - Use std atomics
Change-Id: Ieca85738621d056e612faf4de1e2011a817b8965


[ROCm/clr commit: 738fd1d24b]
2021-02-08 16:50:41 -05:00
Alex Xie c490930624 SWDEV-268914 - Linux, AMF, tests fail to scale images down
In pitch workaround, we need to copy the image to copy buffer
when application wants to read image to buffer. After this
patch, we unconditionally copy the image data to the copy buffer.

Change-Id: I71b0d19459542dfbb3ca51a2c8a3a81367fa2fb5


[ROCm/clr commit: 5330679473]
2021-02-01 15:22:15 -05:00
Joseph Greathouse 62fee66ff2 SWDEV-270773 - Fix workgroup calculation logic for GWS initialization
The existing workgroup calculation logic for GWS initialization is
incorrect. It tries to add together workgroups across dimensions,
leading to major under-count in 2D and 3D kernels. An (x,y,z) kernel
uses x * y * z blocks, not x + y + z.

In addition, the previous logic was incorrect for the case of launching
a single-threaded kernel. It calculated 0 workgroups, leading to
initializing GWS to -1.

Change-Id: I1bb20a0d5b6e0cc10ac55901c28d8f93aac61c09


[ROCm/clr commit: 54d1d69c0a]
2021-01-31 01:16:48 -06:00
Saleel Kudchadker 7a08212ce1 SWDEV-257787 - Add log for tracking copy signals
Change-Id: I713e8463916a85a634a1ec2309bbd46a11c461a8


[ROCm/clr commit: 629a2d8ef3]
2021-01-28 13:25:49 -05:00
Vladislav Sytchenko 95655fd5fd SWDEV-268186 - [PAL] Enable MALL for persistent allocations
Change-Id: Ibc21255d5be52289cb4de3de7d12e0415fd1bc91


[ROCm/clr commit: 0d0739a39b]
2021-01-28 12:47:18 -05:00
Vladislav Sytchenko b8ce1cc059 SWDEV-1 - Update ISA table
Disable gfx9+ for GSL.

Enable gfx9+ (except MI100/200/300) for PAL.

Change-Id: Ic5a238af939e1d8795503aae39df6a6ece50a9d2


[ROCm/clr commit: 81e331dc42]
2021-01-28 11:26:22 -05:00
kjayapra-amd 4693ecf345 SWDEV-270013 - Adding code to differentiate between kern_arg + fine_grain and fine_grain segment of system memory.
Change-Id: Id0404b2dab8561946ad0a90a77030582f7e021a4


[ROCm/clr commit: 85fafb0561]
2021-01-28 09:48:17 -05:00
German Andryeyev f96e973378 SWDEV-257787 - Add engine tracking per signal
- The logic will trace compute, sdma read/write operations and
apply signals when necessary
- ROC_CPU_WAIT_FOR_SIGNAL, ROC_SYSTEM_SCOPE_SIGNAL
and ROC_SKIP_COPY_SYNC were added to control the tracking

Change-Id: I9e8e6174c63bf7784f7ab00964e2918c8667d364


[ROCm/clr commit: dbc7abaecf]
2021-01-25 12:34:45 -05:00