rocm-systems

Autor(a) SHA1 Mensagem Data

Autor(a)	SHA1	Mensagem	Data
Sylvain Jeaugey	5dffba1287	Rework shared memory code to use SYSCHECK macros. This is to handle EINTR/EGAIN properly (issue #137), and also make the code consistent with the rest. Unfortunately posix_fallocate and mmap do not follow the classic return code/errno pattern, so we need to write wrappers around those functions. [ROCm/rccl commit: `eed8218e17`]	2018-11-29 12:52:13 -08:00
Sylvain Jeaugey	8ffcfac437	2.3.5-5 Add support for inter-node communication using sockets and InfiniBand/RoCE. Improve latency. Add support for aggregation. Improve LL/regular tuning. Remove tests as those are now at github.com/nvidia/nccl-tests . [ROCm/rccl commit: `f93fe9bfd9`]	2018-09-25 14:12:01 -07:00

Sylvain Jeaugey

5dffba1287

Rework shared memory code to use SYSCHECK macros.

This is to handle EINTR/EGAIN properly (issue #137), and also
make the code consistent with the rest.

Unfortunately posix_fallocate and mmap do not follow the classic
return code/errno pattern, so we need to write wrappers around those
functions.


[ROCm/rccl commit: eed8218e17]

2018-11-29 12:52:13 -08:00

Sylvain Jeaugey

8ffcfac437

2.3.5-5

Add support for inter-node communication using sockets and InfiniBand/RoCE.
Improve latency.
Add support for aggregation.
Improve LL/regular tuning.
Remove tests as those are now at github.com/nvidia/nccl-tests .


[ROCm/rccl commit: f93fe9bfd9]

2018-09-25 14:12:01 -07:00

2 Cometimentos