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1737 次代码提交

作者 SHA1 备注 提交日期
Chaudhary, Jatin Jaikishan b0d9ea7454 SWDEV-525969 - add gfx950 to use ocp type for fp8 (#157)
* do not use __gfx94plus_clr__ macro in fp8 header


[ROCm/clr commit: 5214d1ca07]
2025-04-09 16:21:39 +01:00
Betigeri, Sourabh 487ede31a9 SWDEV-523281 - [clr] Implementation of hipLaunchKernelExC and hipDrvLaunchKernelEx API with support for cooperative launch (#92)
[ROCm/clr commit: 8c6b90996e]
2025-04-03 20:10:05 +09:00
Dittakavi, Satyanvesh 0506822f4d SWDEV-516595 - Add __shfl functions with __hip_bfloat16 datatype (#42)
Also removes asserts in cooperative groups shfl functions since
__hip_bfloat16 shfl is present now

Change-Id: I57578b6e68dccc10c2ddcd194e9cc18bc7732ce1

[ROCm/clr commit: 376f23b86a]
2025-03-25 15:38:01 +05:30
Gerardo Hernandez 8c9aa07b3a SWDEV-420237 - Add __reduce_add_sync()
Change-Id: Ic8e4fab6b7aeb879d40b2c1419b30d1355a2bbdc


[ROCm/clr commit: 340d6bb69f]
2025-03-12 03:20:49 -04:00
taosang2 dae18cb473 SWDEV-512613 - Improve device atomics functions
Also part of SWDEV-510994.
1. Fix atomicMin/Max_system() for float and double.
2. Remove logics of gfx941 which isn't supported.

Change-Id: Iacfdc1bc13e8da2f5df8751bb315b37d33cea667


[ROCm/clr commit: d91e1f19d0]
2025-03-06 10:05:59 -05:00
Branislav Brzak c81185cf26 SWDEV-516564 - SWDEV-512817 - Remove mentions of gfx940 and gfx941
Change-Id: Ia069fcb9c6948c3fc9a00961593c9dcc59609375


[ROCm/clr commit: c2d1776ebd]
2025-03-05 04:26:07 -05:00
Rahul Manocha 75d53e5c22 SWDEV-489106 - Linker API addition to runtime
1) Add Linker APIs to runtime to support SPIRV linking
2) Migrate Internal implementations to runtime and share with rtc
3) Add Support to bundled and unbundled SPIRV Code object linking.

Change-Id: Ic1fd4431f842a208a2468e8aec54a65b5fa6b0e3


[ROCm/clr commit: 5930f047bb]
2025-02-22 13:39:23 -05:00
Jimbo Xie 8a42a52d0f SWDEV-477219 - implement hipEventRecordWithFlags
Change-Id: Icf07e85fc8c15f921f6e7c9fbd31dd3856dc988b


[ROCm/clr commit: 7a4a22d454]
2025-02-19 13:53:00 -05:00
Jatin Chaudhary 16f9dbff6c SWDEV-511239 - make fp8 standalone host compileable
- Use correct header in device_library_decl
- use std:: instead of __hip_internal:: for host compilation
- hide device specific stuff behind __clang__ and __HIP__ check

Change-Id: I2f3647e00555ed0e79f9954a459c41394c3cd49b


[ROCm/clr commit: c3f49c8788]
2025-02-18 19:07:45 -05:00
Jatin Chaudhary 5725b99619 SWDEV-474146 - use __bf16 to do operations
Change-Id: I568dfa97238fd760f5362a8e560c33402f96cff3


[ROCm/clr commit: c23913f6e7]
2025-02-12 07:03:05 -05:00
Steven Chung 5513df58eb SWDEV-496674 - Convert non-templated typedefs to templates for consistent mangling
Change-Id: I952d15f20afc85c0118403f82e75360197049ef5


[ROCm/clr commit: 782976f5c2]
2025-02-04 16:37:00 -05:00
Aidan Belton-Schure 33b4f178c0 SWDEV-443561 - Add tools dispatch table
Change-Id: I3445554e486ab7b94592571f52c1530cb918d021


[ROCm/clr commit: 152cee3737]
2025-02-04 04:57:38 -05:00
taosang2 40df900647 SWDEV-501963 - Add missing codes for gfx950
Cherry-pick https://gerrit-git.amd.com/c/compute/ec/clr/+/1162997

Change-Id: I6b3c6bf55c61cffd43cd6f17b75998f751b75723


[ROCm/clr commit: 32daa8f384]
2025-01-31 14:34:49 -05:00
Jatin Chaudhary f8421ce480 SWDEV-508617 - There is no NaN for E4M3 and FNUZ
Change-Id: I330b041019990231c098073f94d9d40a3c13ba76


[ROCm/clr commit: 1fdbf35d14]
2025-01-30 11:48:34 -05:00
Jatin Chaudhary 992b5fd009 SWDEV-507817 - fix the return type of one of the atomicMin variants
Change-Id: I9915eb174d5677e21adbabae5819c9e306338ab3


[ROCm/clr commit: e6fb89190a]
2025-01-29 11:52:19 -05:00
Jatin Chaudhary 1fb66c3e1e SWDEV-491248 - Fix build_mask
thread_rank() gives thread index in a block. Limit the range to the
current warp size.

Change-Id: Ib5c9831236096485cf99ba7ab0b911a3b10de31c


[ROCm/clr commit: bd7d40a4d8]
2025-01-22 04:46:01 -05:00
Konstantin Zhuravlyov 20b9b5a08c SWDEV-341212 - HIP header changes for supporting SPIR-V
This removes almost all uses of the deprecated
__AMDGCN_WAVEFRONT_SIZE macro, which is unavailable
when targeting SPIR-V, and adds a SPIR-V compatible
formulation of warpSize (which should end up as the
sole definition of warpSize once we remove support
for treating it as a compile time constant). It
is incomplete in that the cooperative_groups
implementation will need additional surgery.

Squashed commit of the following:

commit 6840826c3fec8516857dc4f2092d84358550f588
Author: Alex Voicu <alexandru.voicu@amd.com>
Date:   Fri Dec 6 23:36:32 2024 +0000

    Add deprecation warning for constexpr uses of `warpSize`.

commit a72307a7353034c2de53fd164e016967945fd0d1
Author: Alex Voicu <alexandru.voicu@amd.com>
Date:   Fri Dec 6 23:12:14 2024 +0000

    Prepare HIP RT for SPIR-V.

commit 5e40dd746ac4f8c93b521ef048ff9d494905ba95
Author: Alex Voicu <alexandru.voicu@amd.com>
Date:   Fri Dec 6 22:46:05 2024 +0000

    Revert stale change.

commit 231fe91c53dba4cabd832fc84eaa6ddb402271a0
Merge: a48905ec9 12dc02b4f
Author: Alex Voicu <alexandru.voicu@amd.com>
Date:   Fri Dec 6 22:37:24 2024 +0000

    Merge branch 'amd-staging' of https://github.com/ROCm/clr into amd-staging

commit a48905ec9cfe0e017cc64943195be82b530117d7
Author: Alex Voicu <alexandru.voicu@amd.com>
Date:   Tue Sep 17 03:14:56 2024 +0100

    Add scaffolding for SPIR-V support.

Change-Id: I2e84bbe90df58a5f9a8709b619905f04fa5b96dc


[ROCm/clr commit: dd4378611a]
2025-01-20 08:42:24 -05:00
Jaydeep Patel 5536076dc6 SWDEV-509664 - Specify type explicitly.
Change-Id: Ia0c0478682fa15eae7a31a2360310f08151716d4


[ROCm/clr commit: 1aa8383b09]
2025-01-17 13:09:48 -05:00
Rahul Manocha 17ad1834d4 SWDEV-492165 - Add support for 16 bit atomicAdd and atomicCAS
Change-Id: I7f1e4876fe2960dff1775d27cb6443a89e146c86


[ROCm/clr commit: 93cff75928]
2025-01-13 13:35:40 -05:00
zichguan-amd a255533afd SWDEV-495789 - revert Fix ambiguity of fma for _Float16 for libc++ (#1976)
Change-Id: I45ae4711a047f4484a018b9409c9f6ecf09720ce


[ROCm/clr commit: b8ba4ccf9c]
2024-12-29 10:56:32 -05:00
Jatin Chaudhary 11f9d84c34 SWDEV-377518 - Fix bf16/fp8 header to be compileable with hiprtc
Change-Id: I2093a39d79a46da7e102266c04c2a71e03dcb88e


[ROCm/clr commit: fccf0fa2f0]
2024-12-17 08:57:15 -05:00
Ioannis Assiouras 2c8805e536 SWDEV-483134 - Remove hipExtHostAlloc API
Change-Id: I60777ef5c56b60dd8100d0d794ca10fb3b96a555


[ROCm/clr commit: e8b2fdab96]
2024-12-16 17:13:49 -05:00
Istvan Kiss 349dacc1d9 SWDEV-502543 - Update doxygen to surface funtions and Coop Group API
Change-Id: Id4df63b8ae64a1113f85d89aa250ac9f7cc8b9bb


[ROCm/clr commit: 3c863dad91]
2024-12-14 14:11:37 -05:00
Sourabh Betigeri 750313dfed SWDEV-421020 - Adds hipGraphAddBatchMemOp, SetGetParams and execSetParams APIs
Change-Id: Ieccecfe6173cc68fd3c01f86c99f7cc09fe194a3


[ROCm/clr commit: f1c05e9026]
2024-12-13 06:23:39 +00:00
Sourabh Betigeri 7261404002 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8


[ROCm/clr commit: 03dbcd8ca7]
2024-12-12 19:29:24 -05:00
Maneesh Gupta e3bf8acd82 Revert "SWDEV-491314 - enable _sync() functions with 64-bit mask argument"
This reverts commit d05c0310d8.

Reason for revert: Introduces regression SWDEV-503319

Change-Id: I888c5b95d904146e4782e8c57d736878fcdde678


[ROCm/clr commit: 072f94c204]
2024-12-11 11:16:48 -05:00
Jatin Chaudhary 78ec2a66af SWDEV-503299 - Do not use operator to check for nan
Some libs use __HIP_NO_HALF_OPERATORS__ and __HIP_NO_HALF_CONVERSIONS__
which results in operators being hidden and can cause errors.

Change-Id: I83c194d7d727cba30b46d7c296f7d396549f5fca


[ROCm/clr commit: 98b33886cd]
2024-12-11 00:33:44 -05:00
Jatin Chaudhary 163f810941 SWDEV-501779 - add correct function qualifier for fp16 functions
Some functions were __device__ only, but should be __host__ and
__device__, changed them to __HOST_DEVICE__.
Some functions were __HOST_DEVICE__ but were using ockl functions,
changed them to __device__ only.

Change-Id: Ife9e7abe60415bda68f5f9a101e6e7c39ad51064


[ROCm/clr commit: 5122b8c999]
2024-12-05 10:17:18 -05:00
Sourabh Betigeri 1712acdd2e Revert "SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs"
This reverts commit ab0ff9163d.

Reason for revert: hipInfo fails on windows. Updating llvm amd-mainline-closed

Change-Id: I57e1fa1945188b0bc0a799c4f3d540f2b7713003


[ROCm/clr commit: 2ca644cf22]
2024-12-02 16:46:12 -05:00
Sameer Sahasrabuddhe d05c0310d8 SWDEV-491314 - enable _sync() functions with 64-bit mask argument
Change-Id: Ieb13a9e1b2fc49ff225a05a51056d1212d95ae57


[ROCm/clr commit: 4e2fd192eb]
2024-12-01 10:16:59 -05:00
Sourabh Betigeri ab0ff9163d SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I449ffca44bbb04d13348d112e896d603c70fd485


[ROCm/clr commit: bd5d8e9baf]
2024-11-30 17:54:32 -05:00
Aidan Belton-Schure 0cb25faf88 SWDEV-436099 Use new amdgcn_ballot builtin
Change-Id: I024fabc6c5b3f39c66885eb7615953f4d0432e9a


[ROCm/clr commit: 9652d69575]
2024-11-27 04:34:50 -05:00
Julia Jiang ea212e71a5 SWDEV-497618 - Define GL group of doxygen for HIP API
Change-Id: Ia43f25201df960b905e5fd45481f486e7bffabdb


[ROCm/clr commit: 3bd32d7d4b]
2024-11-15 11:25:51 -05:00
Sameer Sahasrabuddhe ccb09057d8 SWDEV-490198: _sync() will be enabled by default in 6.4
Change-Id: Id029424a9c0f6b144a7aa0e96fe8acc4a138ec51


[ROCm/clr commit: 556390f9c7]
2024-10-25 09:54:40 -04:00
Rahul Manocha b8a5d8396d SWDEV-468039,SWDEV-482579 - Enable FP8 SW Conversions on pre gfx940 archs
1) SW Conversions for ocp and fnuz are enabled on pre mi300 archs
2) for mi300 only fnuz is enabled
3) for gfx1200 only ocp is enabled

Change-Id: I90373752a2d15eff20d5deec874ed396ba4e1788


[ROCm/clr commit: e729f08704]
2024-10-17 11:49:22 -04:00
Jatin Chaudhary da59165313 SWDEV-486137 - match behavior of int variants of hadd/uhadd/rhadd/urhadd
Match cases and handle cases where it can overflow.

Change-Id: I3d6f802686af230a622ef9891a844135ad3d1ae5


[ROCm/clr commit: b977101893]
2024-10-09 13:47:33 -04:00
Jaydeep Patel 98539759f1 SWDEV-483436 - User spt stream as def with -fgpu-default-stream=per-thread for hipMemsetAsync.
Change-Id: Ia85c2b4c40fc9250754d3b64fb9fd1c615362572


[ROCm/clr commit: d6193a2f23]
2024-09-29 01:42:33 -04:00
Jonathan R. Madsen 43a1d720d5 Fix HIP API trace versioning
Change-Id: I33f2be4668c96e2225d4ca9a253e61ec2dc65102


[ROCm/clr commit: 07c9c7fe56]
2024-09-25 10:32:14 -04:00
Julia Jiang 29e9bed35d SWDEV481762 - Updated definition of 'DEPRECATED' in header file
Change-Id: I88986b8e1815f3d816595f3eb2da8a6c1c1c2993
Jenifer helped make a combined PSDB build, together with the change in hip repos
https://gerrit-git.amd.com/c/compute/ec/hip/+/1114046
Combined PSDB verification passed.
http://rocm-ci.amd.com/job/compute-psdb-staging-hip/17293/


[ROCm/clr commit: bb03ef11a3]
2024-09-05 15:41:04 -04:00
victzhan 11632a954a SWDEV-477218 - Implement hipDeviceGetTexture1DLinearMaxWidth
Change-Id: I8103f710abeb869f5f84be61c57a30b24356def6


[ROCm/clr commit: 8be00b6602]
2024-09-05 15:09:38 -04:00
Ioannis Assiouras a00f071579 SWDEV-470372 - Added hipExtHostAlloc API
This change adds a new HIP API `hipExtHostAlloc` which preserves
the functionality of `hipHostMalloc`.

Change-Id: I13504c6fc13465ddd7aed329795bb4f2fef1baff


[ROCm/clr commit: 2c84211b58]
2024-08-27 08:26:03 -04:00
Jatin Chaudhary 5e3fe9bd1f SWDEV-480489 - fix unsafeAtomicAdd
Integration into pytorch pointed out some issues, value narrowing, to
fix this we are now using unions. Also removed check for -munsafe*
compiler flag. The check is now just on builtin detection.

Change-Id: I49364503fa429bd862952f9b29879072afa6d553


[ROCm/clr commit: bb52d9ed62]
2024-08-27 06:29:11 -04:00
Sameer Sahasrabuddhe aacf75f480 SWDEV-480725: missing __ockl_wfall __ockl_wfany in amd_hip_bf16.h
Change-Id: Iff4aeec411bfeaf4cc187c515e2da3d5898f89cb


[ROCm/clr commit: 6df2da65cd]
2024-08-25 22:49:14 -04:00
Satyanvesh Dittakavi 6907974f90 SWDEV-473942 - SWDEV-431367 - Correct atomicMax(_system) and atomicMin(_system)
- Fixes -0.0 and +0.0 comparison. For atomicMax if the value on
address is -0.0 and on val is +0.0, gfx90a's unsafe atomics will swap
them. This behavior should be consistent with cas loop as well.

- _system variants of atomicMax and atomicMin are resulting in
incorrect output. Updated these to use the similar implementation as
atomicMax and atomicMin.

Change-Id: I20df36ee29ae0434a6b564f2ba71193fe41cfa59


[ROCm/clr commit: d69cc35750]
2024-08-13 10:38:50 -04:00
Rahul Manocha 436271e407 SWDEV-468039 - FP8 host only conversion support on mi200
Change-Id: I0891f42d1b7c0d94d099fe26df5db3eff64ba564


[ROCm/clr commit: 39bbc0341d]
2024-08-07 20:51:00 -04:00
Jaydeep Patel c51153f759 SWDEV-470886 - Add maybe_undef attribute for shfl device function due to not all lanes of wave define var and compiler needs to know about this.
Change-Id: I3a683887e033305ac55362f356838b491a6d50f2


[ROCm/clr commit: 6344ddb2f3]
2024-08-05 00:53:13 -04:00
Sourabh Betigeri f518648183 SWDEV-365151 - Fix the fns32 to do 32 bit computation and adds a wrapper to ease porting from CUDA
Change-Id: I0b5a9ca11c98f8c1c40cfba7f4e057bfda2d756e


[ROCm/clr commit: 7298b80112]
2024-07-26 11:20:14 -04:00
Sourabh Betigeri 5b0cc86295 SWDEV-475394 - Fix for the return type to be in-line with CUDA
Change-Id: I7c833571d47b4e86a86e4a0095b61947d16ecab6


[ROCm/clr commit: 4fbd7abbb2]
2024-07-25 16:33:33 -04:00
Rahul Manocha de67a2a1dc SWDEV-468039 - FP8 OCP headers
Change-Id: Iecd32c5a0357781da07395d32f894415954b7b22


[ROCm/clr commit: 353f15afa6]
2024-07-25 12:42:23 -04:00
Jatin Chaudhary 0193d66679 SWDEV-466747 - add shfl functions in bfloat16
Change-Id: Ide7d7e1d449783cced8867abf43ff45f5bce113a


[ROCm/clr commit: e43176bde9]
2024-07-23 10:51:02 -04:00