5b4e0321d4
SWDEV-345020 - The bit channel description should not allow any channels after a zero channel
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Change-Id: I66e6d25c032d22f9616dc59730f1f094d30c01cf
2022-07-24 21:35:26 -04:00
eab4ea236c
SWDEV-340506 - Unit_hipMalloc3DArray_Negative fix
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Change-Id: I1fbf4be8aaef83b36749f1e253b5dba025e7f3cd
2022-07-07 12:17:45 -04:00
8ed471f210
200~SWDEV-333583 : hipMallocArray bad channel format
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- channel format should be consistent accross parameters
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com >
Change-Id: I1e7680ab9262a66e7bea4aaa21f061044b0f7956
2022-04-29 09:15:41 -04:00
44e0c246f8
SWDEV-245531 - GLInterop adding register image
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Change-Id: I075bec49b7ad5f78336586b9d55e259717c4c000
2022-01-23 14:59:18 -05:00
3dd9dbb359
SWDEV-297563 - Move declarations to hip
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Change-Id: Ifdab79945ea2e625e8cef5cd71d638552e9a740b
2021-08-02 11:56:08 -04:00
d9d9e81acb
SWDEV-293742 - Update copyrights end year for hipamd
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Change-Id: I08f620f84563a9214b59f1b943ed091b67229eab
2021-07-09 12:08:39 -04:00
19c84bc604
ROCMOPS-1956 - Push restructured code to hipamd
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hipamd will have AMD's ROCCLR based HIP backend implementation
Change-Id: Id7de9634519b4ce46fca71a1b61f3d5b1e3fc459
2021-06-07 21:42:44 +00:00
Jaydeep Patel
Ajay
sdashmiz
pghafari
Rahul Garg