The device libraries provide hip.bc, which only contains
__atomic_work_item_fence. This is identical to OpenCL's
atomic_work_item_fence, except prefixed with __. This only existed to
switch over the unknown values the OpenCL function provides. There's
no need to go through the wrapper here since it's using constant
values, and without it we can drop one of the bitcode libraries. I'm
guessing this was a holdover from before the fence builtin existed.
Change-Id: I8b04614f96194eafddeba295215c12c3856e6c42
[ROCm/clr commit: 3e54bad5b3]
The device libraries provide hip.bc, which only contains
__atomic_work_item_fence. This is identical to OpenCL's
atomic_work_item_fence, except prefixed with __. This only existed to
switch over the unknown values the OpenCL function provides. There's
no need to go through the wrapper here since it's using constant
values, and without it we can drop one of the bitcode libraries. I'm
guessing this was a holdover from before the fence builtin existed.
Change-Id: I8b04614f96194eafddeba295215c12c3856e6c42
The uses have moved to using the proper __builtin_amdgcn_ds_swizzle.
Change-Id: I82159ebf41fb91ac6a9d07b33311e569dce5e754
[ROCm/clr commit: 91b851fad7]
Currently, Wavefront::GetInfo(HSA_WAVEFRONT_INFO_SIZE.. always returns
64. Instead, return the proper wavefront size based on the ISA.
Temporarily, we only return 1 wavefront size for each ISA. As we do not
have mechanism from upper layers to determine correct wavefront when
there are multiple wavefronts supported. We are temporarily
returning 32 for all gfx1xxx cards even though they support 64 as the
kernels for gfx1xxx are compiled for wavefront-32 by default.
Change-Id: Ic6c2917b7e6d3704daf742d243f5ec7f49430de9
Currently, Wavefront::GetInfo(HSA_WAVEFRONT_INFO_SIZE.. always returns
64. Instead, return the proper wavefront size based on the ISA.
Temporarily, we only return 1 wavefront size for each ISA. As we do not
have mechanism from upper layers to determine correct wavefront when
there are multiple wavefronts supported. We are temporarily
returning 32 for all gfx1xxx cards even though they support 64 as the
kernels for gfx1xxx are compiled for wavefront-32 by default.
Change-Id: Ic6c2917b7e6d3704daf742d243f5ec7f49430de9
[ROCm/ROCR-Runtime commit: f7e3782b42]
- Use correct header for vendor packet
- Pass one dependent signal when submitting a marker if there is one
Change-Id: I4efc70dd5204b559de26f899d0637f50421c8834
[ROCm/clr commit: 77ceb7e9ad]
- Use correct header for vendor packet
- Pass one dependent signal when submitting a marker if there is one
Change-Id: I4efc70dd5204b559de26f899d0637f50421c8834
Ieb198ad96e26e89b09cb85986214a5b1451b17a6 broke linking
for rdctst and rdcd by removing "../lib/rdc" path.
This change adds it back and makes the paths more visible.
- Link librdc_ras and librdc_rocp to rdctst
- Add longer RUNPATH for rdctst to link rdc libraries
Change-Id: Id4f128c217a6de8bb67df6750ecafdb96545811b
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
Ieb198ad96e26e89b09cb85986214a5b1451b17a6 broke linking
for rdctst and rdcd by removing "../lib/rdc" path.
This change adds it back and makes the paths more visible.
- Link librdc_ras and librdc_rocp to rdctst
- Add longer RUNPATH for rdctst to link rdc libraries
Change-Id: Id4f128c217a6de8bb67df6750ecafdb96545811b
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
[ROCm/rdc commit: fc097d44ff]
The current code generates a _optimized.bc regardlessly, so put back the original logic.
Change-Id: I3f84d10934b3e983f5f828af8d0943449a6e1d94
[ROCm/clr commit: 6647882773]
This is a temporary work around for GPU hang issues observed on GFX11.
Change-Id: I98fbedbbd1c51fe402c2116b35ca548931a390c9
Signed-off-by: David Belanger <david.belanger@amd.com>
This is a temporary work around for GPU hang issues observed on GFX11.
Change-Id: I98fbedbbd1c51fe402c2116b35ca548931a390c9
Signed-off-by: David Belanger <david.belanger@amd.com>
[ROCm/ROCR-Runtime commit: b25867c4b8]