For DD, send a NOP packet so that we leverage the handler to indicate
completion.
Change-Id: Ie57ea0124a8497d39cc49da1c4575c2cd86b9319
[ROCm/clr commit: 9d0846e732]
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.
Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
[ROCm/clr commit: 89b69638d1]
Switch HSA_AMD_SVM_ATTRIB_READ_ONLY to
HSA_AMD_SVM_ATTRIB_READ_MOSTLY to match Cuda. The new attribute
was just exposed in ROCr/KFD.
Change-Id: I2ee522d33c347ba52a4e272d2cd7f67960490cf7
All KMD/asic_reg/UGL headers are located under the drivers folder. No
need for the AMD_UGL_PATH variable as it essentially is
${AMD_DRIVERS_PATH}/ugl.
Change-Id: I070d737d50f2096493b3e75ef9b9e824cb19d048
[ROCm/clr commit: 1423c1db64]
All KMD/asic_reg/UGL headers are located under the drivers folder. No
need for the AMD_UGL_PATH variable as it essentially is
${AMD_DRIVERS_PATH}/ugl.
Change-Id: I070d737d50f2096493b3e75ef9b9e824cb19d048
Add an extension to memory advise to disable cache coherency for
better performance
Change-Id: I283703d81d9c36ddfa2c8fffa15eef60e2195056
[ROCm/clr commit: a9a1e21445]
With HIP API callback runtime has to stall the queue until the
callback is done. Rocclr will introduce SW blocking HSA signal,
which will be released after the callback is done.
Change-Id: I6411f3efab31b468e3b87ebb5c8d155e116b613d
[ROCm/clr commit: d93df7037c]
With HIP API callback runtime has to stall the queue until the
callback is done. Rocclr will introduce SW blocking HSA signal,
which will be released after the callback is done.
Change-Id: I6411f3efab31b468e3b87ebb5c8d155e116b613d
This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.
Currently supported compilers:
HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
LC - enabled by ROCCLR_ENABLE_LC (defaults to ON)
Currently supported runtimes:
HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)
Any configuration is supported as long as at least one compiler and one
runtime is enabled.
Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.
Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf
[ROCm/clr commit: 7f0c18457d]
This change refactors the current ROCclr cmake build to accomodate a
more modular approach. This allows easier support for multiple compiler
and/or multiple runtime backends.
Currently supported compilers:
HSAIL - enabled by ROCCLR_ENABLE_HSAIL (defaults to OFF)
LC - enabled by ROCCLR_ENABLE_LC (defaults to ON)
Currently supported runtimes:
HSA - enabled by ROCCLR_ENABLE_HSA (defaults to ON)
PAL - enabled by ROCCLR_ENABLE_PAL (defaults to OFF)
Any configuration is supported as long as at least one compiler and one
runtime is enabled.
Since ROCclr clients can configure it differently, one cannot reuse the
same ROCclr build artifacts between different clients. To assure this,
this patch assumes that ROCclr will be built as part of the clients
project.
Change-Id: Id4a5c43634296802b8ae87d1ad5984968391ccaf
The major version of the debug ioctl functions has been updated to 10.
Change-Id: Iddc8656ad07c92aa30c6a7a99add28ab3a3f5a80
[ROCm/ROCR-Runtime commit: d0ae4b1f3f]
Update KFDCWSRTest.BasicTest to run CWSR test with legacy HWS,
MES, and software scheduler.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Change-Id: I09af904507109c2bbbace6ff616a57fa2b1b8aa9
Update KFDCWSRTest.BasicTest to run CWSR test with legacy HWS,
MES, and software scheduler.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Change-Id: I09af904507109c2bbbace6ff616a57fa2b1b8aa9
[ROCm/ROCR-Runtime commit: acd5eda54f]
Add the new extension to HIP for quering coherency mode.
The new enum hipMemRangeAttributeCoherencyMode can be used in
hipMemRangeGetAttribute(s), which will return one of the following
values:
hipMemRangeCoherencyModeFineGrain, hipMemRangeCoherencyModeCoarseGrain,
hipMemRangeCoherencyModeIndeterminate
Change-Id: I8717873c254888ea69facc1178d3682e8747c3a7
[ROCm/hip commit: 1f53fbea8f]
Add the new extension to HIP for quering coherency mode.
The new enum hipMemRangeAttributeCoherencyMode can be used in
hipMemRangeGetAttribute(s), which will return one of the following
values:
hipMemRangeCoherencyModeFineGrain, hipMemRangeCoherencyModeCoarseGrain,
hipMemRangeCoherencyModeIndeterminate
Change-Id: I8717873c254888ea69facc1178d3682e8747c3a7
Migrated malloc related files under memory folder into catch2 framework
Change-Id: I5aa07fc8148bdf6bef135947091aaf1d3c54663b
[ROCm/hip-tests commit: 4287af6a2f]
Migrated malloc related files under memory folder into catch2 framework
Change-Id: I5aa07fc8148bdf6bef135947091aaf1d3c54663b
[ROCm/hip commit: 05e230f5c1]
Reduce the data size as unit tests are expected to take lesser time
Change-Id: Ic30be2ba3e0ff5fff19404b46163b79878716b70
[ROCm/hip-tests commit: 7f4cc61ef7]
Chauncey Hui
Saleel Kudchadker
kjayapra-amd
German Andryeyev
Vladislav Sytchenko
cjatin
Tony Tye
Mukul Joshi
Laurent Morichetti
Jenkins
anusha GodavarthySurya
gandryey
dkrottap
Satyanvesh Dittakavi
ansurya