Honor hipEventReleaseToDevice and hipEventReleaseToSystem flags.
hipEventRecord would flush caches if no release flags are provided. To
change this behavior set ROC_EVENT_NO_FLUSH=1
Change-Id: I03e41b515b1d0cf963b0c2d5b9901b09e71a0e59
[ROCm/clr commit: f320acb797]
- Add a global cache state for a device to indicate scopes of submitted
AQL packets
- Remove scopes for TS marker if hipEventReleaseToDevice is passed. Set
env ROC_EVENT_NO_FLUSH=1 to use NOP AQL for event records.
It would flush caches by default with system scope release.
- Calling finish() should ensure if caches are flushed, if not queue a
marker
Change-Id: Ibbbdbb1cd7ac61cb35649169212142545be159e0
[ROCm/clr commit: 8eeaa998c0]
Use GNUInstallDirs variables to determine the location of BINDIR,
LIBDIR, DOCDIR, and SYSCONFDIR.
Note that CMAKE_INSTALL_LIBDIR is overriden, since the default for RHEL
is lib64, but ROCm packaging wants it to be lib always. Distros or users
can easily override this.
Signed-off-by: Jeremy Newton <Jeremy.Newton@amd.com>
Change-Id: Ifb38263dce80d80c5ebb4eacd8e49c76bb013a44
[ROCm/clr commit: b8c124acb5]
Remove assert for kernel arg size, because COv5 reports a value
bigger than the actual usage in the most of cases
Change-Id: I8e15bc45a9e21b58a5894f9977511ca84408ce61
[ROCm/clr commit: 2be0b1e612]
- Clean up detection by using visual studio macros to detect arch; I
didn't list all possible ARM platforms (can be done later if desired)
- Fixed two incorrect uses of !defined(ATI_ARCH_ARM) to instead use
defined(ATI_ARCH_X86), as they contain X86 specific code
- Fixed one use of __ARM_ARCH_7A__ to use ATI_ARCH_ARM instead
This is an improvement to the fixes in the last patch for SWDEV-323669
Signed-off-by: Jeremy Newton <Jeremy.Newton@amd.com>
Change-Id: I8568167293c34ad5331902105877f3ab6e25acb3
[ROCm/clr commit: 00efdc1cd6]
This looks unused. This should allow building rocm-opencl without any
dependency on any particular OCL ICD.
Signed-off-by: Jeremy Newton <Jeremy.Newton@amd.com>
Change-Id: Ib9229ede8400fd0e883275659ab99513b03952cb
[ROCm/clr commit: 86c9bb1946]
With COv5 local size calculation must occur before
runtime programs kernel arguments
Change-Id: I0726c6529bde69b8fcf5360aa83986cf84e04168
[ROCm/clr commit: caa6110c29]
The actual size of allocation can be different from the original
request due to alignments. Pass the size of the original request
for validation during the arena object look-up
Change-Id: I30000046b1ec56abe743e43113046144fd3edbc6
[ROCm/clr commit: fb835c6f3e]
Adding opaque data handle to memory. This is used to look back the HIP object associated with it.
Change-Id: I1bbb14a915bed79c6c3593a29a627778c7aaf13a
[ROCm/clr commit: 867346520f]
Add ROCR memory detection and enable arena mem object for possible
access in HIP
Change-Id: Icf86ac789176bfee4ea8d36b0970a817d4c6a2f7
[ROCm/clr commit: 28597ec5b5]
Tensor flow build console shows "hip/lib/.hipInfo: No such file or directory"
Fixed by adding soft link for .hipInfo and this will maintain backward compatibility for file reorganization
Change-Id: I91c17115b56bbcabeb86cbcd12d3fb9aaa8f847e
[ROCm/clr commit: 1a4fd9b7ea]
hipErrorHostMemoryNotRegistered should be returned when an
unregistered pointer is passed to hipHostUnregister
Change-Id: Ie76086b602bde2cd7a7a2b049cd03d29454ff306
[ROCm/clr commit: ed4014e519]
- Fix a crash with AMD_CPU_AFFINITY=1 as numa_bitmask_alloc isnt the
right api to allocate bitmask
- Do not set affinity for ROCr thread. It worsens performance rather
than any improvement.
- Fix regression from my previous change for event handler.
Change-Id: I3ea75adc2a6333f29752283eddd5b555e9b58cc5
[ROCm/clr commit: 802c2c8a9f]
Saleel Kudchadker
Jaydeep Patel
Sourabh Betigeri
Hao Yuan
Chauncey Hui
Sarbojit Sarkar
Maxime Chambonnet
German Andryeyev
Ajay
Jeremy Newton
Christophe Paquot
kjayapra-amd
Satyanvesh Dittakavi
pghafari
Payam
Rakesh Roy
Julia Jiang
Ranjith Ramakrishnan