6c3ccc2192
Add support to another Rome model
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[ROCm/rccl commit: 95f178324c
2021-02-18 02:00:31 +00:00
fe8923ebba
Add gfx908 Rome 4 NICs model
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[ROCm/rccl commit: 6dfdfef98f
2021-02-06 00:19:47 +00:00
b954d85935
[TransferBench] Fixing some merge issues
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[ROCm/rccl commit: f372c53d52
2021-02-05 16:46:20 +00:00
ae5779702a
Merge remote-tracking branch 'origin/develop' into 2.8.3
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[ROCm/rccl commit: ab1e7a0318
2021-02-04 20:02:34 -05:00
1dfb88f554
[topo_expl] Updating for 2.8.3
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[ROCm/rccl commit: 2f541508c5
2021-02-04 19:08:42 +00:00
f2d07cb9a6
[ib-test] Update for 2.8.3]
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[ROCm/rccl commit: 9aac1ed38f
2021-02-04 19:05:03 +00:00
1643d05c75
[TransferBench] Updating for 2.8.3
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[ROCm/rccl commit: 9ce203dd0a
2021-02-04 18:58:25 +00:00
60c74f63fa
[TransferBench] Restore some previous fixes - memory leak, PCIe address ( #314 )
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[ROCm/rccl commit: 62e0447e9a
2021-02-01 09:48:09 -07:00
c981e76efe
Clique kernel support ( #295 ) ( #15 )
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* Adding experimental clique-based kernels (opt-in only)
Co-authored-by: Stanley Tsang <stanley.tsang@amd.com >
Co-authored-by: Gilbert Lee <gilbert.lee@amd.com >
Co-authored-by: Wenkai Du <43822138+wenkaidu@users.noreply.github.com >
Co-authored-by: Stanley Tsang <stanley.tsang@amd.com >
Co-authored-by: Wenkai Du <43822138+wenkaidu@users.noreply.github.com >
[ROCm/rccl commit: 3e62ceddc5
2021-01-28 09:45:01 -07:00
d4382de267
Improve collective trace
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[ROCm/rccl commit: 2ddbe6646b
2021-01-14 19:28:01 -05:00
2c49121171
Port alltoall[v]
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[ROCm/rccl commit: f4d5d3d620
2021-01-14 19:28:01 -05:00
adff98765c
Merge remote-tracking branch 'nccl/master' into no-target-id
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[ROCm/rccl commit: d469947641
2021-01-14 19:27:53 -05:00
4ea285c527
Fix Rome PCIe 2 node topology generation ( #310 )
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[ROCm/rccl commit: 373a108516
2020-12-15 17:16:17 -08:00
c570f09681
[TransferBench] Fixing bug with fine-grained memory allocation ( #311 )
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* Fixing bug with fine-grained memory
[ROCm/rccl commit: 41c35dad48
2020-12-15 17:37:31 -07:00
5155abb250
[TransferBench] Adding ability to perform CPU-executed copies, various upgrades ( #309 )
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* Adding CPU based execution, fixing typos, adding Fine-grained mem
* Exposing sampling factor when generating range of data sizes
* Refactoring how Links are launched, now once per thread
* Documentation updates
[ROCm/rccl commit: ae0c4092c7
2020-12-11 10:21:14 -07:00
9b48f92d72
[TransferBench] Support multiple of 4 byte sizes, changing default GPU timing mechanism ( #307 )
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* Changing default timing mechanism, adjusting CPU bandwidth calc, adding flag to use combined timing
* Adding support for smaller transfers (byte size must be multiple of 4 instead of 128)
[ROCm/rccl commit: b80ae551b1
2020-12-04 14:57:13 -07:00
b68ff1ebba
Add Rome model and improve search ( #305 )
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[ROCm/rccl commit: 975b14dffa
2020-11-17 14:55:06 -08:00
a7ef699687
Clique kernel support ( #295 )
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* Adding experimental clique-based kernels (opt-in only)
Co-authored-by: Stanley Tsang <stanley.tsang@amd.com >
Co-authored-by: Gilbert Lee <gilbert.lee@amd.com >
Co-authored-by: Wenkai Du <43822138+wenkaidu@users.noreply.github.com >
[ROCm/rccl commit: 41bcfb8878
2020-11-10 15:44:10 -07:00
c0c64d970a
Add more Rome models ( #292 )
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[ROCm/rccl commit: dfa3c41ede
2020-10-30 21:26:04 -07:00
2931959e6e
Adding output to CSV, removing OpenMP, decreasing default numBytes to 64MB, adding aggregate stats ( #290 )
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[ROCm/rccl commit: bfab1d3592
2020-10-27 09:00:33 -06:00
a062c80298
[TransferBench] Displaying PCIe Bus ID ( #288 )
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* Adding PCIe BusID per GPU in topology display
[ROCm/rccl commit: 61e1a71d14
2020-10-21 16:13:36 -06:00
0282595de5
TransferBench Typo. Pinned host memory uses C not P ( #286 )
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[ROCm/rccl commit: 769418c5c7
2020-10-21 12:05:38 -06:00
94437eef28
Revert "Initial support for clique-based kernels ( #276 )" ( #280 )
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This reverts commit d68a532bc684a2541e01
2020-10-15 11:30:18 -07:00
8b120c0508
Update Rome single node models ( #277 )
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[ROCm/rccl commit: 33babcb5e2
2020-10-13 13:33:09 -07:00
d68a532bc6
Initial support for clique-based kernels ( #276 )
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* Initial support for clique-based kernels
[ROCm/rccl commit: 2b8184808d
2020-10-13 11:22:04 -06:00
41260bb948
Rework Rome detection and add multiple network ports models ( #274 )
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* Rework Rome detection and add multiple network ports models
* Remove unused opCount in p2p transport
[ROCm/rccl commit: ae008fd2db
2020-10-07 13:37:36 -07:00
dbde26e681
Add Alltoallv RCCL kernel implementation ( #269 )
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* Add alltoallv API and implementation
* Extend Rome P2P channel limit to multinode and alltoall kernels
* topo_expl: fix compilation and sync up with main
* gtest: use RCCL alltoallv API
* Code review changes
[ROCm/rccl commit: b871ea3c0c
2020-09-30 16:25:36 -07:00
5ca117d7cd
New TransferBench features ( #273 )
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* Upgrading TransferBench to support pinned CPU memory, expanding functionality, cleaning up env vars
[ROCm/rccl commit: ee262819a7
2020-09-25 12:20:48 -06:00
f6b08ca547
Add rccl bw test script in tools ( #255 )
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[ROCm/rccl commit: bbe233f8c1
2020-09-11 16:59:03 +08:00
03bb6bcb54
Increase minimal channels for gfx908 ( #259 )
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[ROCm/rccl commit: c5cbece6d0
2020-08-26 11:40:11 -07:00
5f49a0e088
Add NPS4 support on some models ( #256 )
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* Add NPS4 support on some models
* Add XML models
[ROCm/rccl commit: 391bbf3f1e
2020-08-19 11:03:20 -07:00
3e4ddd065b
Upgrading various TransferBench features ( #257 )
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[ROCm/rccl commit: ec9af40fcd
2020-08-19 09:47:19 -06:00
3d5fb8142e
Add another Rome model ( #249 )
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* Add another Rome model
* Add gfx908 4P3L models and support
* Revert "Use cached value for detecting GDR support only once"
This reverts commit 0108a1219da51e4071e3
2020-08-17 10:51:02 -07:00
1a9b00a7fd
Fixes to make TransferBench compile for hipclang ( #254 )
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[ROCm/rccl commit: c985478133
2020-08-13 12:25:28 -06:00
f242a2f0b0
Collect gcnArch and hipDeviceArch_t in XML ( #252 )
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[ROCm/rccl commit: 7e3d8a31cc
2020-08-12 15:48:38 -07:00
26c540abb8
Merge pull request #247 from wenkaidu/rome
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Additional Rome models support
[ROCm/rccl commit: 3c46cb8ad4
2020-08-07 10:56:12 -07:00
f1373612b0
Update rccl_prim_test.cpp ( #246 )
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Adding doublelocalcopy operation and freeing buffer memory at end.
DoubleLocalCopy Patch Added
[ROCm/rccl commit: 390c63cf0d
2020-08-07 08:20:14 -07:00
c9815aaa36
Add more Rome 4P2H models
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[ROCm/rccl commit: 09ef75656a
2020-08-06 18:20:02 +00:00
487f93b83f
Topology tuning for 4P2H on Rome ( #242 )
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* Topology tuning for 4P2H on Rome
* Use ncclTopoIdToIndex
[ROCm/rccl commit: e7a10aa0e4
2020-07-27 11:53:57 -07:00
49c667ac8a
ib-test: support multiple channels ( #241 )
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[ROCm/rccl commit: 8d5fb920b6
2020-07-27 11:03:12 -07:00
e55a3f20ba
add 4 node 8P6L 1 NIC 2nd Hive model
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[ROCm/rccl commit: 2475daafee
2020-07-22 16:27:15 +00:00
b3306d1c13
simplify model definitions in topo expl
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[ROCm/rccl commit: db55afb014
2020-07-22 16:05:53 +00:00
f604fc774e
Add 8P6L multi-node models ( #239 )
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[ROCm/rccl commit: d5f90e19b5
2020-07-21 14:10:36 -07:00
3e2c9054cd
Change default channels duplication for chordal ring ( #233 )
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[ROCm/rccl commit: ab787c767e
2020-07-14 15:16:50 -07:00
3dd54437fe
Adding appropriate references in rccl-prim-test ( #227 )
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Adding appropriate references to rccl-prim-test.
[ROCm/rccl commit: 9bd4c14603
2020-07-06 10:15:03 -06:00
2f99c7bbad
topo_expl: each rank needs to have its own memory for graphs ( #225 )
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[ROCm/rccl commit: d3548cc474
2020-07-01 15:11:02 -07:00
e8da2a0da6
topo_expl: fix broken build ( #224 )
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[ROCm/rccl commit: a6be82f5ab
2020-06-30 11:11:23 -07:00
e7d664200f
Use posix_memalign for network buffer allocation on host memory ( #221 )
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* Use posix_memalign for network buffer allocation on host memory
* ib-test: add ability to specify run iterations
* ib-test: define iterations as multiple of default cycles
* Add checking to posix_memalign return value
[ROCm/rccl commit: 0eb19a563a
2020-06-22 13:06:25 -07:00
2dc0cfcbf5
ib-test: support host memory allocation through posix_memalign ( #220 )
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* ib-test: support host memory allocation through posix_memalign
* ib-test: add missing CUDACHECK to hip calls
[ROCm/rccl commit: dc739c4e70
2020-06-17 16:16:54 -07:00
9ca3176346
Add IB/RDMA unit test
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[ROCm/rccl commit: cfa97eccd3
2020-06-16 18:29:17 +00:00
Wenkai Du
Gilbert Lee
gilbertlee-amd
Wenkai Du
lijietang
MurtadhaAldallal
Sourav Chakraborty
Stanley Tsang