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33 Commits

Author SHA1 Message Date
German b5b078e036 SWDEV-377991 - Remove liquidflash support 
Change-Id: Iba6455e5c0210c3223a06fec332404cd9f489154


[ROCm/clr commit: 53a10c9039]
 2023-01-20 09:57:06 -05:00
German 7e82b5c716 SWDEV-377991 - Remove liquidflash support 
Change-Id: I8ea0feb6067387f1b545a7492b6bcb55e82ec8b0


[ROCm/clr commit: 3690ae8464]
 2023-01-19 11:39:10 -05:00
German f399cfd045 SWDEV-377991 - Rmove Liquidflash logic 
Untie extra dependency on opencl repo

Change-Id: I8069cd8337214043d3c1453e3dfb0a0a47a83251


[ROCm/clr commit: 5a42279a65]
 2023-01-19 09:58:31 -05:00
kjayapra-amd e295beb8ba SWDEV-371904 - Adding pseudo fine grain flag to hsa memory allocation for device fine grained memory. 
Change-Id: I8cada90f0e3880dfbc5bf5a3fac4554e7a0cb08e


[ROCm/clr commit: e56a611b92]
 2022-12-11 08:15:17 -05:00
kjayapra-amd f8da1e1fc4 SWDEV-361374 - Adding support for hipPointerSetAttributes 
Change-Id: I3ec9627f43b3cbe0aa299c8aa9cd96f8fbd74925


[ROCm/clr commit: 7f1fb925ff]
 2022-11-11 12:07:26 -05:00
Saleel Kudchadker 7fd80925cd SWDEV-335626 - Use ROCr copy for IPC 
Detect IPC buffer and use ROCr copy api instead of blit

Change-Id: Ie6bdd6fc45dbd7457611011d81570b53d5fd5276


[ROCm/clr commit: faaa41aab8]
 2022-07-08 13:32:19 -04:00
Jaydeep e146b7812e SWDEV-332607 - If pitch returned from hipMallocPitch is equal to pitch passed to hipMemset2D then height passed to hipMemset2D must be less than or equal to height passed to hipMallocPitch. 
Change-Id: I8d9b0938fb592170008aaec9cedd519bf40c6201


[ROCm/clr commit: ea0590d1fe]
 2022-06-17 10:35:22 -04:00
Sarbojit Sarkar 8f863abe02 SWDEV-325379 - Fix for remote copy crash 
Change-Id: I22152c0b3538cf7cfc80f82505bc255c01d98f7b


[ROCm/clr commit: 356e22f910]
 2022-06-16 23:59:11 -04:00
Rakesh Roy 52f85f8475 SWDEV-333598 - Add flags field in amd::Memory UserData 
Change-Id: Ie4d59fa34486679fde1027dd113573bda3e7c65c


[ROCm/clr commit: ac2c3b5cad]
 2022-05-05 12:24:53 -04:00
Christophe Paquot 1024cb58a7 SWDEV-322620 - Virtual Memory Management 
Adding virtual memory management APIs to rocclr.
The HIP layer will handle virtual allocs on devices.

Change-Id: Ia978f105c2c3fed3959c77580ba228e845105754


[ROCm/clr commit: b5f555f9ec]
 2022-04-15 00:10:02 -04:00
Christophe Paquot 0f954adf29 SWDEV-322620 - Virtual Memory Management Part 1 
Adding opaque data handle to memory. This is used to look back the HIP object associated with it.

Change-Id: I1bbb14a915bed79c6c3593a29a627778c7aaf13a


[ROCm/clr commit: 867346520f]
 2022-03-31 21:12:26 -04:00
German Andryeyev 2f380870df SWDEV-328670 - Enable arena for ROCr interops 
Add ROCR memory detection and enable arena mem object for possible
access in HIP

Change-Id: Icf86ac789176bfee4ea8d36b0970a817d4c6a2f7


[ROCm/clr commit: 28597ec5b5]
 2022-03-30 16:46:36 -04:00
German Andryeyev c52280ae72 SWDEV-323702 - Use active queue for transfer 
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock

Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de


[ROCm/clr commit: 95d55fdfa8]
 2022-02-18 09:10:53 -05:00
Sarbojit Sarkar c8a6920b91 SWDEV-310181 - Fix for AtoH Memcpy tests failure 
Change-Id: Ibf8c8c01257f0516088d50d5c9f82040ed8fa067


[ROCm/clr commit: 02dc6f9f9a]
 2021-11-29 22:55:23 -05:00
Satyanvesh Dittakavi 1caf1e4936 SWDEV-292714 - Add unique id for each allocation to support HIP_POINTER_ATTRIBUTE_BUFFER_ID 
Change-Id: Ibb3fcb2d0bbbef03525fc884d5b3e9b5f6c11423


[ROCm/clr commit: c56317b2e0]
 2021-11-24 06:10:50 -05:00
agunashe 38f3c7aea1 SWDEV-301069 - current device id saved while allocating memory in VDI 
Change-Id: Ic5426895fb1d152e4e6e1baf8b938f35c85fa3d8


[ROCm/clr commit: 82e73c096b]
 2021-09-16 14:00:07 -04:00
kjayapra-amd c3e74a54e3 SWDEV-295144 - Change uint64_t to size_t to fix failure on 32-bit opencl. 
Change-Id: I5c28e9c606dec1c956f3f48071d8a0271adfff22


[ROCm/clr commit: 788ae8595b]
 2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 04e5354d88 SWDEV-292021 - Fix Device Reset 
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041


[ROCm/clr commit: 924695fb5e]
 2021-08-22 23:56:08 -07:00
kjayapra-amd 282866139f SWDEV-295144 - Typecast arena mem ptr(0x2) to void*, otherwise results in wrong constructor overload. 
Change-Id: I433b70dc70377ae0c5f9b29818703e1ac9d95053


[ROCm/clr commit: e01a24d8b5]
 2021-08-22 23:56:07 -07:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
kjayapra-amd aae0d4ca51 SWDEV-286346 - Implement Arena Memory Object for externally created memory. 
Change-Id: I8530602d89edf83ad367c52167e48a1559ee1e18


[ROCm/clr commit: 1c49d8816c]
 2021-05-18 10:59:52 -04:00
Jason Tang 318c9e1080 SWDEV-1 - Fix warnings when building with clang++ 
Change-Id: Idebd2b618b9a3360147984a0e33852dbe2e65818


[ROCm/clr commit: 0d47b06928]
 2021-02-18 10:02:46 -05:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write 
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
 2021-02-15 17:02:38 -08:00
German Andryeyev 6a6549e474 Add image view allocation 
If deferred allocation is disabled, then make sure the image view
is created without a delay. Also reset the allocation state, since
create() method isn't called for a view creation.

Change-Id: I7aa22a62bff18289ade83e56b5d3305ba68c715b


[ROCm/clr commit: 089a5cc4ad]
 2020-11-18 09:37:30 -05:00
Jason Tang 091f1e8e85 Change file mode 755 back to 644 
Change-Id: I4ba5d66997ffd3331c56674d4bf805160dcdf049


[ROCm/clr commit: 25cc965c76]
 2020-10-19 15:09:32 -04:00
Laurent Morichetti c863b2074b Use std::atomic 
Replace amd::Atomic with std::atomic. Remove make_atomic uses by
converting the variable to std::atomic and making sure the memory
order is relaxed when synchronizes-with is not needed.

Delete utils/atomic.hpp.

Change-Id: I0b36db8d604a8510ac6e36b32885fd16a1b8ccfa


[ROCm/clr commit: 5d4b6f74d3]
 2020-09-09 14:55:29 -04:00
Tao Sang 44eb207f8d Apply constexpr on global constant varaibles 
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef


[ROCm/clr commit: fdef6f722f]
 2020-07-22 22:14:13 -04:00
kjayapra-amd adb0ce1c43 SWDEV-240165 - Move all amd::MemObjMap_ reference to ROCclr and only allow base ptr to get ipc handle. 
Change-Id: I9de10a0c4ba4dee3b3c8b972966840ab807001d8


[ROCm/clr commit: 16e6b65b5c]
 2020-07-09 21:19:45 -04:00
Tao Sang ce1baf5d04 Support numa policy set by user 
Add CL_MEM_FOLLOW_USER_NUMA_POLICY

Change-Id: I90a19dac7641827dff2ceb9ef8ae5f3467ed87a1


[ROCm/clr commit: 53264a8a4a]
 2020-06-19 18:16:47 -04:00
Tao Sang 7ab0bcb3b6 Make hipHostMalloc() respect hipSetDevice() 
Change-Id: Ibdb666fe8dd049735df2288878501a66f7eedc28


[ROCm/clr commit: db10d42e50]
 2020-06-12 18:32:10 -04:00
Laurent Morichetti b3297f189d Replace cl_* integral types with standard types. 
cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t

Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58


[ROCm/clr commit: d9d9c69399]
 2020-02-12 13:16:06 -08:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00